Lines Matching refs:which

10     which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
13     which generates clocks for LLI (Low Latency Interface) IP.
15     which generates clocks for DRAM Memory Controller domain.
17     which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
19     which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
21     which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
23     which generates clocks for G2D/MDMA IPs.
25     which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
27     which generates clocks for Cortex-A5/BUS/AUDIO clocks.
30     which generates global data buses clock and global peripheral buses clock.
32     which generates clocks for 3D Graphics Engine IP.
34     which generates clocks for GSCALER IPs.
36     which generates clocks for Cortex-A53 Quad-core processor.
38     which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
41     which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
43     which generates clocks for MFC(Multi-Format Codec) IP.
45     which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
47     which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
49     which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
52     which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
54     which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
185 to specify the clock which they consume.