Lines Matching +full:clock +full:-
1 * Samsung Exynos5433 CMU (Clock Management Units)
3 The Exynos5433 clock controller generates and supplies clock to various
8 - compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
28 - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
29 and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
30 which generates global data buses clock and global peripheral buses clock.
31 - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
33 - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
35 - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
36 which generates clocks for Cortex-A53 Quad-core processor.
37 - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
38 which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
40 - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
42 - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
43 which generates clocks for MFC(Multi-Format Codec) IP.
44 - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
46 - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
47 which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
48 - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
51 - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
52 which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
53 - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM
56 - reg: physical base address of the controller and length of memory mapped
59 - #clock-cells: should be 1.
61 - clocks: list of the clock controller input clock identifiers,
62 from common clock bindings. Please refer the next section
65 - clock-names: list of the clock controller input clock names,
66 as described in clock-bindings.txt.
68 Input clocks for top clock controller:
69 - oscclk
70 - sclk_mphy_pll
71 - sclk_mfc_pll
72 - sclk_bus_pll
74 Input clocks for cpif clock controller:
75 - oscclk
77 Input clocks for mif clock controller:
78 - oscclk
79 - sclk_mphy_pll
81 Input clocks for fsys clock controller:
82 - oscclk
83 - sclk_ufs_mphy
84 - aclk_fsys_200
85 - sclk_pcie_100_fsys
86 - sclk_ufsunipro_fsys
87 - sclk_mmc2_fsys
88 - sclk_mmc1_fsys
89 - sclk_mmc0_fsys
90 - sclk_usbhost30_fsys
91 - sclk_usbdrd30_fsys
93 Input clocks for g2d clock controller:
94 - oscclk
95 - aclk_g2d_266
96 - aclk_g2d_400
98 Input clocks for disp clock controller:
99 - oscclk
100 - sclk_dsim1_disp
101 - sclk_dsim0_disp
102 - sclk_dsd_disp
103 - sclk_decon_tv_eclk_disp
104 - sclk_decon_vclk_disp
105 - sclk_decon_eclk_disp
106 - sclk_decon_tv_vclk_disp
107 - aclk_disp_333
109 Input clocks for audio clock controller:
110 - oscclk
111 - fout_aud_pll
113 Input clocks for bus0 clock controller:
114 - aclk_bus0_400
116 Input clocks for bus1 clock controller:
117 - aclk_bus1_400
119 Input clocks for bus2 clock controller:
120 - oscclk
121 - aclk_bus2_400
123 Input clocks for g3d clock controller:
124 - oscclk
125 - aclk_g3d_400
127 Input clocks for gscl clock controller:
128 - oscclk
129 - aclk_gscl_111
130 - aclk_gscl_333
132 Input clocks for apollo clock controller:
133 - oscclk
134 - sclk_bus_pll_apollo
136 Input clocks for atlas clock controller:
137 - oscclk
138 - sclk_bus_pll_atlas
140 Input clocks for mscl clock controller:
141 - oscclk
142 - sclk_jpeg_mscl
143 - aclk_mscl_400
145 Input clocks for mfc clock controller:
146 - oscclk
147 - aclk_mfc_400
149 Input clocks for hevc clock controller:
150 - oscclk
151 - aclk_hevc_400
153 Input clocks for isp clock controller:
154 - oscclk
155 - aclk_isp_dis_400
156 - aclk_isp_400
158 Input clocks for cam0 clock controller:
159 - oscclk
160 - aclk_cam0_333
161 - aclk_cam0_400
162 - aclk_cam0_552
164 Input clocks for cam1 clock controller:
165 - oscclk
166 - sclk_isp_uart_cam1
167 - sclk_isp_spi1_cam1
168 - sclk_isp_spi0_cam1
169 - aclk_cam1_333
170 - aclk_cam1_400
171 - aclk_cam1_552
173 Input clocks for imem clock controller:
174 - oscclk
175 - aclk_imem_sssx_266
176 - aclk_imem_266
177 - aclk_imem_200
180 - power-domains: a phandle to respective power domain node as described by
184 Each clock is assigned an identifier and client nodes can use this identifier
185 to specify the clock which they consume.
188 dt-bindings/clock/exynos5433.h header and can be used in device
191 Example 1: Examples of 'oscclk' source clock node are listed below.
194 compatible = "fixed-clock";
195 clock-output-names = "oscclk";
196 #clock-cells = <0>;
199 Example 2: Examples of clock controller nodes are listed below.
201 cmu_top: clock-controller@10030000 {
202 compatible = "samsung,exynos5433-cmu-top";
204 #clock-cells = <1>;
206 clock-names = "oscclk",
216 cmu_cpif: clock-controller@10fc0000 {
217 compatible = "samsung,exynos5433-cmu-cpif";
219 #clock-cells = <1>;
221 clock-names = "oscclk";
225 cmu_mif: clock-controller@105b0000 {
226 compatible = "samsung,exynos5433-cmu-mif";
228 #clock-cells = <1>;
230 clock-names = "oscclk",
236 cmu_peric: clock-controller@14c80000 {
237 compatible = "samsung,exynos5433-cmu-peric";
239 #clock-cells = <1>;
242 cmu_peris: clock-controller@10040000 {
243 compatible = "samsung,exynos5433-cmu-peris";
245 #clock-cells = <1>;
248 cmu_fsys: clock-controller@156e0000 {
249 compatible = "samsung,exynos5433-cmu-fsys";
251 #clock-cells = <1>;
253 clock-names = "oscclk",
275 cmu_g2d: clock-controller@12460000 {
276 compatible = "samsung,exynos5433-cmu-g2d";
278 #clock-cells = <1>;
280 clock-names = "oscclk",
286 power-domains = <&pd_g2d>;
289 cmu_disp: clock-controller@13b90000 {
290 compatible = "samsung,exynos5433-cmu-disp";
292 #clock-cells = <1>;
294 clock-names = "oscclk",
312 power-domains = <&pd_disp>;
315 cmu_aud: clock-controller@114c0000 {
316 compatible = "samsung,exynos5433-cmu-aud";
318 #clock-cells = <1>;
320 clock-names = "oscclk", "fout_aud_pll";
322 power-domains = <&pd_aud>;
325 cmu_bus0: clock-controller@13600000 {
326 compatible = "samsung,exynos5433-cmu-bus0";
328 #clock-cells = <1>;
330 clock-names = "aclk_bus0_400";
334 cmu_bus1: clock-controller@14800000 {
335 compatible = "samsung,exynos5433-cmu-bus1";
337 #clock-cells = <1>;
339 clock-names = "aclk_bus1_400";
343 cmu_bus2: clock-controller@13400000 {
344 compatible = "samsung,exynos5433-cmu-bus2";
346 #clock-cells = <1>;
348 clock-names = "oscclk", "aclk_bus2_400";
352 cmu_g3d: clock-controller@14aa0000 {
353 compatible = "samsung,exynos5433-cmu-g3d";
355 #clock-cells = <1>;
357 clock-names = "oscclk", "aclk_g3d_400";
359 power-domains = <&pd_g3d>;
362 cmu_gscl: clock-controller@13cf0000 {
363 compatible = "samsung,exynos5433-cmu-gscl";
365 #clock-cells = <1>;
367 clock-names = "oscclk",
373 power-domains = <&pd_gscl>;
376 cmu_apollo: clock-controller@11900000 {
377 compatible = "samsung,exynos5433-cmu-apollo";
379 #clock-cells = <1>;
381 clock-names = "oscclk", "sclk_bus_pll_apollo";
385 cmu_atlas: clock-controller@11800000 {
386 compatible = "samsung,exynos5433-cmu-atlas";
388 #clock-cells = <1>;
390 clock-names = "oscclk", "sclk_bus_pll_atlas";
394 cmu_mscl: clock-controller@105d0000 {
395 compatible = "samsung,exynos5433-cmu-mscl";
397 #clock-cells = <1>;
399 clock-names = "oscclk",
405 power-domains = <&pd_mscl>;
408 cmu_mfc: clock-controller@15280000 {
409 compatible = "samsung,exynos5433-cmu-mfc";
411 #clock-cells = <1>;
413 clock-names = "oscclk", "aclk_mfc_400";
415 power-domains = <&pd_mfc>;
418 cmu_hevc: clock-controller@14f80000 {
419 compatible = "samsung,exynos5433-cmu-hevc";
421 #clock-cells = <1>;
423 clock-names = "oscclk", "aclk_hevc_400";
425 power-domains = <&pd_hevc>;
428 cmu_isp: clock-controller@146d0000 {
429 compatible = "samsung,exynos5433-cmu-isp";
431 #clock-cells = <1>;
433 clock-names = "oscclk",
439 power-domains = <&pd_isp>;
442 cmu_cam0: clock-controller@120d0000 {
443 compatible = "samsung,exynos5433-cmu-cam0";
445 #clock-cells = <1>;
447 clock-names = "oscclk",
455 power-domains = <&pd_cam0>;
458 cmu_cam1: clock-controller@145d0000 {
459 compatible = "samsung,exynos5433-cmu-cam1";
461 #clock-cells = <1>;
463 clock-names = "oscclk",
477 power-domains = <&pd_cam1>;
480 cmu_imem: clock-controller@11060000 {
481 compatible = "samsung,exynos5433-cmu-imem";
483 #clock-cells = <1>;
485 clock-names = "oscclk",
495 Example 3: UART controller node that consumes the clock generated by the clock
499 compatible = "samsung,exynos5433-uart";
504 clock-names = "uart", "clk_uart_baud0";
505 pinctrl-names = "default";
506 pinctrl-0 = <&uart0_bus>;