Lines Matching full:clock
1 * Samsung Exynos5433 CMU (Clock Management Units)
3 The Exynos5433 clock controller generates and supplies clock to various
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
29 and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
30 which generates global data buses clock and global peripheral buses clock.
31 - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
33 - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
35 - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
37 - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
40 - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
42 - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
44 - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
46 - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
48 - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
51 - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
53 - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM
59 - #clock-cells: should be 1.
61 - clocks: list of the clock controller input clock identifiers,
62 from common clock bindings. Please refer the next section
65 - clock-names: list of the clock controller input clock names,
66 as described in clock-bindings.txt.
68 Input clocks for top clock controller:
74 Input clocks for cpif clock controller:
77 Input clocks for mif clock controller:
81 Input clocks for fsys clock controller:
93 Input clocks for g2d clock controller:
98 Input clocks for disp clock controller:
109 Input clocks for audio clock controller:
113 Input clocks for bus0 clock controller:
116 Input clocks for bus1 clock controller:
119 Input clocks for bus2 clock controller:
123 Input clocks for g3d clock controller:
127 Input clocks for gscl clock controller:
132 Input clocks for apollo clock controller:
136 Input clocks for atlas clock controller:
140 Input clocks for mscl clock controller:
145 Input clocks for mfc clock controller:
149 Input clocks for hevc clock controller:
153 Input clocks for isp clock controller:
158 Input clocks for cam0 clock controller:
164 Input clocks for cam1 clock controller:
173 Input clocks for imem clock controller:
184 Each clock is assigned an identifier and client nodes can use this identifier
185 to specify the clock which they consume.
188 dt-bindings/clock/exynos5433.h header and can be used in device
191 Example 1: Examples of 'oscclk' source clock node are listed below.
194 compatible = "fixed-clock";
195 clock-output-names = "oscclk";
196 #clock-cells = <0>;
199 Example 2: Examples of clock controller nodes are listed below.
201 cmu_top: clock-controller@10030000 {
204 #clock-cells = <1>;
206 clock-names = "oscclk",
216 cmu_cpif: clock-controller@10fc0000 {
219 #clock-cells = <1>;
221 clock-names = "oscclk";
225 cmu_mif: clock-controller@105b0000 {
228 #clock-cells = <1>;
230 clock-names = "oscclk",
236 cmu_peric: clock-controller@14c80000 {
239 #clock-cells = <1>;
242 cmu_peris: clock-controller@10040000 {
245 #clock-cells = <1>;
248 cmu_fsys: clock-controller@156e0000 {
251 #clock-cells = <1>;
253 clock-names = "oscclk",
275 cmu_g2d: clock-controller@12460000 {
278 #clock-cells = <1>;
280 clock-names = "oscclk",
289 cmu_disp: clock-controller@13b90000 {
292 #clock-cells = <1>;
294 clock-names = "oscclk",
315 cmu_aud: clock-controller@114c0000 {
318 #clock-cells = <1>;
320 clock-names = "oscclk", "fout_aud_pll";
325 cmu_bus0: clock-controller@13600000 {
328 #clock-cells = <1>;
330 clock-names = "aclk_bus0_400";
334 cmu_bus1: clock-controller@14800000 {
337 #clock-cells = <1>;
339 clock-names = "aclk_bus1_400";
343 cmu_bus2: clock-controller@13400000 {
346 #clock-cells = <1>;
348 clock-names = "oscclk", "aclk_bus2_400";
352 cmu_g3d: clock-controller@14aa0000 {
355 #clock-cells = <1>;
357 clock-names = "oscclk", "aclk_g3d_400";
362 cmu_gscl: clock-controller@13cf0000 {
365 #clock-cells = <1>;
367 clock-names = "oscclk",
376 cmu_apollo: clock-controller@11900000 {
379 #clock-cells = <1>;
381 clock-names = "oscclk", "sclk_bus_pll_apollo";
385 cmu_atlas: clock-controller@11800000 {
388 #clock-cells = <1>;
390 clock-names = "oscclk", "sclk_bus_pll_atlas";
394 cmu_mscl: clock-controller@105d0000 {
397 #clock-cells = <1>;
399 clock-names = "oscclk",
408 cmu_mfc: clock-controller@15280000 {
411 #clock-cells = <1>;
413 clock-names = "oscclk", "aclk_mfc_400";
418 cmu_hevc: clock-controller@14f80000 {
421 #clock-cells = <1>;
423 clock-names = "oscclk", "aclk_hevc_400";
428 cmu_isp: clock-controller@146d0000 {
431 #clock-cells = <1>;
433 clock-names = "oscclk",
442 cmu_cam0: clock-controller@120d0000 {
445 #clock-cells = <1>;
447 clock-names = "oscclk",
458 cmu_cam1: clock-controller@145d0000 {
461 #clock-cells = <1>;
463 clock-names = "oscclk",
480 cmu_imem: clock-controller@11060000 {
483 #clock-cells = <1>;
485 clock-names = "oscclk",
495 Example 3: UART controller node that consumes the clock generated by the clock
504 clock-names = "uart", "clk_uart_baud0";