Lines Matching +full:pll +full:-

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11   - Serge Semin <fancer.lancer@gmail.com>
14   Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18   IP-blocks or to groups of blocks (clock domains). The transformation is done
19   by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23   2) PLLs clocks generators (PLLs) - described in this binding file.
24   3) AXI-bus clock dividers (AXI).
28           +---------------+
29           | Baikal-T1 CCU |
30           |   +----+------|- MIPS P5600 cores
31           | +-|PLLs|------|- DDR controller
32           | | +----+      |
33   +----+  | |  |  |       |
34   |XTAL|--|-+  |  | +---+-|
35   +----+  | |  |  +-|AXI|-|- AXI-bus
36           | |  |    +---+-|
38           | |  +----+---+-|- APB-bus
39           | +-------|SYS|-|- Low-speed Devices
40           |         +---+-|- High-speed Devices
41           +---------------+
43   Each CCU sub-block is represented as a separate dts-node and has an
52   with an interface wrapper (so called safe PLL' clocks switcher) to simplify
53   the PLL configuration procedure. The PLLs work as depicted on the next
56       +--------------------------+
58       +-->+---+    +---+   +---+ |  +---+   0|\
59   CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
60           +---+ +->+---+   +---+ /->+---+    | |--->CLKOUT
61   CLKOD---------C----------------+          1| |
62        +--------C--------------------------->|/
64   Rclk-+->+---+ |                             |
65   CLKR--->|/NR|-+                             |
66           +---+                               |
67   BYPASS--------------------------------------+
68   BWADJ--->
70   where Rclk is the reference clock coming  from XTAL, NR - reference clock
71   divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
72   output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
73   the binding supports the PLL dividers configuration in accordance with a
81   The CCU PLL dts-node uses the common clock bindings with no custom
83   'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
84   Baikal-T1 SoC System Controller its DT node is supposed to be a child of
89     const: baikal,bt1-ccu-pll
94   "#clock-cells":
101   clock-names:
107   - compatible
108   - "#clock-cells"
109   - clocks
110   - clock-names
113   # Clock Control Unit PLL node:
114   - |
115     clock-controller@1f04d000 {
116       compatible = "baikal,bt1-ccu-pll";
118       #clock-cells = <1>;
121       clock-names = "ref_clk";
124   - |
125     clk25m: clock-oscillator-25m {
126       compatible = "fixed-clock";
127       #clock-cells = <0>;
128       clock-frequency = <25000000>;
129       clock-output-names = "clk25m";