Lines Matching +full:gxbb +full:- +full:clkc

1 * Amlogic GXBB AO Clock and Reset Unit
3 The Amlogic GXBB AO clock controller generates and supplies clock to various
4 controllers within the Always-On part of the SoC.
8 - compatible: value should be different for each SoC family as :
9 	- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
10 	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
11 	- GXM (S912) : "amlogic,meson-gxm-aoclkc"
12 	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
13 	- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
14 	followed by the common "amlogic,meson-gx-aoclkc"
15 - clocks: list of clock phandle, one for each entry clock-names.
16 - clock-names: should contain the following:
18   * "mpeg-clk" : the main clock controller mother clock (aka clk81)
19   * "ext-32k-0"  : external 32kHz reference #0 if any (optional)
20   * "ext-32k-1"  : external 32kHz reference #1 if any (optional - gx only)
21   * "ext-32k-2"  : external 32kHz reference #2 if any (optional - gx only)
23 - #clock-cells: should be 1.
27 preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
30 - #reset-cells: should be 1.
34 preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
38 - compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
39 - reg: base address and size of the AO system control register space.
43 ao_sysctrl: sys-ctrl@0 {
44 	compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
47 	clkc_AO: clock-controller {
48 		compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
49 		#clock-cells = <1>;
50 		#reset-cells = <1>;
51 		clocks = <&xtal>, <&clkc CLKID_CLK81>;
52 		clock-names = "xtal", "mpeg-clk";
59 		compatible = "amlogic,meson-uart";