Lines Matching +full:cache +full:- +full:controller +full:- +full:0
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Composable Cache Controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 The SiFive Composable Cache Controller is used to provide access to fast copies
15 of memory for masters in a Core Complex. The Composable Cache Controller also
16 acts as directory-based coherency manager.
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
29 - compatible
34 - items:
35 - enum:
36 - sifive,ccache0
37 - sifive,fu540-c000-ccache
38 - sifive,fu740-c000-ccache
39 - const: cache
40 - items:
41 - enum:
42 - starfive,jh7100-ccache
43 - starfive,jh7110-ccache
44 - const: sifive,ccache0
45 - const: cache
46 - items:
47 - const: microchip,mpfs-ccache
48 - const: sifive,fu540-c000-ccache
49 - const: cache
51 cache-block-size:
54 cache-level:
57 cache-sets:
60 cache-size:
63 cache-unified: true
68 - description: DirError interrupt
69 - description: DataError interrupt
70 - description: DataFail interrupt
71 - description: DirFail interrupt
76 next-level-cache: true
78 memory-region:
81 The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
82 The reserved memory node should be defined as per the bindings in reserved-memory.txt.
85 - $ref: /schemas/cache-controller.yaml#
87 - if:
92 - sifive,fu740-c000-ccache
93 - starfive,jh7100-ccache
94 - starfive,jh7110-ccache
95 - microchip,mpfs-ccache
111 - if:
116 - sifive,fu740-c000-ccache
117 - starfive,jh7100-ccache
118 - starfive,jh7110-ccache
122 cache-sets:
127 cache-sets:
130 - if:
138 cache-level:
143 cache-level:
149 - compatible
150 - cache-block-size
151 - cache-level
152 - cache-sets
153 - cache-size
154 - cache-unified
155 - interrupts
156 - reg
159 - |
160 cache-controller@2010000 {
161 compatible = "sifive,fu540-c000-ccache", "cache";
162 cache-block-size = <64>;
163 cache-level = <2>;
164 cache-sets = <1024>;
165 cache-size = <2097152>;
166 cache-unified;
167 reg = <0x2010000 0x1000>;
168 interrupt-parent = <&plic0>;
172 next-level-cache = <&L25>;
173 memory-region = <&l2_lim>;