Lines Matching +full:system +full:- +full:cache +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Last Level Cache Controller
10 - Bjorn Andersson <andersson@kernel.org>
13 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
16 common pool of memory. Cache memory is divided into partitions called slices
23 - qcom,qdu1000-llcc
24 - qcom,sc7180-llcc
25 - qcom,sc7280-llcc
26 - qcom,sc8180x-llcc
27 - qcom,sc8280xp-llcc
28 - qcom,sdm845-llcc
29 - qcom,sm6350-llcc
30 - qcom,sm7150-llcc
31 - qcom,sm8150-llcc
32 - qcom,sm8250-llcc
33 - qcom,sm8350-llcc
34 - qcom,sm8450-llcc
35 - qcom,sm8550-llcc
36 - qcom,sm8650-llcc
37 - qcom,x1e80100-llcc
43 reg-names:
50 nvmem-cells:
52 - description: Reference to an nvmem node for multi channel DDR
54 nvmem-cell-names:
56 - const: multi-chan-ddr
59 - compatible
60 - reg
61 - reg-names
64 - if:
69 - qcom,qdu1000-llcc
70 - qcom,sc7180-llcc
71 - qcom,sm6350-llcc
76 - description: LLCC0 base register region
77 - description: LLCC broadcast base register region
78 reg-names:
80 - const: llcc0_base
81 - const: llcc_broadcast_base
83 - if:
88 - qcom,sc7280-llcc
93 - description: LLCC0 base register region
94 - description: LLCC1 base register region
95 - description: LLCC broadcast base register region
96 reg-names:
98 - const: llcc0_base
99 - const: llcc1_base
100 - const: llcc_broadcast_base
102 - if:
107 - qcom,sc8180x-llcc
108 - qcom,sc8280xp-llcc
109 - qcom,x1e80100-llcc
114 - description: LLCC0 base register region
115 - description: LLCC1 base register region
116 - description: LLCC2 base register region
117 - description: LLCC3 base register region
118 - description: LLCC4 base register region
119 - description: LLCC5 base register region
120 - description: LLCC6 base register region
121 - description: LLCC7 base register region
122 - description: LLCC broadcast base register region
123 reg-names:
125 - const: llcc0_base
126 - const: llcc1_base
127 - const: llcc2_base
128 - const: llcc3_base
129 - const: llcc4_base
130 - const: llcc5_base
131 - const: llcc6_base
132 - const: llcc7_base
133 - const: llcc_broadcast_base
135 - if:
140 - qcom,sdm845-llcc
141 - qcom,sm8150-llcc
142 - qcom,sm8250-llcc
143 - qcom,sm8350-llcc
144 - qcom,sm8450-llcc
145 - qcom,sm8550-llcc
150 - description: LLCC0 base register region
151 - description: LLCC1 base register region
152 - description: LLCC2 base register region
153 - description: LLCC3 base register region
154 - description: LLCC broadcast base register region
155 reg-names:
157 - const: llcc0_base
158 - const: llcc1_base
159 - const: llcc2_base
160 - const: llcc3_base
161 - const: llcc_broadcast_base
166 - |
167 #include <dt-bindings/interrupt-controller/arm-gic.h>
170 #address-cells = <2>;
171 #size-cells = <2>;
173 system-cache-controller@1100000 {
174 compatible = "qcom,sdm845-llcc";
178 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",