Lines Matching +full:soc +full:- +full:nvmem
1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
13 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
15 SoC, the idea is to minimize the local caches at the clients and migrate to
23 - qcom,qdu1000-llcc
24 - qcom,sa8775p-llcc
25 - qcom,sc7180-llcc
26 - qcom,sc7280-llcc
27 - qcom,sc8180x-llcc
28 - qcom,sc8280xp-llcc
29 - qcom,sdm845-llcc
30 - qcom,sm6350-llcc
31 - qcom,sm7150-llcc
32 - qcom,sm8150-llcc
33 - qcom,sm8250-llcc
34 - qcom,sm8350-llcc
35 - qcom,sm8450-llcc
36 - qcom,sm8550-llcc
37 - qcom,sm8650-llcc
38 - qcom,x1e80100-llcc
44 reg-names:
51 nvmem-cells:
53 - description: Reference to an nvmem node for multi channel DDR
55 nvmem-cell-names:
57 - const: multi-chan-ddr
60 - compatible
61 - reg
62 - reg-names
65 - if:
70 - qcom,sc7180-llcc
71 - qcom,sm6350-llcc
76 - description: LLCC0 base register region
77 - description: LLCC broadcast base register region
78 reg-names:
80 - const: llcc0_base
81 - const: llcc_broadcast_base
83 - if:
88 - qcom,sa8775p-llcc
93 - description: LLCC0 base register region
94 - description: LLCC1 base register region
95 - description: LLCC2 base register region
96 - description: LLCC3 base register region
97 - description: LLCC4 base register region
98 - description: LLCC5 base register region
99 - description: LLCC broadcast base register region
100 reg-names:
102 - const: llcc0_base
103 - const: llcc1_base
104 - const: llcc2_base
105 - const: llcc3_base
106 - const: llcc4_base
107 - const: llcc5_base
108 - const: llcc_broadcast_base
110 - if:
115 - qcom,sc7280-llcc
120 - description: LLCC0 base register region
121 - description: LLCC1 base register region
122 - description: LLCC broadcast base register region
123 reg-names:
125 - const: llcc0_base
126 - const: llcc1_base
127 - const: llcc_broadcast_base
129 - if:
134 - qcom,qdu1000-llcc
135 - qcom,sc8180x-llcc
136 - qcom,sc8280xp-llcc
137 - qcom,x1e80100-llcc
142 - description: LLCC0 base register region
143 - description: LLCC1 base register region
144 - description: LLCC2 base register region
145 - description: LLCC3 base register region
146 - description: LLCC4 base register region
147 - description: LLCC5 base register region
148 - description: LLCC6 base register region
149 - description: LLCC7 base register region
150 - description: LLCC broadcast base register region
151 reg-names:
153 - const: llcc0_base
154 - const: llcc1_base
155 - const: llcc2_base
156 - const: llcc3_base
157 - const: llcc4_base
158 - const: llcc5_base
159 - const: llcc6_base
160 - const: llcc7_base
161 - const: llcc_broadcast_base
163 - if:
168 - qcom,sdm845-llcc
169 - qcom,sm8150-llcc
170 - qcom,sm8250-llcc
171 - qcom,sm8350-llcc
176 - description: LLCC0 base register region
177 - description: LLCC1 base register region
178 - description: LLCC2 base register region
179 - description: LLCC3 base register region
180 - description: LLCC broadcast base register region
181 reg-names:
183 - const: llcc0_base
184 - const: llcc1_base
185 - const: llcc2_base
186 - const: llcc3_base
187 - const: llcc_broadcast_base
189 - if:
194 - qcom,sm8450-llcc
195 - qcom,sm8550-llcc
196 - qcom,sm8650-llcc
201 - description: LLCC0 base register region
202 - description: LLCC1 base register region
203 - description: LLCC2 base register region
204 - description: LLCC3 base register region
205 - description: LLCC broadcast OR register region
206 - description: LLCC broadcast AND register region
207 reg-names:
209 - const: llcc0_base
210 - const: llcc1_base
211 - const: llcc2_base
212 - const: llcc3_base
213 - const: llcc_broadcast_base
214 - const: llcc_broadcast_and_base
219 - |
220 #include <dt-bindings/interrupt-controller/arm-gic.h>
222 soc {
223 #address-cells = <2>;
224 #size-cells = <2>;
226 system-cache-controller@1100000 {
227 compatible = "qcom,sdm845-llcc";
231 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",