Lines Matching +full:lock +full:- +full:offset
2 ------------------------------------
9 more configuration registers often protected by a lock register where one or
10 more key values must be written to a lock register in order to unlock the
24 - compatible: must be "ti,c64x+dscr"
25 - reg: register area base and size
34 - ti,dscr-devstat
35 offset of the devstat register
37 - ti,dscr-silicon-rev
38 offset, start bit, and bitsize of silicon revision field
40 - ti,dscr-rmii-resets
41 offset and bitmask of RMII reset field. May have multiple tuples if more
44 - ti,dscr-locked-regs
46 a lock register. Each tuple consists of the register offset, lock register
49 - ti,dscr-kick-regs
50 offset and key values of two "kick" registers used to write protect other
53 the second register before other registers in the area are write-enabled.
55 - ti,dscr-mac-fuse-regs
58 a register offset and four cells representing bytes in the register from
60 index (1-6) of the byte within the register. A value of 0 means the byte
63 - ti,dscr-devstate-ctl-regs
73 reg is the offset of the register holding the control bits
79 - ti,dscr-devstate-stat-regs
90 reg is the offset of the register holding the status bits
96 - ti,dscr-privperm
97 Offset and default value for register used to set access privilege for
103 device-state-config-regs@2a80000 {
107 ti,dscr-devstat = <0>;
108 ti,dscr-silicon-rev = <8 28 0xf>;
109 ti,dscr-rmii-resets = <0x40020 0x00040000>;
111 ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
112 ti,dscr-devstate-ctl-regs =
116 ti,dscr-devstate-stat-regs =
120 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
123 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
125 ti,dscr-kick-regs = <0x38 0x83E70B13