Lines Matching +full:interconnect +full:- +full:0
1 Texas Instruments sysc interconnect target module wrapper binding
3 Texas Instruments SoCs can have a generic interconnect target module
5 interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
8 of the interconnect.
10 Each interconnect target module can have one or more devices connected to
11 it. There is a set of control registers for managing interconnect target
12 module clocks, idle modes and interconnect level resets for the module.
15 space of the first child device IP block managed by the interconnect
20 - compatible shall be one of the following generic types:
23 "ti,sysc-omap2"
24 "ti,sysc-omap4"
25 "ti,sysc-omap4-simple"
30 "ti,sysc-omap2-timer"
31 "ti,sysc-omap4-timer"
32 "ti,sysc-omap3430-sr"
33 "ti,sysc-omap3630-sr"
34 "ti,sysc-omap4-sr"
35 "ti,sysc-omap3-sham"
36 "ti,sysc-omap-aes"
37 "ti,sysc-mcasp"
38 "ti,sysc-dra7-mcasp"
39 "ti,sysc-usb-host-fs"
40 "ti,sysc-dra7-mcan"
41 "ti,sysc-pruss"
43 - reg shall have register areas implemented for the interconnect
46 - reg-names shall contain the register names implemented for the
47 interconnect target module in question such as
50 - ranges shall contain the interconnect target module IO range
52 by the interconnect target module, the ranges may include
58 - ti,sysc-mask shall contain mask of supported register bits for the
60 Manual (TRM) for the interconnect target module
62 - ti,sysc-midle list of master idle modes supported by the interconnect
66 - ti,sysc-sidle list of slave idle modes supported by the interconnect
70 - ti,sysc-delay-us delay needed after OCP softreset before accssing
73 - ti,syss-mask optional mask of reset done status bits as described in the
78 - clocks clock specifier for each name in the clock-names as
79 specified in the binding documentation for ti-clkctrl,
80 typically available for all interconnect targets on TI SoCs
81 based on omap4 except if it's read-only register in hwauto
84 - clock-names should contain at least "fck", and optionally also "ick"
85 depending on the SoC and the interconnect target module,
86 some interconnect target modules also need additional
91 - ti,hwmods optional TI interconnect module name to use legacy
94 - ti,no-reset-on-init interconnect target module should not be reset at init
96 - ti,no-idle-on-init interconnect target module should not be idled at init
98 - ti,no-idle interconnect target module should not be idled
100 Example: Single instance of MUSB controller on omap4 using interconnect ranges
101 using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
103 target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
104 compatible = "ti,sysc-omap2";
106 reg = <0x2b400 0x4>,
107 <0x2b404 0x4>,
108 <0x2b408 0x4>;
109 reg-names = "rev", "sysc", "syss";
110 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
111 clock-names = "fck";
112 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
115 ti,sysc-midle = <SYSC_IDLE_FORCE>,
118 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
122 ti,syss-mask = <1>;
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0x2b000 0x1000>;
127 usb_otg_hs: otg@0 {
128 compatible = "ti,omap4-musb";
129 reg = <0x0 0x7ff>;
132 usb-phy = <&usb2_phy>;
139 instance as children of a single interconnect target module.