Lines Matching +full:0 +full:x1b000000
24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
58 ranges = <0 0x0 0x1a800000 0x00800000>,
59 <1 0x0 0x1b000000 0x00800000>,
60 <2 0x0 0x1b800000 0x00800000>,
61 <3 0x0 0x1d000000 0x08000000>,
62 <4 0x0 0x1c800000 0x00800000>,
63 <5 0x0 0x1c000000 0x00800000>;
80 CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum
81 value is actually 1, so a value of 0 will still yield 1 recovery cycle.
84 WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS
85 stays active for 1 extra cycle etc. Valid values 0 thru 15.
87 the first write to a page or burst memory. Valid values 0 thru 255.
89 first read to a page or burst memory. Valid values 0 thru 255.
90 - qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
91 cycle. Valid values 0 thru 15.
92 - qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
93 cycle. Valid values 0 thru 15.
101 2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
104 assertion to OE assertion. Valid values 0 thru 15.
113 ranges = <0 0x0 0x1a800000 0x00800000>,
114 <1 0x0 0x1b000000 0x00800000>,
115 <2 0x0 0x1b800000 0x00800000>,
116 <3 0x0 0x1d000000 0x08000000>,
117 <4 0x0 0x1c800000 0x00800000>,
118 <5 0x0 0x1c000000 0x00800000>;
119 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
125 pinctrl-0 = <&foo_ebi2_pins>;
127 foo-ebi2@2,0 {
129 reg = <2 0x0 0x100>;
131 qcom,xmem-recovery-cycles = <0>;