Lines Matching +full:clock +full:- +full:mode
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
20 - nvidia,tegra210-pmc
27 clock-names:
29 - const: pclk
30 - const: clk32k_in
33 pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
39 Must contain an entry for each entry in clock-names.
40 See ../clocks/clocks-bindings.txt for details.
42 '#clock-cells':
46 PMC also has blink control which allows 32Khz clock output to
48 Consumer of PMC clock should specify the desired clock by having
49 the clock ID in its "clocks" phandle cell with pmc clock provider.
50 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
51 clock IDs.
53 '#interrupt-cells':
59 interrupt-controller: true
61 nvidia,invert-interrupt:
69 nvidia,core-power-req-active-high:
71 description: Core power request active-high.
73 nvidia,sys-clock-req-active-high:
75 description: System clock request active-high.
77 nvidia,combined-power-req:
81 nvidia,cpu-pwr-good-en:
86 nvidia,suspend-mode:
90 The suspend mode that the platform should use.
91 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
92 Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
93 Mode 2 is for LP2, CPU voltage off
95 nvidia,cpu-pwr-good-time:
99 nvidia,cpu-pwr-off-time:
103 nvidia,core-pwr-good-time:
104 $ref: /schemas/types.yaml#/definitions/uint32-array
106 <Oscillator-stable-time Power-stable-time>
109 nvidia,core-pwr-off-time:
113 nvidia,lp0-vec:
114 $ref: /schemas/types.yaml#/definitions/uint32-array
119 The AVP (Audio-Video Processor) is an ARM7 processor and
121 or resume from deep sleep mode. When the system is resumed
122 from the deep sleep mode, the warm boot code will restore
126 core-supply:
130 core-domain:
138 operating-points-v2:
140 Should contain level, voltages and opp-supported-hw property.
141 The supported-hw is a bitfield indicating SoC speedo or process
144 "#power-domain-cells":
148 - operating-points-v2
149 - "#power-domain-cells"
153 i2c-thermtrip:
156 On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
157 hardware-triggered thermal reset will be enabled.
160 nvidia,i2c-controller-id:
168 nvidia,bus-addr:
172 nvidia,reg-addr:
176 nvidia,reg-data:
180 nvidia,pinmux-id:
188 - nvidia,i2c-controller-id
189 - nvidia,bus-addr
190 - nvidia,reg-addr
191 - nvidia,reg-data
200 represents a power-domain on the Tegra SoC that can be power-gated
203 "power-domains" property that is a phandle pointing to corresponding
208 Please refer to Tegra TRM for mode details on the powergate nodes to
209 use for each power-gate block inside Tegra.
235 "^[a-z0-9]+$":
244 Must contain an entry for each clock required by the PMC
245 for controlling a power-gate.
246 See ../clocks/clock-bindings.txt document for more details.
253 for controlling a power-gate.
256 power-domains:
259 '#power-domain-cells':
264 - clocks
265 - resets
266 - '#power-domain-cells'
271 "^[a-f0-9]+-[a-f0-9]+$":
277 and signaling voltage. A pad can be either in active or power down mode.
285 see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
291 hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
295 audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
296 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
297 hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
298 sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
305 low-power-enable:
307 description: Configure the pad into power down mode.
309 low-power-disable:
311 description: Configure the pad into active mode.
313 power-source:
319 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
323 All of the listed Tegra210 pads except pex-cntrl support power
326 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
327 sdmmc3, spi, spi-hv, and uart.
330 - pins
335 - compatible
336 - reg
337 - clock-names
338 - clocks
339 - '#clock-cells'
344 "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
345 "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
346 "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
349 - |
351 #include <dt-bindings/clock/tegra210-car.h>
352 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
353 #include <dt-bindings/soc/tegra-pmc.h>
356 compatible = "nvidia,tegra210-pmc";
358 core-supply = <®ulator>;
360 clock-names = "pclk", "clk32k_in";
361 #clock-cells = <1>;
363 nvidia,invert-interrupt;
364 nvidia,suspend-mode = <0>;
365 nvidia,cpu-pwr-good-time = <0>;
366 nvidia,cpu-pwr-off-time = <0>;
367 nvidia,core-pwr-good-time = <4587 3876>;
368 nvidia,core-pwr-off-time = <39065>;
369 nvidia,core-power-req-active-high;
370 nvidia,sys-clock-req-active-high;
372 pd_core: core-domain {
373 operating-points-v2 = <&core_opp_table>;
374 #power-domain-cells = <0>;
382 power-domains = <&pd_core>;
383 #power-domain-cells = <0>;
389 power-domains = <&pd_core>;
390 #power-domain-cells = <0>;