Lines Matching +full:sdm845 +full:- +full:llcc
1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rishabh Bhatnagar <rishabhb@codeaurora.org>
11 - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
24 - qcom,sc7180-llcc
25 - qcom,sc7280-llcc
26 - qcom,sc8180x-llcc
27 - qcom,sc8280xp-llcc
28 - qcom,sdm845-llcc
29 - qcom,sm6350-llcc
30 - qcom,sm8150-llcc
31 - qcom,sm8250-llcc
32 - qcom,sm8350-llcc
33 - qcom,sm8450-llcc
34 - qcom,sm8550-llcc
38 - description: LLCC base register region
39 - description: LLCC broadcast base register region
41 reg-names:
43 - const: llcc_base
44 - const: llcc_broadcast_base
50 - compatible
51 - reg
52 - reg-names
57 - |
58 #include <dt-bindings/interrupt-controller/arm-gic.h>
60 system-cache-controller@1100000 {
61 compatible = "qcom,sdm845-llcc";
63 reg-names = "llcc_base", "llcc_broadcast_base";