Lines Matching +full:machine +full:- +full:mode
3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
16 trigger to execute the SPM state machine. The SPM state machine waits for the
19 the SPM state machine out of its wait, the next step is to ensure that the
22 driver and is not defined in the DT. The SPM state machine should be
34 between the time it enters idle and the next known wake up. SPC mode is used
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
47 Power Collapse: This state is similar to the SPC mode, but distinguishes
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
53 of this low power mode would be considered high even though at a cpu level,
58 The idle-state for QCOM SoCs are distinguished by the compatible property of
59 the idle-states device node.
61 The devicetree representation of the idle state should be -
65 - compatible: Must be one of -
66 "qcom,idle-state-ret",
67 "qcom,idle-state-spc",
68 "qcom,idle-state-pc",
69 and "arm,idle-state".
75 idle-states {
77 compatible = "qcom,idle-state-spc", "arm,idle-state";
78 entry-latency-us = <150>;
79 exit-latency-us = <200>;
80 min-residency-us = <2000>;
84 [1]. Documentation/devicetree/bindings/cpu/idle-states.yaml