Lines Matching +full:back +full:- +full:powering
3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
17 interrupt to trigger the core back in to active. This triggers the cache
41 back into Elevation Level (EL) which trampolines the control back to the
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
45 be flushed in s/w, before powering down the core.
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
58 The idle-state for QCOM SoCs are distinguished by the compatible property of
59 the idle-states device node.
61 The devicetree representation of the idle state should be -
65 - compatible: Must be one of -
66 "qcom,idle-state-ret",
67 "qcom,idle-state-spc",
68 "qcom,idle-state-pc",
69 and "arm,idle-state".
75 idle-states {
77 compatible = "qcom,idle-state-spc", "arm,idle-state";
78 entry-latency-us = <150>;
79 exit-latency-us = <200>;
80 min-residency-us = <2000>;
84 [1]. Documentation/devicetree/bindings/cpu/idle-states.yaml