Lines Matching +full:system +full:- +full:cache +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM L2 Cache Controller
10 - Rob Herring <robh@kernel.org>
14 PL220/PL310 and variants) based level 2 cache controller. All these various
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
36 - arm,l210-cache
37 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
38 - bcm,bcm11351-a2-pl310-cache
41 # cache controller
42 - brcm,bcm11351-a2-pl310-cache
43 # Marvell Controller designed to be
44 # compatible with the ARM one, with system cache mode (meaning
47 - marvell,aurora-system-cache
48 # Marvell Controller designed to be
49 # compatible with the ARM one with outer cache mode.
50 - marvell,aurora-outer-cache
51 - items:
52 # Marvell Tauros3 cache controller, compatible
53 # with arm,pl310-cache controller.
54 - const: marvell,tauros3-cache
55 - const: arm,pl310-cache
57 cache-level:
60 cache-unified: true
61 cache-size: true
62 cache-sets: true
63 cache-block-size: true
64 cache-line-size: true
69 arm,data-latency:
73 $ref: /schemas/types.yaml#/definitions/uint32-array
80 arm,tag-latency:
85 $ref: /schemas/types.yaml#/definitions/uint32-array
92 arm,dirty-latency:
98 arm,filter-ranges:
102 $ref: /schemas/types.yaml#/definitions/uint32-array
107 arm,io-coherent:
108 description: indicates that the system is operating in an hardware
109 I/O coherent mode. Valid only when the arm,pl310-cache compatible
118 cache-id-part:
119 description: cache id part number to be used if it is not present
123 wt-override:
127 arm,double-linefill:
129 non-zero, disable if zero.
133 arm,double-linefill-incr:
135 if non-zero, disable if zero.
139 arm,double-linefill-wrap:
141 if non-zero, disable if zero.
145 arm,prefetch-drop:
146 description: Override prefetch drop enable setting. Enable if non-zero,
151 arm,prefetch-offset:
156 arm,shared-override:
157 description: The default behavior of the L220 or PL310 cache
159 memory non-cacheable transactions" into "cacheable no allocate" (for reads)
165 arm,parity-enable:
166 description: enable parity checking on the L2 cache (L220 or PL310).
169 arm,parity-disable:
170 description: disable parity checking on the L2 cache (L220 or PL310).
173 marvell,ecc-enable:
174 description: enable ECC protection on the L2 cache
177 arm,outer-sync-disable:
178 description: disable the outer sync operation on the L2 cache.
179 Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
183 prefetch-data:
190 prefetch-instr:
198 arm,dynamic-clock-gating:
206 arm,standby-mode:
213 arm,early-bresp-disable:
217 arm,full-line-zero-disable:
223 - compatible
224 - cache-unified
225 - reg
230 - |
231 cache-controller@fff12000 {
232 compatible = "arm,pl310-cache";
234 arm,data-latency = <1 1 1>;
235 arm,tag-latency = <2 2 2>;
236 arm,filter-ranges = <0x80000000 0x8000000>;
237 cache-unified;
238 cache-level = <2>;