Lines Matching +full:dynamic +full:- +full:power +full:- +full:coefficient
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
88 - apple,avalanche
89 - apple,blizzard
90 - apple,icestorm
91 - apple,firestorm
92 - arm,arm710t
93 - arm,arm720t
94 - arm,arm740t
95 - arm,arm7ej-s
96 - arm,arm7tdmi
97 - arm,arm7tdmi-s
98 - arm,arm9es
99 - arm,arm9ej-s
100 - arm,arm920t
101 - arm,arm922t
102 - arm,arm925
103 - arm,arm926e-s
104 - arm,arm926ej-s
105 - arm,arm940t
106 - arm,arm946e-s
107 - arm,arm966e-s
108 - arm,arm968e-s
109 - arm,arm9tdmi
110 - arm,arm1020e
111 - arm,arm1020t
112 - arm,arm1022e
113 - arm,arm1026ej-s
114 - arm,arm1136j-s
115 - arm,arm1136jf-s
116 - arm,arm1156t2-s
117 - arm,arm1156t2f-s
118 - arm,arm1176jzf
119 - arm,arm1176jz-s
120 - arm,arm1176jzf-s
121 - arm,arm11mpcore
122 - arm,armv8 # Only for s/w models
123 - arm,cortex-a5
124 - arm,cortex-a7
125 - arm,cortex-a8
126 - arm,cortex-a9
127 - arm,cortex-a12
128 - arm,cortex-a15
129 - arm,cortex-a17
130 - arm,cortex-a32
131 - arm,cortex-a34
132 - arm,cortex-a35
133 - arm,cortex-a53
134 - arm,cortex-a55
135 - arm,cortex-a57
136 - arm,cortex-a65
137 - arm,cortex-a72
138 - arm,cortex-a73
139 - arm,cortex-a75
140 - arm,cortex-a76
141 - arm,cortex-a77
142 - arm,cortex-a78
143 - arm,cortex-a78ae
144 - arm,cortex-a78c
145 - arm,cortex-a510
146 - arm,cortex-a520
147 - arm,cortex-a710
148 - arm,cortex-a715
149 - arm,cortex-a720
150 - arm,cortex-a725
151 - arm,cortex-m0
152 - arm,cortex-m0+
153 - arm,cortex-m1
154 - arm,cortex-m3
155 - arm,cortex-m4
156 - arm,cortex-r4
157 - arm,cortex-r5
158 - arm,cortex-r7
159 - arm,cortex-r52
160 - arm,cortex-x1
161 - arm,cortex-x1c
162 - arm,cortex-x2
163 - arm,cortex-x3
164 - arm,cortex-x4
165 - arm,cortex-x925
166 - arm,neoverse-e1
167 - arm,neoverse-n1
168 - arm,neoverse-n2
169 - arm,neoverse-n3
170 - arm,neoverse-v1
171 - arm,neoverse-v2
172 - arm,neoverse-v3
173 - arm,neoverse-v3ae
174 - brcm,brahma-b15
175 - brcm,brahma-b53
176 - brcm,vulcan
177 - cavium,thunder
178 - cavium,thunder2
179 - faraday,fa526
180 - intel,sa110
181 - intel,sa1100
182 - marvell,feroceon
183 - marvell,mohawk
184 - marvell,pj4a
185 - marvell,pj4b
186 - marvell,sheeva-v5
187 - marvell,sheeva-v7
188 - nvidia,tegra132-denver
189 - nvidia,tegra186-denver
190 - nvidia,tegra194-carmel
191 - qcom,krait
192 - qcom,kryo
193 - qcom,kryo240
194 - qcom,kryo250
195 - qcom,kryo260
196 - qcom,kryo280
197 - qcom,kryo360
198 - qcom,kryo385
199 - qcom,kryo465
200 - qcom,kryo468
201 - qcom,kryo485
202 - qcom,kryo560
203 - qcom,kryo570
204 - qcom,kryo660
205 - qcom,kryo685
206 - qcom,kryo780
207 - qcom,oryon
208 - qcom,scorpion
210 enable-method:
213 # On ARM v8 64-bit this property is required
214 - enum:
215 - psci
216 - spin-table
217 # On ARM 32-bit systems this property is optional
218 - enum:
219 - actions,s500-smp
220 - allwinner,sun6i-a31
221 - allwinner,sun8i-a23
222 - allwinner,sun9i-a80-smp
223 - allwinner,sun8i-a83t-smp
224 - amlogic,meson8-smp
225 - amlogic,meson8b-smp
226 - arm,realview-smp
227 - aspeed,ast2600-smp
228 - brcm,bcm11351-cpu-method
229 - brcm,bcm23550
230 - brcm,bcm2836-smp
231 - brcm,bcm63138
232 - brcm,bcm-nsp-smp
233 - brcm,brahma-b15
234 - marvell,armada-375-smp
235 - marvell,armada-380-smp
236 - marvell,armada-390-smp
237 - marvell,armada-xp-smp
238 - marvell,98dx3236-smp
239 - marvell,mmp3-smp
240 - mediatek,mt6589-smp
241 - mediatek,mt81xx-tz-smp
242 - qcom,gcc-msm8660
243 - qcom,kpss-acc-v1
244 - qcom,kpss-acc-v2
245 - qcom,msm8226-smp
246 - qcom,msm8909-smp
247 # Only valid on ARM 32-bit, see above for ARM v8 64-bit
248 - qcom,msm8916-smp
249 - renesas,apmu
250 - renesas,r9a06g032-smp
251 - rockchip,rk3036-smp
252 - rockchip,rk3066-smp
253 - socionext,milbeaut-m10v-smp
254 - ste,dbx500-smp
255 - ti,am3352
256 - ti,am4372
258 cpu-release-addr:
260 - $ref: /schemas/types.yaml#/definitions/uint32
261 - $ref: /schemas/types.yaml#/definitions/uint64
263 The DT specification defines this as 64-bit always, but some 32-bit Arm
264 systems have used a 32-bit value which must be supported.
265 Required for systems that have an "enable-method"
266 property value of "spin-table".
268 cpu-idle-states:
269 $ref: /schemas/types.yaml#/definitions/phandle-array
274 by this cpu (see ./idle-states.yaml).
276 capacity-dmips-mhz:
278 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
279 DMIPS/MHz, relative to highest capacity-dmips-mhz
282 cci-control-port: true
284 dynamic-power-coefficient:
287 A u32 value that represents the running time dynamic
288 power coefficient in units of uW/MHz/V^2. The
289 coefficient can either be calculated from power
292 The dynamic power consumption of the CPU is
294 the clock frequency (f). The coefficient is used to
295 calculate the dynamic power as below -
297 Pdyn = dynamic-power-coefficient * V^2 * f
301 performance-domains:
306 dvfs/performance-domain.yaml.
308 power-domains:
313 power-domain-names:
315 A list of power domain name strings sorted in the same order as the
316 power-domains property.
328 Required for systems that have an "enable-method" property
329 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
338 Required for systems that have an "enable-method" property
339 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
340 "qcom,msm8916-smp".
342 * arm/msm/qcom,kpss-acc.txt
347 Specifies the syscon node controlling the cpu core power domains.
349 Optional for systems that have an "enable-method"
350 property value of "rockchip,rk3066-smp"
352 the cpu-core power-domains.
354 secondary-boot-reg:
357 Required for systems that have an "enable-method" property value of
358 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
364 The secondary-boot-reg property is a u32 value that specifies the
371 # If the enable-method property contains one of those values
373 enable-method:
376 - brcm,bcm11351-cpu-method
377 - brcm,bcm23550
378 - brcm,bcm-nsp-smp
379 # and if enable-method is present
381 - enable-method
385 - secondary-boot-reg
388 - device_type
389 - reg
390 - compatible
393 rockchip,pmu: [enable-method]
398 - |
400 #size-cells = <0>;
401 #address-cells = <1>;
405 compatible = "arm,cortex-a15";
411 compatible = "arm,cortex-a15";
417 compatible = "arm,cortex-a7";
423 compatible = "arm,cortex-a7";
428 - |
429 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
431 #size-cells = <0>;
432 #address-cells = <1>;
436 compatible = "arm,cortex-a8";
441 - |
442 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
444 #size-cells = <0>;
445 #address-cells = <1>;
449 compatible = "arm,arm926ej-s";
454 - |
455 // Example 4 (ARM Cortex-A57 64-bit system):
457 #size-cells = <0>;
458 #address-cells = <2>;
462 compatible = "arm,cortex-a57";
464 enable-method = "spin-table";
465 cpu-release-addr = <0 0x20000000>;
470 compatible = "arm,cortex-a57";
472 enable-method = "spin-table";
473 cpu-release-addr = <0 0x20000000>;
478 compatible = "arm,cortex-a57";
480 enable-method = "spin-table";
481 cpu-release-addr = <0 0x20000000>;
486 compatible = "arm,cortex-a57";
488 enable-method = "spin-table";
489 cpu-release-addr = <0 0x20000000>;
494 compatible = "arm,cortex-a57";
496 enable-method = "spin-table";
497 cpu-release-addr = <0 0x20000000>;
502 compatible = "arm,cortex-a57";
504 enable-method = "spin-table";
505 cpu-release-addr = <0 0x20000000>;
510 compatible = "arm,cortex-a57";
512 enable-method = "spin-table";
513 cpu-release-addr = <0 0x20000000>;
518 compatible = "arm,cortex-a57";
520 enable-method = "spin-table";
521 cpu-release-addr = <0 0x20000000>;
526 compatible = "arm,cortex-a57";
528 enable-method = "spin-table";
529 cpu-release-addr = <0 0x20000000>;
534 compatible = "arm,cortex-a57";
536 enable-method = "spin-table";
537 cpu-release-addr = <0 0x20000000>;
542 compatible = "arm,cortex-a57";
544 enable-method = "spin-table";
545 cpu-release-addr = <0 0x20000000>;
550 compatible = "arm,cortex-a57";
552 enable-method = "spin-table";
553 cpu-release-addr = <0 0x20000000>;
558 compatible = "arm,cortex-a57";
560 enable-method = "spin-table";
561 cpu-release-addr = <0 0x20000000>;
566 compatible = "arm,cortex-a57";
568 enable-method = "spin-table";
569 cpu-release-addr = <0 0x20000000>;
574 compatible = "arm,cortex-a57";
576 enable-method = "spin-table";
577 cpu-release-addr = <0 0x20000000>;
582 compatible = "arm,cortex-a57";
584 enable-method = "spin-table";
585 cpu-release-addr = <0 0x20000000>;