Lines Matching +full:cci +full:- +full:400 +full:- +full:pmu
2 ARM CCI cache coherent interconnect binding description
5 ARM multi-cluster systems maintain intra-cluster coherency through a
6 cache coherent interconnect (CCI) that is capable of monitoring bus
14 * CCI interconnect node
16 Description: Describes a CCI cache coherent Interconnect component
18 Node name must be "cci".
20 through the CCI interconnect is the same as the one seen from the
22 Every CCI node has to define the following properties:
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
37 address of CCI control registers common to all
40 - ranges:
47 Specification for hierarchical bus addressing. CCI
51 CCI interconnect node can define the following child nodes:
53 - CCI control interface nodes
55 Node name must be "slave-if".
56 Parent node must be CCI interconnect node.
58 A CCI control interface node must contain the following
61 - compatible
65 "arm,cci-400-ctrl-if"
67 - interface-type:
70 Definition: must be set to one of {"ace", "ace-lite"}
74 - reg:
83 - CCI PMU node
85 Parent node must be CCI interconnect node.
87 A CCI pmu node must contain the following properties:
89 - compatible
93 "arm,cci-400-pmu,r0"
94 "arm,cci-400-pmu,r1"
95 "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
96 secure access to CCI registers
97 "arm,cci-500-pmu,r0"
98 "arm,cci-550-pmu,r0"
99 - reg:
108 - interrupts:
112 ../interrupt-controller/interrupts.txt.
120 The CCI PMU has an interrupt signal for each
124 * CCI interconnect bus masters
126 Description: masters in the device tree connected to a CCI port
129 A CCI interconnect bus master node must contain the following
132 - cci-control-port:
135 Definition: a phandle containing the CCI control interface node
141 #size-cells = <0>;
142 #address-cells = <1>;
146 compatible = "arm,cortex-a15";
147 cci-control-port = <&cci_control1>;
153 compatible = "arm,cortex-a15";
154 cci-control-port = <&cci_control1>;
160 compatible = "arm,cortex-a7";
161 cci-control-port = <&cci_control2>;
167 compatible = "arm,cortex-a7";
168 cci-control-port = <&cci_control2>;
176 cci-control-port = <&cci_control0>;
179 #dma-cells = <1>;
180 #dma-channels = <8>;
181 #dma-requests = <32>;
184 cci@2c090000 {
185 compatible = "arm,cci-400";
186 #address-cells = <1>;
187 #size-cells = <1>;
191 cci_control0: slave-if@1000 {
192 compatible = "arm,cci-400-ctrl-if";
193 interface-type = "ace-lite";
197 cci_control1: slave-if@4000 {
198 compatible = "arm,cci-400-ctrl-if";
199 interface-type = "ace";
203 cci_control2: slave-if@5000 {
204 compatible = "arm,cci-400-ctrl-if";
205 interface-type = "ace";
209 pmu@9000 {
210 compatible = "arm,cci-400-pmu";
220 This CCI node corresponds to a CCI component whose control registers sits
222 CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
223 CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
224 CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};