Lines Matching +full:timeout +full:- +full:lp +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
21 u32 lp;
82 rtwdev->dbcc_en, phy_idx);
84 if (!rtwdev->dbcc_en)
171 struct rtw89_dack_info *dack = &rtwdev->dack;
177 dack->addck_d[0][0], dack->addck_d[0][1]);
180 dack->addck_d[1][0], dack->addck_d[1][1]);
183 dack->dadck_d[0][0], dack->dadck_d[0][1]);
186 dack->dadck_d[1][0], dack->dadck_d[1][1]);
190 dack->biask_d[0][0], dack->biask_d[0][1]);
193 dack->biask_d[1][0], dack->biask_d[1][1]);
197 t = dack->msbk_d[0][0][i];
202 t = dack->msbk_d[0][1][i];
207 t = dack->msbk_d[1][0][i];
212 t = dack->msbk_d[1][1][i];
219 struct rtw89_dack_info *dack = &rtwdev->dack;
222 dack->addck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0,
224 dack->addck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0,
228 dack->addck_d[1][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1,
230 dack->addck_d[1][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1,
236 struct rtw89_dack_info *dack = &rtwdev->dack;
239 dack->addck_d[0][0]);
241 dack->addck_d[0][1]);
244 dack->addck_d[1][0]);
246 dack->addck_d[1][1]);
252 struct rtw89_dack_info *dack = &rtwdev->dack;
258 dack->msbk_d[0][0][i] = rtw89_phy_read32_mask(rtwdev,
262 dack->msbk_d[0][1][i] = rtw89_phy_read32_mask(rtwdev,
266 dack->biask_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS00,
268 dack->biask_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS01,
270 dack->dadck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK00,
272 dack->dadck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK01,
278 struct rtw89_dack_info *dack = &rtwdev->dack;
284 dack->msbk_d[1][0][i] = rtw89_phy_read32_mask(rtwdev,
288 dack->msbk_d[1][1][i] = rtw89_phy_read32_mask(rtwdev,
292 dack->biask_d[1][0] = rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS10,
294 dack->biask_d[1][1] = rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS11,
296 dack->dadck_d[1][0] = rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK10,
298 dack->dadck_d[1][1] = rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK11,
305 struct rtw89_dack_info *dack = &rtwdev->dack;
319 val32 |= dack->msbk_d[path][index][i + 12] << (i * 8);
328 val32 |= dack->msbk_d[path][index][i + 8] << (i * 8);
337 val32 |= dack->msbk_d[path][index][i + 4] << (i * 8);
346 val32 |= dack->msbk_d[path][index][i] << (i * 8);
353 val32 = (dack->biask_d[path][index] << 22) |
354 (dack->dadck_d[path][index] << 14);
370 struct rtw89_dack_info *dack = &rtwdev->dack;
384 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n");
385 dack->addck_timeout[0] = true;
400 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADDCK timeout\n");
401 dack->addck_timeout[0] = true;
480 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_CTL, def->ctl);
481 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_EN, def->en);
482 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, def->bw0);
483 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, def->bw1);
484 rtw89_phy_write32_mask(rtwdev, R_DRCK | (path << 8), B_DRCK_MUL, def->mul);
485 rtw89_phy_write32_mask(rtwdev, R_ADCMOD | (path << 8), B_ADCMOD_LP, def->lp);
509 struct rtw89_dack_info *dack = &rtwdev->dack;
522 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DACK timeout\n");
523 dack->msbk_timeout[0] = true;
536 struct rtw89_dack_info *dack = &rtwdev->dack;
549 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DACK timeout\n");
550 dack->msbk_timeout[0] = true;
576 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DRCK timeout\n");
589 struct rtw89_dack_info *dack = &rtwdev->dack;
593 dack->dack_done = false;
617 dack->dack_done = true;
622 dack->dack_cnt++;
656 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
663 switch (iqk_info->iqk_bw[path]) {
707 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]IQK timeout!!!\n");
721 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
752 iqk_cmd = 0x008 | (1 << (4 + path)) | ((0x8 + iqk_info->iqk_bw[path]) << 8);
759 iqk_cmd = 0x008 | (1 << (4 + path)) | ((0xc + iqk_info->iqk_bw[path]) << 8);
784 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
799 switch (iqk_info->iqk_band[path]) {
821 switch (iqk_info->iqk_band[path]) {
856 iqk_info->nb_rxcfir[path] = 0x40000002;
857 iqk_info->is_wb_rxiqk[path] = false;
859 iqk_info->nb_rxcfir[path] = 0x40000000;
860 iqk_info->is_wb_rxiqk[path] = true;
869 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
884 switch (iqk_info->iqk_band[path]) {
905 switch (iqk_info->iqk_band[path]) {
932 iqk_info->nb_rxcfir[path] =
936 iqk_info->nb_rxcfir[path] = 0x40000002;
938 iqk_info->is_wb_rxiqk[path] = false;
945 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
950 switch (iqk_info->iqk_band[path]) {
1001 iqk_info->nb_txcfir[path] = 0x40000002;
1002 iqk_info->is_wb_txiqk[path] = false;
1004 iqk_info->nb_txcfir[path] = 0x40000000;
1005 iqk_info->is_wb_txiqk[path] = true;
1014 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1018 switch (iqk_info->iqk_band[path]) {
1053 iqk_info->nb_txcfir[path] =
1057 iqk_info->nb_txcfir[path] = 0x40000002;
1059 iqk_info->is_wb_txiqk[path] = false;
1066 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
1067 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1068 u8 idx = rfk_mcc->table_idx;
1086 iqk_info->lok_idac[idx][path] = val;
1097 iqk_info->lok_vbuf[idx][path] = val;
1105 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1114 switch (iqk_info->iqk_band[path]) {
1137 iqk_info->lok_cor_fail[0][path] = tmp;
1140 switch (iqk_info->iqk_band[path]) {
1162 switch (iqk_info->iqk_band[path]) {
1185 iqk_info->lok_fin_fail[0][path] = tmp;
1188 switch (iqk_info->iqk_band[path]) {
1214 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1216 switch (iqk_info->iqk_band[path]) {
1226 0x403e0 | iqk_info->syn1to2);
1238 0x403e0 | iqk_info->syn1to2);
1250 0x403e0 | iqk_info->syn1to2);
1261 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1266 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]));
1268 iqk_info->lok_cor_fail[0][path]);
1270 iqk_info->lok_fin_fail[0][path]);
1272 iqk_info->iqk_tx_fail[0][path]);
1274 iqk_info->iqk_rx_fail[0][path]);
1276 flag = iqk_info->lok_cor_fail[0][path];
1278 flag = iqk_info->lok_fin_fail[0][path];
1280 flag = iqk_info->iqk_tx_fail[0][path];
1282 flag = iqk_info->iqk_rx_fail[0][path];
1286 iqk_info->bp_iqkenable[path] = tmp;
1288 iqk_info->bp_txkresult[path] = tmp;
1290 iqk_info->bp_rxkresult[path] = tmp;
1293 iqk_info->iqk_times);
1297 iqk_info->iqk_fail_cnt++;
1299 iqk_info->iqk_fail_cnt);
1304 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1307 iqk_info->lok_fail[path] = _iqk_lok(rtwdev, phy_idx, path);
1309 if (iqk_info->is_nbiqk)
1310 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path);
1312 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path);
1315 if (iqk_info->is_nbiqk)
1316 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path);
1318 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path);
1327 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1331 iqk_info->iqk_band[path] = chan->band_type;
1332 iqk_info->iqk_bw[path] = chan->band_width;
1333 iqk_info->iqk_ch[path] = chan->channel;
1336 "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path,
1337 iqk_info->iqk_band[path]);
1338 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_bw[%x] = 0x%x\n",
1339 path, iqk_info->iqk_bw[path]);
1340 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_ch[%x] = 0x%x\n",
1341 path, iqk_info->iqk_ch[path]);
1344 rtwdev->dbcc_en ? "on" : "off",
1345 iqk_info->iqk_band[path] == 0 ? "2G" :
1346 iqk_info->iqk_band[path] == 1 ? "5G" : "6G",
1347 iqk_info->iqk_ch[path],
1348 iqk_info->iqk_bw[path] == 0 ? "20M" :
1349 iqk_info->iqk_bw[path] == 1 ? "40M" : "80M");
1350 if (!rtwdev->dbcc_en)
1351 iqk_info->syn1to2 = 0x1;
1353 iqk_info->syn1to2 = 0x3;
1357 iqk_info->iqk_band[path]);
1359 iqk_info->iqk_bw[path]);
1361 iqk_info->iqk_ch[path]);
1374 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1378 iqk_info->nb_txcfir[path]);
1380 iqk_info->nb_rxcfir[path]);
1408 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
1411 idx = rfk_mcc->table_idx;
1474 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RCK timeout\n");
1489 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1493 if (iqk_info->is_iqk_init)
1497 iqk_info->is_iqk_init = true;
1498 iqk_info->is_nbiqk = false;
1499 iqk_info->iqk_fft_en = false;
1500 iqk_info->iqk_sram_en = false;
1501 iqk_info->iqk_cfir_en = false;
1502 iqk_info->iqk_xym_en = false;
1503 iqk_info->iqk_times = 0x0;
1506 iqk_info->iqk_channel[ch] = 0x0;
1508 iqk_info->lok_cor_fail[ch][path] = false;
1509 iqk_info->lok_fin_fail[ch][path] = false;
1510 iqk_info->iqk_tx_fail[ch][path] = false;
1511 iqk_info->iqk_rx_fail[ch][path] = false;
1512 iqk_info->iqk_mcc_ch[ch][path] = 0x0;
1513 iqk_info->iqk_table_idx[path] = 0x0;
1521 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1530 iqk_info->iqk_times++;
1531 iqk_info->version = RTW8852C_IQK_VER;
1533 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
1616 if (abs(i_even_bs - i_even) > th || abs(q_even_bs - q_even) > th)
1633 if (abs(i_odd_bs - i_odd) > th || abs(q_odd_bs - q_odd) > th)
1645 if ((abs(val_i_bs - val_i) < th) && (abs(val_q_bs - val_q) <= th)) {
1650 if (abs(val_i_bs - val_i) > th) {
1656 if (abs(val_q_bs - val_q) > th) {
1726 rtw89_warn(rtwdev, "[RX_DCK] S%d RXDCK timeout\n", path);
1756 if (chan->band_type == RTW89_BAND_5G) {
1757 if (chan->channel >= 36 && chan->channel <= 64) {
1759 } else if (chan->channel >= 100 && chan->channel <= 144) {
1760 target_ch = chan->channel + 32;
1762 target_ch = chan->channel + 33;
1763 } else if (chan->channel >= 149 && chan->channel <= 177) {
1764 target_ch = chan->channel - 33;
1766 } else if (chan->band_type == RTW89_BAND_6G) {
1767 if (chan->channel >= 1 && chan->channel <= 125)
1768 target_ch = chan->channel + 32;
1770 target_ch = chan->channel - 32;
1772 target_ch = chan->channel;
1777 chan->channel, target_ch);
1885 "[DPK] one-shot for %s = 0x%x (ret=%d)\n",
1895 "[DPK] one-shot over 20ms!!!!\n");
1907 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1909 u8 kidx = dpk->cur_idx[path];
1911 dpk->bp[path][kidx].band = chan->band_type;
1912 dpk->bp[path][kidx].ch = chan->channel;
1913 dpk->bp[path][kidx].bw = chan->band_width;
1917 path, dpk->cur_idx[path], phy,
1918 rtwdev->is_tssi_mode[path] ? "on" : "off",
1919 rtwdev->dbcc_en ? "on" : "off",
1920 dpk->bp[path][kidx].band == 0 ? "2G" :
1921 dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1922 dpk->bp[path][kidx].ch,
1923 dpk->bp[path][kidx].bw == 0 ? "20M" :
1924 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
2061 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2063 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
2065 0x50121 | BIT(rtwdev->dbcc_en));
2082 0x50101 | BIT(rtwdev->dbcc_en));
2085 if (dpk->bp[path][kidx].band == RTW89_BAND_6G && dpk->bp[path][kidx].ch >= 161)
2096 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160)
2103 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2105 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160) {
2108 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) {
2111 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) {
2119 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160 ? "160M" :
2120 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
2121 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
2129 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2139 dpk->corr_idx[path][kidx] = corr_idx;
2140 dpk->corr_val[path][kidx] = corr_val;
2154 dpk->dc_i[path][kidx] = dc_i;
2155 dpk->dc_q[path][kidx] = dc_q;
2205 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2208 dpk->cur_k_set =
2209 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), 0xE0000000) - 1;
2321 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2352 if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
2381 tmp_dbm = max_t(u8, tmp_dbm - 3, 7);
2418 } while (!goout && agc_cnt < 6 && --limit > 0);
2451 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2464 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_5 ||
2465 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_10 ||
2466 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_20)
2468 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ||
2469 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80)
2501 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2505 cur_band = chan->band_type;
2506 cur_ch = chan->channel;
2509 if (cur_band != dpk->bp[path][idx].band ||
2510 cur_ch != dpk->bp[path][idx].ch)
2515 dpk->cur_idx[path] = idx;
2536 if (rtwdev->hal.cv == CHIP_CAV)
2555 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2558 para = rtw89_phy_read32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8),
2561 dpk->bp[path][kidx].txagc_dpk = FIELD_GET(_DPK_PARA_TXAGC, para);
2562 dpk->bp[path][kidx].ther_dpk = FIELD_GET(_DPK_PARA_THER, para);
2565 dpk->cur_k_set, dpk->bp[path][kidx].ther_dpk, dpk->bp[path][kidx].txagc_dpk);
2571 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2579 rtw89_phy_write32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8),
2582 dpk->bp[path][kidx].gs =
2583 rtw89_phy_read32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8),
2618 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2625 dpk->bp[path][kidx].mdpd_en = BIT(dpk->cur_k_set);
2626 dpk->bp[path][kidx].path_ok = true;
2629 path, kidx, dpk->bp[path][kidx].mdpd_en);
2632 B_DPD_MEN, dpk->bp[path][kidx].mdpd_en);
2640 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2641 u8 kidx = dpk->cur_idx[path];
2670 dpk->cur_k_set, is_fail ? "need Check" : "is Success");
2677 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2678 u8 kidx = dpk->cur_idx[path];
2680 dpk->bp[path][kidx].path_ok = false;
2694 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2707 if (dpk->is_dpk_reload_en) {
2713 if (!reloaded[path] && dpk->bp[path][0].ch != 0)
2714 dpk->cur_idx[path] = !dpk->cur_idx[path];
2720 dpk->cur_idx[path] = 0;
2726 path, dpk->cur_idx[path]);
2731 if (rtwdev->is_tssi_mode[path])
2738 path, dpk->cur_idx[path]);
2749 path, dpk->cur_idx[path]);
2755 if (rtwdev->is_tssi_mode[path])
2764 struct rtw89_fem_info *fem = &rtwdev->fem;
2766 u8 band = chan->band_type;
2768 if (rtwdev->hal.cv == CHIP_CAV && band != RTW89_BAND_2G) {
2771 } else if (fem->epa_2g && band == RTW89_BAND_2G) {
2774 } else if (fem->epa_5g && band == RTW89_BAND_5G) {
2777 } else if (fem->epa_6g && band == RTW89_BAND_6G) {
2801 RTW8852C_DPK_VER, rtwdev->hal.cv,
2816 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2817 u8 val, kidx = dpk->cur_idx[path];
2819 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok ?
2820 dpk->bp[path][kidx].mdpd_en : 0;
2826 kidx, dpk->is_dpk_enable && !off ? "enable" : "disable");
2831 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2840 kidx = dpk->cur_idx[path];
2843 path, kidx, dpk->bp[path][kidx].ch);
2862 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
2867 if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0)
2868 delta_ther = dpk->bp[path][kidx].ther_dpk - cur_ther;
2874 delta_ther, cur_ther, dpk->bp[path][kidx].ther_dpk);
2877 txagc_rf - dpk->bp[path][kidx].txagc_dpk, txagc_rf,
2878 dpk->bp[path][kidx].txagc_dpk);
2887 txagc_rf != 0 && rtwdev->hal.cv == CHIP_CAV) {
2889 "[DPK_TRK] New pwsf = 0x%x\n", 0x78 - delta_ther);
2892 0x07FC0000, 0x78 - delta_ther);
2901 enum rtw89_bandwidth bw = chan->band_width;
2902 enum rtw89_band band = chan->band_type;
2955 enum rtw89_band band = chan->band_type;
2992 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
2994 u8 ch = chan->channel;
2995 u8 subband = chan->subband_type;
3062 thermal = tssi_info->thermal[RF_PATH_A];
3090 -thm_down_a[i++] :
3091 -thm_down_a[DELTA_SWINGIDX_SIZE - 1];
3094 for (j = 63; j >= 32; j--)
3097 thm_up_a[DELTA_SWINGIDX_SIZE - 1];
3112 thermal = tssi_info->thermal[RF_PATH_B];
3140 -thm_down_b[i++] :
3141 -thm_down_b[DELTA_SWINGIDX_SIZE - 1];
3144 for (j = 63; j >= 32; j--)
3147 thm_up_b[DELTA_SWINGIDX_SIZE - 1];
3168 enum rtw89_band band = chan->band_type;
3185 enum rtw89_band band = chan->band_type;
3242 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3245 if (rtwdev->dbcc_en) {
3263 tssi_info->base_thermal[i] =
3264 ewma_thermal_read(&rtwdev->phystat.avg_thermal[i]);
3265 rtwdev->is_tssi_mode[i] = true;
3273 if (rtwdev->dbcc_en) {
3286 rtwdev->is_tssi_mode[RF_PATH_A] = false;
3289 rtwdev->is_tssi_mode[RF_PATH_B] = false;
3595 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3597 enum rtw89_band band = chan->band_type;
3598 u8 ch = chan->channel;
3614 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
3615 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
3622 val = tssi_info->tssi_mcs[path][gidx];
3637 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st];
3638 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd];
3645 val = tssi_info->tssi_6g_mcs[path][gidx];
3659 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3661 enum rtw89_band band = chan->band_type;
3662 u8 ch = chan->channel;
3678 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
3679 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
3686 val = tssi_info->tssi_trim[path][tgidx];
3702 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st];
3703 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd];
3710 val = tssi_info->tssi_trim_6g[path][tgidx];
3724 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3726 u8 ch = chan->channel;
3736 if (rtwdev->dbcc_en) {
3749 val = tssi_info->tssi_cck[i][gidx] + trim_de;
3753 i, gidx, tssi_info->tssi_cck[i][gidx], trim_de);
3796 if (rtwdev->dbcc_en && path == RF_PATH_B)
3808 if (!rtwdev->dbcc_en) {
3882 if (rtwdev->dbcc_en)
3885 if (path == RF_PATH_B && rtwdev->hal.cv == CHIP_CAV) {
3994 struct rtw89_lck_info *lck = &rtwdev->lck;
3997 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
3998 lck->thermal[path] =
3999 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
4001 "[LCK] path=%d thermal=0x%x", path, lck->thermal[path]);
4008 int path = rtwdev->dbcc_en ? 2 : 1;
4029 struct rtw89_lck_info *lck = &rtwdev->lck;
4034 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
4036 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
4037 delta = abs((int)cur_thermal - lck->thermal[path]);
4069 rtw8852c_ctrl_bw_ch(rtwdev, phy_idx, chan->channel,
4070 chan->band_type,
4071 chan->band_width);
4076 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
4098 p->ch = rfk_mcc->ch[idx];
4100 p->has_band = true;
4101 p->band = rfk_mcc->band[idx];
4106 rfk_mcc->ch[idx] = chan->channel;
4107 rfk_mcc->band[idx] = chan->band_type;
4108 rfk_mcc->table_idx = idx;
4149 struct rtw89_rx_dck_info *rx_dck = &rtwdev->rx_dck;
4158 RXDCK_VER_8852C, rtwdev->hal.cv);
4165 if (rtwdev->is_tssi_mode[path])
4170 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_LO_SEL, rtwdev->dbcc_en);
4178 if (rek_cnt == retry_limit - 1) {
4191 rx_dck->thermal[path] = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
4194 if (rtwdev->is_tssi_mode[path])
4210 struct rtw89_rx_dck_info *rx_dck = &rtwdev->rx_dck;
4219 if (chan->band_type == RTW89_BAND_2G)
4222 if (rtwdev->scanning)
4227 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
4228 delta = abs((int)cur_thermal - rx_dck->thermal[path]);
4246 _ctrl_ch(rtwdev, RTW89_PHY_0, dck_channel, chan->band_type);
4252 _ctrl_ch(rtwdev, RTW89_PHY_0, chan->channel, chan->band_type);
4260 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
4262 dpk->is_dpk_enable = true;
4263 dpk->is_dpk_reload_en = false;
4292 if (rtwdev->dbcc_en) {
4328 if (!rtwdev->is_tssi_mode[RF_PATH_A])
4330 if (!rtwdev->is_tssi_mode[RF_PATH_B])
4333 if (rtwdev->dbcc_en) {
4360 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4363 if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B])
4371 tssi_info->default_txagc_offset[RF_PATH_A] =
4374 if (tssi_info->default_txagc_offset[RF_PATH_A])
4382 tssi_info->default_txagc_offset[RF_PATH_B] =
4385 if (tssi_info->default_txagc_offset[RF_PATH_B])
4392 tssi_info->default_txagc_offset[RF_PATH_A]);
4394 tssi_info->default_txagc_offset[RF_PATH_B]);
4416 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
4421 dpk->is_dpk_enable = false;
4426 dpk->is_dpk_enable = true;