Lines Matching full:path
153 u8 path;
157 for (path = 0; path < RF_PATH_MAX; path++) {
158 if (!(kpath & BIT(path)))
162 2, 5000, false, rtwdev, path, 0x00,
166 path, ret);
304 enum rtw89_rf_path path, u8 index)
312 path_offset = (path == RF_PATH_A ? 0 : 0x28);
320 val32 |= dack->msbk_d[path][index][i + 12] << (i * 8);
329 val32 |= dack->msbk_d[path][index][i + 8] << (i * 8);
338 val32 |= dack->msbk_d[path][index][i + 4] << (i * 8);
347 val32 |= dack->msbk_d[path][index][i] << (i * 8);
354 val32 = (dack->biask_d[path][index] << 22) |
355 (dack->dadck_d[path][index] << 14);
361 static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
366 _dack_reload_by_path(rtwdev, path, i);
407 static void _dack_reset(struct rtw89_dev *rtwdev, u8 path)
409 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
443 static void rtw8852c_txck_force(struct rtw89_dev *rtwdev, u8 path, bool force,
446 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x0);
451 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_VAL, ck);
452 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x1);
455 static void rtw8852c_rxck_force(struct rtw89_dev *rtwdev, u8 path, bool force,
460 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x0);
465 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_VAL, ck);
466 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x1);
481 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_CTL, def->ctl);
482 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_EN, def->en);
483 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, def->bw0);
484 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, def->bw1);
485 rtw89_phy_write32_mask(rtwdev, R_DRCK | (path << 8), B_DRCK_MUL, def->mul);
486 rtw89_phy_write32_mask(rtwdev, R_ADCMOD | (path << 8), B_ADCMOD_LP, def->lp);
648 static void rtw8852c_disable_rxagc(struct rtw89_dev *rtwdev, u8 path, u8 en_rxgac)
650 if (path == RF_PATH_A)
656 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
660 if (path == RF_PATH_A)
665 switch (iqk_info->iqk_bw[path]) {
668 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_DPD_GDIS, 0x1);
669 rtw8852c_rxck_force(rtwdev, path, true, ADC_480M);
670 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_ACK_VAL, 0x0);
671 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1);
672 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x1);
675 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_DPD_GDIS, 0x1);
676 rtw8852c_rxck_force(rtwdev, path, true, ADC_960M);
677 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_ACK_VAL, 0x1);
678 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1);
679 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x1);
682 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_DPD_GDIS, 0x1);
683 rtw8852c_rxck_force(rtwdev, path, true, ADC_1920M);
684 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_ACK_VAL, 0x2);
685 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1);
686 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x1);
694 if (path == RF_PATH_A)
700 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype)
712 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret);
715 "[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp);
721 enum rtw89_phy_idx phy_idx, u8 path, u8 ktype)
724 u32 addr_rfc_ctl = R_UPD_CLK + (path << 13);
730 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1);
734 iqk_cmd = 0x008 | (1 << (4 + path));
738 iqk_cmd = 0x108 | (1 << (4 + path));
742 iqk_cmd = 0x508 | (1 << (4 + path));
746 iqk_cmd = 0x208 | (1 << (4 + path));
750 iqk_cmd = 0x308 | (1 << (4 + path));
754 iqk_cmd = 0x008 | (1 << (4 + path)) | ((0x8 + iqk_info->iqk_bw[path]) << 8);
757 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
761 iqk_cmd = 0x008 | (1 << (4 + path)) | ((0xc + iqk_info->iqk_bw[path]) << 8);
765 iqk_cmd = 0x408 | (1 << (4 + path));
769 iqk_cmd = 0x608 | (1 << (4 + path));
777 fail = _iqk_check_cal(rtwdev, path, ktype);
784 enum rtw89_phy_idx phy_idx, u8 path)
792 bkrf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_NBW);
793 if (path == RF_PATH_B) {
801 switch (iqk_info->iqk_band[path]) {
804 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
805 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
806 rtw89_write_rf(rtwdev, path, RR_RXG, RR_RXG_IQKMOD, 0x9);
809 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
810 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
811 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x8);
814 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
815 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
816 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x9);
823 switch (iqk_info->iqk_band[path]) {
826 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG,
828 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_VOBUF,
832 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG,
834 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT,
838 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG,
840 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT,
844 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
846 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
848 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
850 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
853 if (path == RF_PATH_B)
854 rtw89_write_rf(rtwdev, path, RR_IQKPLL, RR_IQKPLL_MOD, 0x0);
855 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, bkrf0);
858 iqk_info->nb_rxcfir[path] = 0x40000002;
859 iqk_info->is_wb_rxiqk[path] = false;
861 iqk_info->nb_rxcfir[path] = 0x40000000;
862 iqk_info->is_wb_rxiqk[path] = true;
869 enum rtw89_phy_idx phy_idx, u8 path)
877 bkrf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_NBW);
878 if (path == RF_PATH_B) {
886 switch (iqk_info->iqk_band[path]) {
889 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
890 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
891 rtw89_write_rf(rtwdev, path, RR_RXG, RR_RXG_IQKMOD, 0x9);
894 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
895 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
896 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x8);
899 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
900 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, 0x0);
901 rtw89_write_rf(rtwdev, path, RR_RXAE, RR_RXAE_IQKMOD, 0x9);
907 switch (iqk_info->iqk_band[path]) {
910 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, _rxk_g_idxrxgain[gp]);
911 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_VOBUF, _rxk_g_idxattc2[gp]);
914 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, _rxk_a_idxrxgain[gp]);
915 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT, _rxk_a_idxattc2[gp]);
918 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, _rxk_a6_idxrxgain[gp]);
919 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_IATT, _rxk_a6_idxattc2[gp]);
923 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
924 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x0);
925 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP_V1, gp);
926 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
928 if (path == RF_PATH_B)
929 rtw89_write_rf(rtwdev, path, RR_IQKPLL, RR_IQKPLL_MOD, 0x0);
931 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_NBW, bkrf0);
934 iqk_info->nb_rxcfir[path] =
935 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
938 iqk_info->nb_rxcfir[path] = 0x40000002;
940 iqk_info->is_wb_rxiqk[path] = false;
945 enum rtw89_phy_idx phy_idx, u8 path)
952 switch (iqk_info->iqk_band[path]) {
954 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
956 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
958 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
961 R_KIP_IQP + (path << 8),
965 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
967 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
969 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
972 R_KIP_IQP + (path << 8),
976 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
978 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
980 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
983 R_KIP_IQP + (path << 8),
989 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
991 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
993 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
995 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
999 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
1003 iqk_info->nb_txcfir[path] = 0x40000002;
1004 iqk_info->is_wb_txiqk[path] = false;
1006 iqk_info->nb_txcfir[path] = 0x40000000;
1007 iqk_info->is_wb_txiqk[path] = true;
1014 enum rtw89_phy_idx phy_idx, u8 path)
1020 switch (iqk_info->iqk_band[path]) {
1022 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, _txk_g_power_range[gp]);
1023 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, _txk_g_track_range[gp]);
1024 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, _txk_g_gain_bb[gp]);
1025 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1029 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, _txk_a_power_range[gp]);
1030 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, _txk_a_track_range[gp]);
1031 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, _txk_a_gain_bb[gp]);
1032 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1036 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, _txk_a6_power_range[gp]);
1037 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, _txk_a6_track_range[gp]);
1038 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, _txk_a6_gain_bb[gp]);
1039 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1046 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
1047 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x1);
1048 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G2, 0x0);
1049 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp + 1);
1052 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1055 iqk_info->nb_txcfir[path] =
1056 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8),
1059 iqk_info->nb_txcfir[path] = 0x40000002;
1061 iqk_info->is_wb_txiqk[path] = false;
1066 static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path)
1079 val = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK);
1088 iqk_info->lok_idac[idx][path] = val;
1090 val = rtw89_read_rf(rtwdev, path, RR_LOKVB, RFREG_MASK);
1099 iqk_info->lok_vbuf[idx][path] = val;
1105 enum rtw89_phy_idx phy_idx, u8 path)
1116 switch (iqk_info->iqk_band[path]) {
1118 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1119 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1124 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1125 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1130 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1131 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1138 tmp = _iqk_one_shot(rtwdev, phy_idx, path, tmp_id);
1139 iqk_info->lok_cor_fail[0][path] = tmp;
1142 switch (iqk_info->iqk_band[path]) {
1144 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1145 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1149 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1150 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1154 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1155 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1161 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
1164 switch (iqk_info->iqk_band[path]) {
1166 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1167 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1172 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1173 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1178 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x6);
1179 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1186 tmp = _iqk_one_shot(rtwdev, phy_idx, path, tmp_id);
1187 iqk_info->lok_fin_fail[0][path] = tmp;
1190 switch (iqk_info->iqk_band[path]) {
1193 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1194 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1198 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1199 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1203 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1204 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1208 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
1209 fail = _lok_finetune_check(rtwdev, path);
1214 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
1218 switch (iqk_info->iqk_band[path]) {
1221 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0);
1222 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0);
1223 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1);
1224 rtw89_write_rf(rtwdev, path, RR_TXA2, RR_TXA2_LDO, 0xf);
1225 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1226 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1227 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
1230 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1231 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6);
1234 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW2, 0x0);
1235 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXAS, 0x1);
1236 rtw89_write_rf(rtwdev, path, RR_TXA2, RR_TXA2_LDO, 0xf);
1237 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1238 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1239 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
1242 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1243 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6);
1246 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW2, 0x0);
1247 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXAS, 0x1);
1248 rtw89_write_rf(rtwdev, path, RR_TXA2, RR_TXA2_LDO, 0xf);
1249 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1250 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1251 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
1254 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1255 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6);
1261 u8 path)
1267 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %lu\n", path,
1268 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]));
1269 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_COR_fail= %d\n", path,
1270 iqk_info->lok_cor_fail[0][path]);
1271 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_FIN_fail= %d\n", path,
1272 iqk_info->lok_fin_fail[0][path]);
1273 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_TXIQK_fail = %d\n", path,
1274 iqk_info->iqk_tx_fail[0][path]);
1275 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_RXIQK_fail= %d,\n", path,
1276 iqk_info->iqk_rx_fail[0][path]);
1278 flag = iqk_info->lok_cor_fail[0][path];
1279 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FCOR << (path * 4), flag);
1280 flag = iqk_info->lok_fin_fail[0][path];
1281 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FFIN << (path * 4), flag);
1282 flag = iqk_info->iqk_tx_fail[0][path];
1283 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FTX << (path * 4), flag);
1284 flag = iqk_info->iqk_rx_fail[0][path];
1285 rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_F_RX << (path * 4), flag);
1287 tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD);
1288 iqk_info->bp_iqkenable[path] = tmp;
1289 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1290 iqk_info->bp_txkresult[path] = tmp;
1291 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD);
1292 iqk_info->bp_rxkresult[path] = tmp;
1297 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, B_IQKINF_FAIL << (path * 4));
1300 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_FCNT << (path * 4),
1304 static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1308 _iqk_txk_setting(rtwdev, path);
1309 iqk_info->lok_fail[path] = _iqk_lok(rtwdev, phy_idx, path);
1312 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path);
1314 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path);
1316 _iqk_rxk_setting(rtwdev, path);
1318 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path);
1320 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path);
1322 _iqk_info_iqk(rtwdev, phy_idx, path);
1326 enum rtw89_phy_idx phy, u8 path,
1334 iqk_info->iqk_band[path] = chan->band_type;
1335 iqk_info->iqk_bw[path] = chan->band_width;
1336 iqk_info->iqk_ch[path] = chan->channel;
1339 "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path,
1340 iqk_info->iqk_band[path]);
1342 path, iqk_info->iqk_bw[path]);
1344 path, iqk_info->iqk_ch[path]);
1346 "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", path, phy,
1348 iqk_info->iqk_band[path] == 0 ? "2G" :
1349 iqk_info->iqk_band[path] == 1 ? "5G" : "6G",
1350 iqk_info->iqk_ch[path],
1351 iqk_info->iqk_bw[path] == 0 ? "20M" :
1352 iqk_info->iqk_bw[path] == 1 ? "40M" : "80M");
1359 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BAND << (path * 16),
1360 iqk_info->iqk_band[path]);
1361 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BW << (path * 16),
1362 iqk_info->iqk_bw[path]);
1363 rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_CH << (path * 16),
1364 iqk_info->iqk_ch[path]);
1370 u8 path)
1372 _iqk_by_path(rtwdev, phy_idx, path);
1375 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
1380 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD,
1381 iqk_info->nb_txcfir[path]);
1382 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
1383 iqk_info->nb_rxcfir[path]);
1385 0x00001219 + (path << 4));
1387 fail = _iqk_check_cal(rtwdev, path, 0x12);
1394 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1395 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
1396 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1400 enum rtw89_phy_idx phy_idx, u8 path)
1402 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
1406 rtw8852c_disable_rxagc(rtwdev, path, 0x1);
1409 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
1415 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_IQC, idx);
1416 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, idx);
1417 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1423 enum rtw89_phy_idx phy_idx, u8 path)
1428 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
1429 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x1);
1430 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x0);
1431 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x1);
1432 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x0);
1435 rtw8852c_disable_rxagc(rtwdev, path, 0x0);
1436 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), MASKDWORD, 0xf801fffd);
1437 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_DPD_DIS, 0x1);
1438 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_DAC_VAL, 0x1);
1440 rtw8852c_txck_force(rtwdev, path, true, DAC_960M);
1441 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_DPD_GDIS, 0x1);
1443 rtw8852c_rxck_force(rtwdev, path, true, ADC_1920M);
1444 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK | (path << 13), B_ACK_VAL, 0x2);
1446 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW | (path << 13), B_P0_NRBW_DBG, 0x1);
1451 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x1);
1452 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x1);
1455 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
1461 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
1463 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
1465 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1466 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
1469 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
1472 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
1475 false, rtwdev, path, 0x1c, BIT(3));
1479 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
1480 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
1482 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
1486 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK),
1487 rtw89_read_rf(rtwdev, path, RR_RCKS, RFREG_MASK));
1493 u8 ch, path;
1510 for (path = 0; path < RTW8852C_IQK_SS; path++) {
1511 iqk_info->lok_cor_fail[ch][path] = false;
1512 iqk_info->lok_fin_fail[ch][path] = false;
1513 iqk_info->iqk_tx_fail[ch][path] = false;
1514 iqk_info->iqk_rx_fail[ch][path] = false;
1515 iqk_info->iqk_mcc_ch[ch][path] = 0x0;
1516 iqk_info->iqk_table_idx[path] = 0x0;
1522 enum rtw89_phy_idx phy_idx, u8 path,
1538 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx);
1540 _rfk_backup_rf_reg(rtwdev, backup_rf_val[path], path);
1541 _iqk_macbb_setting(rtwdev, phy_idx, path);
1542 _iqk_preset(rtwdev, path);
1543 _iqk_start_iqk(rtwdev, phy_idx, path);
1544 _iqk_restore(rtwdev, path);
1545 _iqk_afebb_restore(rtwdev, phy_idx, path);
1547 _rfk_restore_rf_reg(rtwdev, backup_rf_val[path], path);
1570 static void _rx_dck_value_rewrite(struct rtw89_dev *rtwdev, u8 path, u8 addr,
1582 rtw89_write_rf(rtwdev, path, RR_LUTPLL, RR_CAL_RW, 0x1);
1583 rtw89_write_rf(rtwdev, path, RR_RFC, RR_WCAL, 0x1);
1584 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x1);
1585 rtw89_write_rf(rtwdev, path, RR_LUTWA, MASKBYTE0, addr);
1586 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ofst_val);
1587 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ofst_val);
1588 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0);
1589 rtw89_write_rf(rtwdev, path, RR_RFC, RR_WCAL, 0x0);
1590 rtw89_write_rf(rtwdev, path, RR_LUTPLL, RR_CAL_RW, 0x0);
1597 static bool _rx_dck_rek_check(struct rtw89_dev *rtwdev, u8 path)
1607 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i]);
1608 i_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1609 q_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1614 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i]);
1615 i_even = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1616 q_even = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1624 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i] + 1);
1625 i_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1626 q_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1631 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i] + 1);
1632 i_odd = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1633 q_odd = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1645 static void _rx_dck_fix_if_need(struct rtw89_dev *rtwdev, u8 path, u8 addr,
1667 _rx_dck_value_rewrite(rtwdev, path, addr, val_i, val_q);
1670 static void _rx_dck_recover(struct rtw89_dev *rtwdev, u8 path)
1681 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i]);
1682 i_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1683 q_even_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1685 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr_bs[i] + 1);
1686 i_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1687 q_odd_bs = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1693 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i]);
1694 i_even = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1695 q_even = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1700 _rx_dck_fix_if_need(rtwdev, path, _dck_addr[i],
1707 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DCK, _dck_addr[i] + 1);
1708 i_odd = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_TIA);
1709 q_odd = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_TIA);
1714 _rx_dck_fix_if_need(rtwdev, path, _dck_addr[i] + 1,
1719 static void _rx_dck_toggle(struct rtw89_dev *rtwdev, u8 path)
1724 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
1725 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
1728 2, 2000, false, rtwdev, path,
1731 rtw89_warn(rtwdev, "[RX_DCK] S%d RXDCK timeout\n", path);
1733 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RX_DCK] S%d RXDCK finish\n", path);
1735 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
1738 static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path,
1743 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0);
1745 _rx_dck_toggle(rtwdev, path);
1746 if (rtw89_read_rf(rtwdev, path, RR_DCKC, RR_DCKC_CHK) == 0)
1748 res = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_DONE);
1750 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_IDAC, res);
1751 _rx_dck_toggle(rtwdev, path);
1752 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_IDAC, 0x1);
1835 enum rtw89_rf_path path, bool is_bybb)
1838 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1840 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1844 enum rtw89_rf_path path, bool off);
1847 u32 reg_bkup[][RTW8852C_DPK_KIP_REG_NUM], u8 path)
1852 reg_bkup[path][i] =
1853 rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD);
1856 reg[i] + (path << 8), reg_bkup[path][i]);
1861 u32 reg_bkup[][RTW8852C_DPK_KIP_REG_NUM], u8 path)
1866 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8),
1867 MASKDWORD, reg_bkup[path][i]);
1869 reg[i] + (path << 8), reg_bkup[path][i]);
1874 enum rtw89_rf_path path, enum rtw8852c_dpk_id id)
1880 dpk_cmd = (u16)((id << 8) | (0x19 + path * 0x12));
1909 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx)
1914 u8 kidx = dpk->cur_idx[path];
1916 dpk->bp[path][kidx].band = chan->band_type;
1917 dpk->bp[path][kidx].ch = chan->channel;
1918 dpk->bp[path][kidx].bw = chan->band_width;
1922 path, dpk->cur_idx[path], phy,
1923 rtwdev->is_tssi_mode[path] ? "on" : "off",
1925 dpk->bp[path][kidx].band == 0 ? "2G" :
1926 dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1927 dpk->bp[path][kidx].ch,
1928 dpk->bp[path][kidx].bw == 0 ? "20M" :
1929 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
1934 enum rtw89_rf_path path, u8 kpath)
1937 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x1);
1938 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x0);
1939 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x1);
1940 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x0);
1943 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0xd801dffd);
1946 rtw8852c_txck_force(rtwdev, path, true, DAC_960M);
1949 rtw8852c_rxck_force(rtwdev, path, true, ADC_1920M);
1950 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13),
1958 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x1);
1959 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x1);
1961 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE setting\n", path);
1964 static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev, u8 path)
1966 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13),
1968 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x1);
1969 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A1 << path, 0x0);
1970 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x1);
1971 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A3 << path, 0x0);
1972 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0x00000000);
1973 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), B_P0_TXCK_ALL, 0x00);
1974 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A0 << path, 0x0);
1975 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_A2 << path, 0x0);
1977 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE restore\n", path);
1981 enum rtw89_rf_path path, bool is_pause)
1983 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
1986 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
1990 static void _dpk_kip_control_rfc(struct rtw89_dev *rtwdev, u8 path, bool ctrl_by_kip)
1992 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), B_IQK_RFC_ON, ctrl_by_kip);
1997 static void _dpk_txpwr_bb_force(struct rtw89_dev *rtwdev, u8 path, bool force)
1999 rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13), B_TXPWRB_ON, force);
2000 rtw89_phy_write32_mask(rtwdev, R_TXPWRB_H + (path << 13), B_TXPWRB_RDY, force);
2003 path, force ? "on" : "off");
2007 enum rtw89_rf_path path)
2009 _dpk_one_shot(rtwdev, phy, path, D_KIP_RESTORE);
2010 _dpk_kip_control_rfc(rtwdev, path, false);
2011 _dpk_txpwr_bb_force(rtwdev, path, false);
2012 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
2017 enum rtw89_rf_path path)
2023 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1);
2026 _dpk_kip_control_rfc(rtwdev, path, false);
2028 cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB);
2029 rf_11 = rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK);
2030 reg_81cc = rtw89_phy_read32_mask(rtwdev, R_KIP_IQP + (path << 8),
2033 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
2034 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x3);
2035 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0xd);
2036 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, 0x1f);
2038 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x12);
2039 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, 0x3);
2041 _dpk_kip_control_rfc(rtwdev, path, true);
2045 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK);
2047 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
2048 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD));
2050 _dpk_kip_control_rfc(rtwdev, path, false);
2052 rtw89_write_rf(rtwdev, path, RR_TXIG, RFREG_MASK, rf_11);
2053 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, cur_rxbb);
2054 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, reg_81cc);
2058 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1);
2060 _dpk_kip_control_rfc(rtwdev, path, true);
2064 enum rtw89_rf_path path, u8 kidx)
2068 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
2069 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
2071 rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK);
2072 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x2);
2073 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x4);
2074 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
2075 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
2079 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK),
2080 rtw89_read_rf(rtwdev, path, RR_RXBB, RFREG_MASK),
2081 rtw89_read_rf(rtwdev, path, RR_TIA, RFREG_MASK),
2082 rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK),
2083 rtw89_read_rf(rtwdev, path, RR_LUTDBG, RFREG_MASK),
2084 rtw89_read_rf(rtwdev, path, 0x1001a, RFREG_MASK));
2086 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
2088 rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK);
2090 if (dpk->bp[path][kidx].band == RTW89_BAND_6G && dpk->bp[path][kidx].ch >= 161)
2091 rtw89_write_rf(rtwdev, path, RR_IQGEN, RR_IQGEN_BIAS, 0x8);
2093 rtw89_write_rf(rtwdev, path, RR_LOGEN, RR_LOGEN_RPT, 0xd);
2094 rtw89_write_rf(rtwdev, path, RR_TXAC, RR_TXAC_IQG, 0x8);
2096 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_ATT, 0x0);
2097 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT2, 0x3);
2098 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
2099 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
2101 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160)
2102 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_EBW, 0x0);
2106 static void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2110 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160) {
2113 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) {
2116 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) {
2124 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_160 ? "160M" :
2125 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
2126 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
2129 static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2144 dpk->corr_idx[path][kidx] = corr_idx;
2145 dpk->corr_val[path][kidx] = corr_val;
2157 path, corr_idx, corr_val, dc_i, dc_q);
2159 dpk->dc_i[path][kidx] = dc_i;
2160 dpk->dc_q[path][kidx] = dc_q;
2170 path, rxbb,
2208 static void _dpk_kset_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
2212 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0x10);
2214 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), 0xE0000000) - 1;
2218 enum rtw89_rf_path path, u8 dbm, bool set_from_bb)
2222 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] set S%d txagc to %ddBm\n", path, dbm);
2223 rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13), B_TXPWRB_VAL, dbm << 2);
2225 _dpk_one_shot(rtwdev, phy, path, D_TXAGC);
2226 _dpk_kset_query(rtwdev, path);
2230 enum rtw89_rf_path path, u8 kidx)
2232 _dpk_one_shot(rtwdev, phy, path, D_GAIN_LOSS);
2233 _dpk_kip_set_txagc(rtwdev, phy, path, 0xff, false);
2235 rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A1, 0x0);
2236 rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A0, 0x0);
2287 enum rtw89_rf_path path, u8 kidx)
2289 _dpk_kip_control_rfc(rtwdev, path, false);
2291 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
2292 _dpk_kip_control_rfc(rtwdev, path, true);
2294 _dpk_one_shot(rtwdev, phy, path, D_RXAGC);
2296 return _dpk_sync_check(rtwdev, path, kidx);
2315 static void _dpk_bypass_rxiqc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
2317 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1);
2318 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, 0x40000002);
2324 enum rtw89_rf_path path, u8 kidx, u8 init_xdbm, u8 loss_only)
2339 is_fail = _dpk_kip_set_rxagc(rtwdev, phy, path, kidx);
2352 _dpk_one_shot(rtwdev, phy, path, D_SYNC);
2357 if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
2358 _dpk_bypass_rxiqc(rtwdev, path);
2360 _dpk_lbk_rxiqk(rtwdev, phy, path);
2366 tmp_gl_idx = _dpk_gainloss(rtwdev, phy, path, kidx);
2387 _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true);
2399 _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true);
2406 _dpk_kip_control_rfc(rtwdev, path, false);
2407 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB);
2413 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, tmp_rxbb);
2416 _dpk_kip_control_rfc(rtwdev, path, true);
2454 enum rtw89_rf_path path, u8 kidx)
2469 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_5 ||
2470 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_10 ||
2471 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_20)
2473 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ||
2474 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80)
2482 _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL);
2491 _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL);
2498 _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL);
2503 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx)
2514 if (cur_band != dpk->bp[path][idx].band ||
2515 cur_ch != dpk->bp[path][idx].ch)
2518 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
2520 dpk->cur_idx[path] = idx;
2523 "[DPK] reload S%d[%d] success\n", path, idx);
2536 enum rtw89_rf_path path, u8 kidx)
2539 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
2543 R_DPD_CH0A + (path << 8) + (kidx << 2),
2547 R_DPD_CH0A + (path << 8) + (kidx << 2),
2550 _dpk_kip_control_rfc(rtwdev, path, true);
2551 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_MDPD, kidx);
2553 _dpk_one_shot(rtwdev, phy, path, D_KIP_PRESET);
2556 static void _dpk_para_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2563 para = rtw89_phy_read32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8),
2566 dpk->bp[path][kidx].txagc_dpk = FIELD_GET(_DPK_PARA_TXAGC, para);
2567 dpk->bp[path][kidx].ther_dpk = FIELD_GET(_DPK_PARA_THER, para);
2570 dpk->cur_k_set, dpk->bp[path][kidx].ther_dpk, dpk->bp[path][kidx].txagc_dpk);
2574 enum rtw89_rf_path path, u8 kidx, bool is_execute)
2579 rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8), B_DPK_GN_AG, 0x200);
2580 rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8), B_DPK_GN_EN, 0x3);
2582 _dpk_one_shot(rtwdev, phy, path, D_GAIN_NORM);
2584 rtw89_phy_write32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8),
2587 dpk->bp[path][kidx].gs =
2588 rtw89_phy_read32_mask(rtwdev, dpk_par_regs[kidx][dpk->cur_k_set] + (path << 8),
2621 enum rtw89_rf_path path, u8 kidx)
2625 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
2626 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0);
2627 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2630 dpk->bp[path][kidx].mdpd_en = BIT(dpk->cur_k_set);
2631 dpk->bp[path][kidx].path_ok = true;
2634 path, kidx, dpk->bp[path][kidx].mdpd_en);
2636 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2637 B_DPD_MEN, dpk->bp[path][kidx].mdpd_en);
2639 _dpk_gain_normalize_8852c(rtwdev, phy, path, kidx, false);
2643 enum rtw89_rf_path path, u8 gain)
2646 u8 kidx = dpk->cur_idx[path];
2651 "[DPK] ========= S%d[%d] DPK Start =========\n", path, kidx);
2652 _dpk_kip_control_rfc(rtwdev, path, false);
2653 _rf_direct_cntrl(rtwdev, path, false);
2654 rtw89_write_rf(rtwdev, path, RR_BBDC, RFREG_MASK, 0x03ffd);
2655 _dpk_rf_setting(rtwdev, gain, path, kidx);
2656 _set_rx_dck(rtwdev, phy, path, false);
2658 _dpk_kip_preset_8852c(rtwdev, phy, path, kidx);
2659 _dpk_txpwr_bb_force(rtwdev, path, true);
2660 _dpk_kip_set_txagc(rtwdev, phy, path, init_xdbm, true);
2661 _dpk_tpg_sel(rtwdev, path, kidx);
2663 is_fail = _dpk_agc(rtwdev, phy, path, kidx, init_xdbm, false);
2667 _dpk_idl_mpa(rtwdev, phy, path, kidx);
2668 _dpk_para_query(rtwdev, path, kidx);
2669 _dpk_on(rtwdev, phy, path, kidx);
2672 _dpk_kip_control_rfc(rtwdev, path, false);
2673 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RF_RX);
2674 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d]_K%d %s\n", path, kidx,
2680 static void _dpk_init(struct rtw89_dev *rtwdev, u8 path)
2683 u8 kidx = dpk->cur_idx[path];
2685 dpk->bp[path][kidx].path_ok = false;
2688 static void _dpk_drf_direct_cntrl(struct rtw89_dev *rtwdev, u8 path, bool is_bybb)
2691 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
2693 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
2704 u8 path;
2714 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2715 if (!(kpath & BIT(path)))
2718 reloaded[path] = _dpk_reload_check(rtwdev, phy, path,
2720 if (!reloaded[path] && dpk->bp[path][0].ch != 0)
2721 dpk->cur_idx[path] = !dpk->cur_idx[path];
2723 _dpk_onoff(rtwdev, path, false);
2726 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++)
2727 dpk->cur_idx[path] = 0;
2730 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2733 path, dpk->cur_idx[path]);
2734 _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path);
2735 _rfk_backup_rf_reg(rtwdev, backup_rf_val[path], path);
2736 _dpk_information(rtwdev, phy, path, chanctx_idx);
2737 _dpk_init(rtwdev, path);
2738 if (rtwdev->is_tssi_mode[path])
2739 _dpk_tssi_pause(rtwdev, path, true);
2742 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2745 path, dpk->cur_idx[path]);
2746 rtw8852c_disable_rxagc(rtwdev, path, 0x0);
2747 _dpk_drf_direct_cntrl(rtwdev, path, false);
2748 _dpk_bb_afe_setting(rtwdev, phy, path, kpath);
2749 is_fail = _dpk_main(rtwdev, phy, path, 1);
2750 _dpk_onoff(rtwdev, path, is_fail);
2753 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2756 path, dpk->cur_idx[path]);
2757 _dpk_kip_restore(rtwdev, phy, path);
2758 _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path);
2759 _rfk_restore_rf_reg(rtwdev, backup_rf_val[path], path);
2760 _dpk_bb_afe_restore(rtwdev, path);
2761 rtw8852c_disable_rxagc(rtwdev, path, 0x1);
2762 if (rtwdev->is_tssi_mode[path])
2763 _dpk_tssi_pause(rtwdev, path, false);
2795 u8 path, kpath;
2799 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2800 if (kpath & BIT(path))
2801 _dpk_onoff(rtwdev, path, true);
2823 enum rtw89_rf_path path, bool off)
2826 u8 val, kidx = dpk->cur_idx[path];
2828 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok ?
2829 dpk->bp[path][kidx].mdpd_en : 0;
2831 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2834 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
2841 u8 path, kidx;
2848 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++) {
2849 kidx = dpk->cur_idx[path];
2852 path, kidx, dpk->bp[path][kidx].ch);
2855 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), 0x0000003f);
2857 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), MASKBYTE2);
2859 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BTP + (path << 13), B_TXAGC_BTP);
2862 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xf);
2864 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_TH);
2866 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_OF);
2868 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_TSSI);
2871 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
2876 if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0)
2877 delta_ther = dpk->bp[path][kidx].ther_dpk - cur_ther;
2883 delta_ther, cur_ther, dpk->bp[path][kidx].ther_dpk);
2886 txagc_rf - dpk->bp[path][kidx].txagc_dpk, txagc_rf,
2887 dpk->bp[path][kidx].txagc_dpk);
2900 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
2907 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2927 if (path == RF_PATH_A) {
2943 enum rtw89_rf_path path)
2945 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2952 enum rtw89_rf_path path)
2954 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2960 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2964 if (path == RF_PATH_A) {
2978 enum rtw89_rf_path path)
2980 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2986 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3100 if (path == RF_PATH_A) {
3204 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3208 if (path == RF_PATH_A) {
3220 enum rtw89_rf_path path,
3226 if (path == RF_PATH_A) {
3246 enum rtw89_rf_path path)
3248 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3254 enum rtw89_rf_path path)
3256 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3262 enum rtw89_rf_path path)
3264 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3271 enum rtw89_rf_path path)
3273 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3281 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C;
3285 path = RF_PATH_A;
3288 path = RF_PATH_B;
3293 for (i = path; i < path_max; i++) {
3309 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C;
3313 path = RF_PATH_A;
3316 path = RF_PATH_B;
3321 for (i = path; i < path_max; i++) {
3631 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3645 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
3646 path, gidx);
3651 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
3652 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
3656 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3657 path, val, de_1st, de_2nd);
3659 val = tssi_info->tssi_mcs[path][gidx];
3662 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3668 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
3669 path, gidx);
3674 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st];
3675 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd];
3679 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3680 path, val, de_1st, de_2nd);
3682 val = tssi_info->tssi_6g_mcs[path][gidx];
3685 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3694 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3708 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3709 path, tgidx);
3714 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
3715 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
3719 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3720 path, val, tde_1st, tde_2nd);
3722 val = tssi_info->tssi_trim[path][tgidx];
3725 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3726 path, val);
3732 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3733 path, tgidx);
3738 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st];
3739 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd];
3743 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3744 path, val, tde_1st, tde_2nd);
3746 val = tssi_info->tssi_trim_6g[path][tgidx];
3749 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3750 path, val);
3766 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C;
3773 path = RF_PATH_A;
3776 path = RF_PATH_B;
3781 for (i = path; i < path_max; i++) {
3787 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
3804 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
3823 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3829 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0);
3830 rtw89_phy_write32_mask(rtwdev, tssi_en[path], BIT(31), 0x0);
3831 if (rtwdev->dbcc_en && path == RF_PATH_B)
3836 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1);
3837 rtw89_phy_write32_mask(rtwdev, tssi_en[path], BIT(31), 0x1);
3855 static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
3867 rf_reg18 = rtw89_read_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK);
3875 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x3);
3876 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xf);
3880 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x3);
3881 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xf);
3885 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x2);
3886 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xd);
3890 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, 0x1);
3891 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, 0xb);
3897 rtw89_write_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK, rf_reg18);
3904 u8 kpath, path;
3910 for (path = 0; path < 2; path++) {
3911 if (!(kpath & BIT(path)))
3915 _bw_setting(rtwdev, path, bw, is_dav);
3917 _bw_setting(rtwdev, path, bw, is_dav);
3921 if (path == RF_PATH_B && rtwdev->hal.cv == CHIP_CAV) {
3932 static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
3944 rf_reg18 = rtw89_read_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK);
3964 rtw89_write_rf(rtwdev, path, reg_reg18_addr, RFREG_MASK, rf_reg18);
3971 u8 kpath, path;
3986 for (path = 0; path < 2; path++) {
3987 if (kpath & BIT(path)) {
3988 _ch_setting(rtwdev, path, central_ch, band, true);
3989 _ch_setting(rtwdev, path, central_ch, band, false);
3998 u8 path;
4002 for (path = 0; path < 2; path++) {
4003 if (!(kpath & BIT(path)))
4006 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
4007 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0xa);
4023 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, val);
4024 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
4031 int path;
4033 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
4034 lck->thermal[path] =
4035 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
4037 "[LCK] path=%d thermal=0x%x", path, lck->thermal[path]);
4044 int path = rtwdev->dbcc_en ? 2 : 1;
4052 for (i = 0; i < path; i++) {
4068 int path;
4070 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
4072 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
4073 delta = abs((int)cur_thermal - lck->thermal[path]);
4076 "[LCK] path=%d current thermal=0x%x delta=0x%x\n",
4077 path, cur_thermal, delta);
4149 u8 path;
4151 for (path = 0; path < 2; path++)
4152 _rck(rtwdev, path);
4187 u8 path, kpath;
4197 for (path = 0; path < 2; path++) {
4198 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
4199 if (!(kpath & BIT(path)))
4202 if (rtwdev->is_tssi_mode[path])
4203 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
4205 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
4206 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
4207 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_LO_SEL, rtwdev->dbcc_en);
4210 _set_rx_dck(rtwdev, phy, path, is_afe);
4216 _rx_dck_recover(rtwdev, path);
4220 is_fail = _rx_dck_rek_check(rtwdev, path);
4226 path, rek_cnt);
4228 rx_dck->thermal[path] = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
4229 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
4231 if (rtwdev->is_tssi_mode[path])
4232 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
4255 int path;
4263 for (path = 0; path < RF_PATH_NUM_8852C; path++) {
4265 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
4266 delta = abs((int)cur_thermal - rx_dck->thermal[path]);
4269 "[RX_DCK] path=%d current thermal=0x%x delta=0x%x\n",
4270 path, cur_thermal, delta);
4282 for (path = 0; path < RF_PATH_NUM_8852C; path++) {
4289 for (path = 0; path < RF_PATH_NUM_8852C; path++)
4329 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C;
4335 path = RF_PATH_A;
4338 path = RF_PATH_B;
4345 for (i = path; i < path_max; i++) {
4365 u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C;
4377 path = RF_PATH_A;
4380 path = RF_PATH_B;
4387 for (i = path; i < path_max; i++) {
4459 u8 path;
4464 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++)
4465 _dpk_onoff(rtwdev, path, false);
4469 for (path = 0; path < RTW8852C_DPK_RF_PATH; path++)
4470 _dpk_onoff(rtwdev, path, false);