Lines Matching refs:rtwdev

176 static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev, u32 backup_bb_reg_val[])
182 			rtw89_phy_read32_mask(rtwdev, rtw8852b_backup_bb_regs[i],
184 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
190 static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev, u32 backup_rf_reg_val[],
197 			rtw89_read_rf(rtwdev, rf_path,
199 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
205 static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev,
211 		rtw89_phy_write32_mask(rtwdev, rtw8852b_backup_bb_regs[i],
213 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
219 static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev,
225 		rtw89_write_rf(rtwdev, rf_path, rtw8852b_backup_rf_regs[i],
228 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
234 static void _rfk_rf_direct_cntrl(struct rtw89_dev *rtwdev,
238 		rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
240 		rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
243 static void _rfk_drf_direct_cntrl(struct rtw89_dev *rtwdev,
247 		rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
249 		rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
252 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path)
259 				       1, 8200, false, rtwdev, 0xbff8, MASKBYTE0);
261 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]NCTL1 IQK timeout!!!\n");
266 		fail = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
267 	rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0);
269 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret);
270 	val = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD);
271 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8008 = 0x%x\n", path, val);
276 static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
280 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]dbcc_en: %x,PHY%d\n",
281 		    rtwdev->dbcc_en, phy_idx);
283 	if (!rtwdev->dbcc_en) {
294 static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
297 	rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0);
298 	rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
299 	rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
303 static void _rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
308 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
310 		    RTW8852B_RXDCK_VER, rtwdev->hal.cv);
313 		rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
314 		dck_tune = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE);
316 		if (rtwdev->is_tssi_mode[path])
317 			rtw89_phy_write32_mask(rtwdev,
321 		rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
322 		rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0);
323 		rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
324 		_set_rx_dck(rtwdev, phy, path);
325 		rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune);
326 		rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
328 		if (rtwdev->is_tssi_mode[path])
329 			rtw89_phy_write32_mask(rtwdev,
335 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
342 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
344 	rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
346 	rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
347 	rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
349 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%05x\n",
350 		    rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
353 	rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
356 				       false, rtwdev, path, RR_RCKS, BIT(3));
358 	rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
360 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] rck_val = 0x%x, ret = %d\n",
363 	rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
364 	rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
366 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF 0x1b = 0x%x\n",
367 		    rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK));
370 static void _afe_init(struct rtw89_dev *rtwdev)
372 	rtw89_write32(rtwdev, R_AX_PHYREG_SET, 0xf);
374 	rtw89_rfk_parser(rtwdev, &rtw8852b_afe_init_defs_tbl);
377 static void _drck(struct rtw89_dev *rtwdev)
383 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]Ddie RCK start!!!\n");
384 	rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_KICK, 0x1);
387 				       false, rtwdev, R_DRCK_RS, B_DRCK_RS_DONE);
389 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DRCK timeout\n");
391 	rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_KICK, 0x0);
392 	rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x1);
394 	rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x0);
395 	rck_d = rtw89_phy_read32_mask(rtwdev, R_DRCK_RS, B_DRCK_RS_LPS);
396 	rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_SEL, 0x0);
397 	rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_CV, rck_d);
399 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0xc0cc = 0x%x\n",
400 		    rtw89_phy_read32_mask(rtwdev, R_DRCK_V1, MASKDWORD));
403 static void _addck_backup(struct rtw89_dev *rtwdev)
405 	struct rtw89_dack_info *dack = &rtwdev->dack;
407 	rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x0);
408 	dack->addck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A0);
409 	dack->addck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A1);
411 	rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x0);
412 	dack->addck_d[1][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1, B_ADDCKR1_A0);
413 	dack->addck_d[1][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1, B_ADDCKR1_A1);
416 static void _addck_reload(struct rtw89_dev *rtwdev)
418 	struct rtw89_dack_info *dack = &rtwdev->dack;
421 	rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK0D_VAL, dack->addck_d[0][0]);
422 	rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_VAL, dack->addck_d[0][1] >> 6);
423 	rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK0D_VAL2, dack->addck_d[0][1] & 0x3f);
424 	rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_MAN, 0x3);
427 	rtw89_phy_write32_mask(rtwdev, R_ADDCK1D, B_ADDCK1D_VAL, dack->addck_d[1][0]);
428 	rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK0_VAL, dack->addck_d[1][1] >> 6);
429 	rtw89_phy_write32_mask(rtwdev, R_ADDCK1D, B_ADDCK1D_VAL2, dack->addck_d[1][1] & 0x3f);
430 	rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_MAN, 0x3);
433 static void _dack_backup_s0(struct rtw89_dev *rtwdev)
435 	struct rtw89_dack_info *dack = &rtwdev->dack;
438 	rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
441 		rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_V, i);
443 			rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0M0);
444 		rtw89_phy_write32_mask(rtwdev, R_DCOF8, B_DCOF8_V, i);
446 			rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0M1);
450 		rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS00, B_DACK_BIAS00);
452 		rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS01, B_DACK_BIAS01);
455 		rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK00, B_DACK_DADCK00);
457 		rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK01, B_DACK_DADCK01);
460 static void _dack_backup_s1(struct rtw89_dev *rtwdev)
462 	struct rtw89_dack_info *dack = &rtwdev->dack;
465 	rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
468 		rtw89_phy_write32_mask(rtwdev, R_DACK10, B_DACK10, i);
470 			rtw89_phy_read32_mask(rtwdev, R_DACK10S, B_DACK10S);
471 		rtw89_phy_write32_mask(rtwdev, R_DACK11, B_DACK11, i);
473 			rtw89_phy_read32_mask(rtwdev, R_DACK11S, B_DACK11S);
477 		rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS10, B_DACK_BIAS10);
479 		rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS11, B_DACK_BIAS11);
482 		rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK10, B_DACK_DADCK10);
484 		rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK11, B_DACK_DADCK11);
487 static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
493 	rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
498 		tmp = rtw89_phy_read32_mask(rtwdev, R_DBG32_D, MASKDWORD);
506 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
510 static void _addck(struct rtw89_dev *rtwdev)
512 	struct rtw89_dack_info *dack = &rtwdev->dack;
517 	rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_MAN, 0x0);
518 	rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 0x30, 0x0);
519 	rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
520 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x0);
521 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0);
522 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1);
523 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xf);
524 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x0);
525 	rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, BIT(1), 0x1);
526 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3);
528 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S0 ADDCK\n");
529 	_check_addc(rtwdev, RF_PATH_A);
531 	rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_TRG, 0x1);
532 	rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_TRG, 0x0);
534 	rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x1);
537 				       false, rtwdev, R_ADDCKR0, BIT(0));
539 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n");
542 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
543 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 ADDCK\n");
544 	_check_addc(rtwdev, RF_PATH_A);
546 	rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, BIT(1), 0x0);
547 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x1);
548 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xc);
549 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x1);
550 	rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0);
553 	rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
554 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x0);
555 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0);
556 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1);
557 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xf);
558 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x0);
559 	rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, BIT(1), 0x1);
560 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3);
562 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S1 ADDCK\n");
563 	_check_addc(rtwdev, RF_PATH_B);
565 	rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_TRG, 0x1);
566 	rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_TRG, 0x0);
568 	rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x1);
571 				       false, rtwdev, R_ADDCKR1, BIT(0));
573 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADDCK timeout\n");
576 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
577 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 ADDCK\n");
578 	_check_addc(rtwdev, RF_PATH_B);
580 	rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, BIT(1), 0x0);
581 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x1);
582 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xc);
583 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x1);
584 	rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0);
587 static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
589 	rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
593 	_check_addc(rtwdev, path);
595 	rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
600 static bool _dack_s0_check_done(struct rtw89_dev *rtwdev, bool part1)
603 		if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P0, B_DACK_S0P0_OK) == 0 ||
604 		    rtw89_phy_read32_mask(rtwdev, R_DACK_S0P1, B_DACK_S0P1_OK) == 0)
607 		if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0P2_OK) == 0 ||
608 		    rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0P3_OK) == 0)
615 static void _dack_s0(struct rtw89_dev *rtwdev)
617 	struct rtw89_dack_info *dack = &rtwdev->dack;
621 	rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s0_1_defs_tbl);
624 				       false, rtwdev, true);
626 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK timeout\n");
629 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
631 	rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s0_2_defs_tbl);
634 				       false, rtwdev, false);
636 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DADCK timeout\n");
639 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
641 	rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s0_3_defs_tbl);
643 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 DADCK\n");
645 	_dack_backup_s0(rtwdev);
646 	rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0);
649 static bool _dack_s1_check_done(struct rtw89_dev *rtwdev, bool part1)
652 		if (rtw89_phy_read32_mask(rtwdev, R_DACK_S1P0, B_DACK_S1P0_OK) == 0 &&
653 		    rtw89_phy_read32_mask(rtwdev, R_DACK_S1P1, B_DACK_S1P1_OK) == 0)
656 		if (rtw89_phy_read32_mask(rtwdev, R_DACK10S, B_DACK_S1P2_OK) == 0 &&
657 		    rtw89_phy_read32_mask(rtwdev, R_DACK11S, B_DACK_S1P3_OK) == 0)
664 static void _dack_s1(struct rtw89_dev *rtwdev)
666 	struct rtw89_dack_info *dack = &rtwdev->dack;
670 	rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s1_1_defs_tbl);
673 				       false, rtwdev, true);
675 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK timeout\n");
678 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
680 	rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s1_2_defs_tbl);
683 				       false, rtwdev, false);
685 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DADCK timeout\n");
688 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
690 	rtw89_rfk_parser(rtwdev, &rtw8852b_dack_s1_3_defs_tbl);
692 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 DADCK\n");
694 	_check_dadc(rtwdev, RF_PATH_B);
695 	_dack_backup_s1(rtwdev);
696 	rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0);
699 static void _dack(struct rtw89_dev *rtwdev)
701 	_dack_s0(rtwdev);
702 	_dack_s1(rtwdev);
705 static void _dack_dump(struct rtw89_dev *rtwdev)
707 	struct rtw89_dack_info *dack = &rtwdev->dack;
711 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
714 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
717 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
720 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
723 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
726 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
730 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
733 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
736 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
739 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
742 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n");
745 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
748 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n");
751 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
755 static void _dac_cal(struct rtw89_dev *rtwdev, bool force)
757 	struct rtw89_dack_info *dack = &rtwdev->dack;
761 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK 0x1\n");
762 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK start!!!\n");
764 	rf0_0 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK);
765 	rf1_0 = rtw89_read_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK);
766 	_afe_init(rtwdev);
767 	_drck(rtwdev);
769 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0);
770 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0);
771 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x337e1);
772 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x337e1);
773 	_addck(rtwdev);
774 	_addck_backup(rtwdev);
775 	_addck_reload(rtwdev);
777 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0);
778 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0);
779 	_dack(rtwdev);
780 	_dack_dump(rtwdev);
783 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, rf0_0);
784 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, rf1_0);
785 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1);
786 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1);
788 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n");
791 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
793 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
798 		rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
799 		rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1);
800 		tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
801 		rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
804 		rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
805 		rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1);
806 		tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
807 		rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
814 static bool _iqk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
817 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
823 		rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
827 		rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
831 		rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
835 		rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
843 		rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
848 		rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
849 		rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x011);
853 		rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
854 		rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
861 	rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1);
863 	fail = _iqk_check_cal(rtwdev, path);
864 	rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
869 static bool _rxk_group_sel(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
872 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
880 			rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
882 			rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G,
884 			rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G,
888 			rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
890 			rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT,
892 			rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2,
899 		rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
901 		rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
903 		rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
905 		fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
906 		rtw89_phy_write32_mask(rtwdev, R_IQKINF,
910 	rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
914 		rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
919 		rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
927 static bool _iqk_nbrxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
930 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
937 		rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
939 		rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G,
941 		rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G,
945 		rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM,
947 		rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_HATT,
949 		rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_CC2,
956 	rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
957 	rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x0);
958 	rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP_V1, gp);
959 	rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
962 	fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
963 	rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail);
965 	rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
969 			 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD) | 0x2;
976 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
978 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
981 		rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
982 		rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
984 		rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x0f);
986 		rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x03);
987 		rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa001);
989 		rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041);
990 		rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_VAL, 0x2);
991 		rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ON, 0x1);
992 		rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_VAL, 0x2);
993 		rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_ON, 0x1);
994 		rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON, 0x1);
995 		rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x1);
997 		rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
998 		rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
1000 		rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x0f);
1002 		rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x03);
1003 		rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa001);
1005 		rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041);
1006 		rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_VAL, 0x1);
1007 		rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ON, 0x1);
1008 		rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_VAL, 0x1);
1009 		rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_ON, 0x1);
1010 		rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON, 0x1);
1011 		rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x0);
1015 static bool _txk_group_sel(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1017 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1025 			rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
1027 			rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
1029 			rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
1031 			rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1035 			rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
1037 			rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
1039 			rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
1041 			rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1048 		rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1050 		rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1052 		rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1054 		rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1056 		rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1057 		fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
1058 		rtw89_phy_write32_mask(rtwdev, R_IQKINF,
1065 		rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
1070 		rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
1078 static bool _iqk_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1080 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1086 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
1088 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
1090 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
1092 		rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1096 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0,
1098 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1,
1100 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG,
1102 		rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1109 	rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
1110 	rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x1);
1111 	rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G2, 0x0);
1112 	rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp);
1113 	rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1114 	kfail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1118 			rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8),
1126 static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias)
1128 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1130 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1131 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias);
1133 	rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2);
1135 		rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0);
1137 		rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1);
1138 	rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias);
1139 	rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
1140 	rtw89_write_rf(rtwdev, path, RR_TXVBUF, RR_TXVBUF_DACEN, 0x1);
1142 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x7c = %x\n", path,
1143 		    rtw89_read_rf(rtwdev, path, RR_TXVBUF, RFREG_MASK));
1146 static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path)
1148 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1157 	tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK);
1169 	tmp = rtw89_read_rf(rtwdev, path, RR_LOKVB, RFREG_MASK);
1180 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
1183 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
1190 static bool _iqk_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1192 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1195 	rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
1199 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1200 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6);
1203 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
1204 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x4);
1212 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1215 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1221 	rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9);
1222 	tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE);
1227 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1230 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1236 	rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24);
1237 	tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
1241 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1244 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0);
1250 	rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9);
1251 	rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
1252 	tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE);
1257 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1260 		rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12);
1266 	rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24);
1267 	_iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_VBUFFER);
1269 	return _lok_finetune_check(rtwdev, path);
1272 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
1274 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1278 		rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW2, 0x00);
1279 		rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0);
1280 		rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0);
1281 		rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1);
1282 		rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1283 		rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1284 		rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x00);
1285 		rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e);
1289 		rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00);
1290 		rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x1);
1291 		rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0);
1292 		rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1293 		rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x80);
1294 		rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e);
1302 static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path)
1304 	rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
1305 	rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1);
1307 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f);
1309 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13);
1310 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001);
1312 	rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041);
1315 static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1317 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1322 	rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FCOR << (path * 4), flag);
1324 	rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FFIN << (path * 4), flag);
1326 	rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_FTX << (path * 4), flag);
1328 	rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_F_RX << (path * 4), flag);
1330 	tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD);
1332 	tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1334 	tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD);
1337 	rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_KCNT, iqk_info->iqk_times);
1339 	tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, B_IQKINF_FAIL << (path * 4));
1342 	rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_FCNT << (path * 4),
1346 static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1348 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1354 	_iqk_txclk_setting(rtwdev, path);
1358 		_lok_res_table(rtwdev, path, ibias++);
1359 		_iqk_txk_setting(rtwdev, path);
1360 		lok_is_fail = _iqk_lok(rtwdev, phy_idx, path);
1366 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] LOK (%d) fail\n", path);
1370 		iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path);
1372 		iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path);
1375 	_iqk_rxclk_setting(rtwdev, path);
1376 	_iqk_rxk_setting(rtwdev, path);
1378 		iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path);
1380 		iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path);
1382 	_iqk_info_iqk(rtwdev, phy_idx, path);
1385 static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path,
1388 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
1389 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1401 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] (1)idx = %x\n", idx);
1408 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] (2)idx = %x\n", idx);
1410 	reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
1411 	reg_35c = rtw89_phy_read32_mask(rtwdev, R_CIRST, B_CIRST_SYN);
1419 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x18= 0x%x, idx = %x\n",
1421 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x18= 0x%x\n",
1423 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]times = 0x%x, ch =%x\n",
1425 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_mcc_ch[%x][%x] = 0x%x\n",
1433 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
1437 	rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_VER, RTW8852B_IQK_VER);
1439 	rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BAND << (path * 16),
1442 	rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_BW << (path * 16),
1444 	rtw89_phy_write32_mask(rtwdev, R_IQKCH, B_IQKCH_CH << (path * 16),
1448 static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)
1450 	_iqk_by_path(rtwdev, phy_idx, path);
1453 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
1455 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1458 	rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD,
1460 	rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
1462 	rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD,
1464 	fail = _iqk_check_cal(rtwdev, path);
1466 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s result =%x\n", __func__, fail);
1468 	rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1469 	rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000000);
1470 	rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000);
1471 	rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS, B_IQK_RES_K, 0x0);
1472 	rtw89_phy_write32_mask(rtwdev, R_IQRSN, B_IQRSN_K1, 0x0);
1473 	rtw89_phy_write32_mask(rtwdev, R_IQRSN, B_IQRSN_K2, 0x0);
1474 	rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1475 	rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1476 	rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0x3);
1477 	rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1478 	rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
1481 static void _iqk_afebb_restore(struct rtw89_dev *rtwdev,
1489 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "===> %s\n", __func__);
1491 	kpath = _kpath(rtwdev, phy_idx);
1504 		rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
1507 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
1509 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1513 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] (3)idx = %x\n", idx);
1515 	rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_IQC, idx);
1516 	rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, idx);
1518 	rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1519 	rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
1520 	rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
1521 	rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a);
1523 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x54 = 0x%x\n", path, 1 << path,
1524 		    rtw89_phy_read32_mask(rtwdev, R_CFIR_LUT + (path << 8), MASKDWORD));
1525 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x04 = 0x%x\n", path, 1 << path,
1526 		    rtw89_phy_read32_mask(rtwdev, R_COEF_SEL + (path << 8), MASKDWORD));
1529 static void _iqk_macbb_setting(struct rtw89_dev *rtwdev,
1537 	kpath = _kpath(rtwdev, phy_idx);
1550 		rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
1553 static void _iqk_init(struct rtw89_dev *rtwdev)
1555 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1558 	rtw89_phy_write32_mask(rtwdev, R_IQKINF, MASKDWORD, 0x0);
1562 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1584 static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
1596 					       rtwdev, path, RR_MOD, RR_MOD_MASK);
1597 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
1602 static void _tmac_tx_pause(struct rtw89_dev *rtwdev, enum rtw89_phy_idx band_idx,
1608 	_wait_rx_mode(rtwdev, _kpath(rtwdev, band_idx));
1611 static void _doiqk(struct rtw89_dev *rtwdev, bool force,
1615 	struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1618 	u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB, chanctx_idx);
1620 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
1622 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
1627 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
1628 	_iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx);
1630 	_rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
1631 	_rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1632 	_iqk_macbb_setting(rtwdev, phy_idx, path);
1633 	_iqk_preset(rtwdev, path);
1634 	_iqk_start_iqk(rtwdev, phy_idx, path);
1635 	_iqk_restore(rtwdev, path);
1636 	_iqk_afebb_restore(rtwdev, phy_idx, path);
1637 	_rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
1638 	_rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1640 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
1643 static void _iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool force,
1646 	u8 kpath = _kpath(rtwdev, phy_idx);
1650 		_doiqk(rtwdev, force, phy_idx, RF_PATH_A, chanctx_idx);
1653 		_doiqk(rtwdev, force, phy_idx, RF_PATH_B, chanctx_idx);
1656 		_doiqk(rtwdev, force, phy_idx, RF_PATH_A, chanctx_idx);
1657 		_doiqk(rtwdev, force, phy_idx, RF_PATH_B, chanctx_idx);
1664 static void _dpk_bkup_kip(struct rtw89_dev *rtwdev, const u32 reg[],
1671 			rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD);
1672 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n",
1677 static void _dpk_reload_kip(struct rtw89_dev *rtwdev, const u32 reg[],
1683 		rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD,
1685 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Reload 0x%x = %x\n",
1690 static u8 _dpk_order_convert(struct rtw89_dev *rtwdev)
1695 	order = rtw89_phy_read32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP);
1698 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] convert MDPD order to 0x%x\n", val);
1703 static void _dpk_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, bool off)
1705 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1710 	rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
1711 			       MASKBYTE3, _dpk_order_convert(rtwdev) << 1 | val);
1713 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
1717 static void _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
1725 	rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, dpk_cmd);
1729 				       rtwdev, 0xbff8, MASKBYTE0);
1731 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot over 20ms!!!!\n");
1735 	rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00030000);
1739 				       rtwdev, 0x80fc, MASKLWORD);
1741 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot over 20ms!!!!\n");
1743 	rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0);
1745 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
1759 static void _dpk_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
1762 	rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3);
1763 	_set_rx_dck(rtwdev, phy, path);
1766 static void _dpk_information(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
1769 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
1770 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1778 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
1781 		    rtwdev->is_tssi_mode[path] ? "on" : "off",
1782 		    rtwdev->dbcc_en ? "on" : "off",
1790 static void _dpk_bb_afe_setting(struct rtw89_dev *rtwdev,
1795 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
1797 	rtw89_rfk_parser(rtwdev, &rtw8852b_dpk_afe_defs_tbl);
1800 		rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_EX, 0x1);
1801 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, B_PATH1_BW_SEL_EX, 0x1);
1804 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
1808 static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev,
1813 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
1815 	rtw89_rfk_parser(rtwdev, &rtw8852b_dpk_afe_restore_defs_tbl);
1817 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
1821 		rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_EX, 0x0);
1822 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,  B_PATH1_BW_SEL_EX, 0x0);
1826 static void _dpk_tssi_pause(struct rtw89_dev *rtwdev,
1829 	rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
1832 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
1836 static void _dpk_kip_restore(struct rtw89_dev *rtwdev,
1839 	rtw89_rfk_parser(rtwdev, &rtw8852b_dpk_kip_defs_tbl);
1841 	if (rtwdev->hal.cv > CHIP_CAV)
1842 		rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), B_DPD_COM_OF, 0x1);
1844 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
1847 static void _dpk_lbk_rxiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
1853 	cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB);
1855 	rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x1);
1856 	rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR, 0x0);
1858 	tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
1859 	rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
1860 	rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0xd);
1861 	rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1);
1864 		rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x13);
1866 		rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x00);
1868 		rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x05);
1870 	rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x0);
1871 	rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
1872 	rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80014);
1875 	rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
1876 	rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x025);
1878 	_dpk_one_shot(rtwdev, phy, path, LBK_RXIQK);
1880 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
1881 		    rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD));
1883 	rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
1884 	rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0);
1885 	rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x0);
1886 	rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, B_KPATH_CFG_ED, 0x0);
1887 	rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1);
1888 	rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0x5);
1891 static void _dpk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx, enum rtw89_rf_path path)
1893 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1895 	rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
1896 	rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0);
1897 	rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1);
1901 	dpk->bp[path][kidx].ther_dpk = rtw89_read_rf(rtwdev, path, RR_TM, RR_TM_VAL);
1903 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] thermal@DPK = 0x%x\n",
1907 static void _dpk_rf_setting(struct rtw89_dev *rtwdev, u8 gain,
1910 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1913 		rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220);
1914 		rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_FATT, 0xf2);
1915 		rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
1916 		rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
1918 		rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220);
1919 		rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SWATT, 0x5);
1920 		rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1);
1921 		rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1);
1922 		rtw89_write_rf(rtwdev, path, RR_RXA_LNA, RFREG_MASK, 0x920FC);
1923 		rtw89_write_rf(rtwdev, path, RR_XALNA2, RFREG_MASK, 0x002C0);
1924 		rtw89_write_rf(rtwdev, path, RR_IQGEN, RFREG_MASK, 0x38800);
1927 	rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1);
1928 	rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
1929 	rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0);
1931 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
1933 		    rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK),
1934 		    rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK),
1935 		    rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK));
1938 static void _dpk_bypass_rxcfir(struct rtw89_dev *rtwdev,
1942 		rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1944 		rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1946 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
1948 			    rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
1951 		rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2);
1952 		rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS);
1953 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
1955 			    rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
1961 void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
1963 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1966 		rtw89_phy_write32_clr(rtwdev, R_TPG_MOD, B_TPG_MOD_F);
1968 		rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2);
1970 		rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1);
1972 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] TPG_Select for %s\n",
1977 static void _dpk_table_select(struct rtw89_dev *rtwdev,
1983 	rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val);
1984 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
1989 static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
1994 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1998 	rtw89_phy_write32_clr(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL);
2000 	corr_idx = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORI);
2001 	corr_val = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORV);
2003 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
2010 	rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9);
2012 	dc_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
2013 	dc_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ);
2018 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d DC I/Q, = %d / %d\n",
2031 static bool _dpk_sync(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2034 	_dpk_one_shot(rtwdev, phy, path, SYNC);
2036 	return _dpk_sync_check(rtwdev, path, kidx);
2039 static u16 _dpk_dgain_read(struct rtw89_dev *rtwdev)
2043 	rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0);
2045 	dgain = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
2047 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x\n", dgain);
2052 static s8 _dpk_dgain_mapping(struct rtw89_dev *rtwdev, u16 dgain)
2095 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain offset = %d\n", offset);
2100 static u8 _dpk_gainloss_read(struct rtw89_dev *rtwdev)
2102 	rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6);
2103 	rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1);
2105 	return rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_GL);
2108 static void _dpk_gainloss(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2111 	_dpk_table_select(rtwdev, path, kidx, 1);
2112 	_dpk_one_shot(rtwdev, phy, path, GAIN_LOSS);
2115 static void _dpk_kip_preset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2118 	_dpk_tpg_sel(rtwdev, path, kidx);
2119 	_dpk_one_shot(rtwdev, phy, path, KIP_PRESET);
2122 static void _dpk_kip_pwr_clk_on(struct rtw89_dev *rtwdev,
2125 	rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
2126 	rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a);
2127 	rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08);
2129 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] KIP Power/CLK on\n");
2132 static void _dpk_kip_set_txagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2135 	rtw89_write_rf(rtwdev, path, RR_TXAGC, RFREG_MASK, txagc);
2136 	rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
2137 	_dpk_one_shot(rtwdev, phy, path, DPK_TXAGC);
2138 	rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
2140 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] set TXAGC = 0x%x\n", txagc);
2143 static void _dpk_kip_set_rxagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2148 	tmp = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
2149 	rtw89_phy_write32_mask(rtwdev, R_KIP_MOD, B_KIP_MOD, tmp);
2150 	rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1);
2151 	_dpk_one_shot(rtwdev, phy, path, DPK_RXAGC);
2152 	rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0);
2153 	rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL_V1, 0x8);
2155 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
2157 		    rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_RXBB_V1),
2158 		    rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB));
2161 static u8 _dpk_set_offset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2166 	txagc = rtw89_read_rf(rtwdev, path, RR_TXAGC, RFREG_MASK);
2175 	_dpk_kip_set_txagc(rtwdev, phy, path, txagc);
2177 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp_txagc (GL=%d) = 0x%x\n",
2182 static bool _dpk_pas_read(struct rtw89_dev *rtwdev, bool is_check)
2187 	rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06);
2188 	rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x0);
2189 	rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08);
2192 		rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00);
2193 		val1_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
2195 		val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
2198 		rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f);
2199 		val2_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
2201 		val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
2204 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n",
2209 			rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, i);
2210 			rtw89_debug(rtwdev, RTW89_DBG_RFK,
2212 				    rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD));
2223 static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2227 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
2240 			if (_dpk_sync(rtwdev, phy, path, kidx)) {
2246 			dgain = _dpk_dgain_read(rtwdev);
2255 			tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD,
2257 			offset = _dpk_dgain_mapping(rtwdev, dgain);
2269 			rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKRXBB,
2271 			rtw89_debug(rtwdev, RTW89_DBG_RFK,
2275 					_dpk_bypass_rxcfir(rtwdev, path, true);
2277 					_dpk_lbk_rxiqk(rtwdev, phy, path);
2288 			_dpk_gainloss(rtwdev, phy, path, kidx);
2289 			tmp_gl_idx = _dpk_gainloss_read(rtwdev);
2291 			if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true)) ||
2303 				rtw89_debug(rtwdev, RTW89_DBG_RFK,
2306 				tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0x3);
2315 				rtw89_debug(rtwdev, RTW89_DBG_RFK,
2318 				tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0xfe);
2324 			tmp_txagc = _dpk_set_offset(rtwdev, phy, path, tmp_gl_idx);
2335 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
2342 static void _dpk_set_mdpd_para(struct rtw89_dev *rtwdev, u8 order)
2346 		rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
2347 		rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x3);
2348 		rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x1);
2351 		rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
2352 		rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN);
2353 		rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN);
2356 		rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order);
2357 		rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN);
2358 		rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN);
2361 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
2366 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
2370 static void _dpk_idl_mpa(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2373 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2377 		_dpk_set_mdpd_para(rtwdev, 0x2);
2379 		_dpk_set_mdpd_para(rtwdev, 0x0);
2381 	_dpk_one_shot(rtwdev, phy, path, MDPK_IDL);
2384 static void _dpk_fill_result(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2387 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2391 	rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
2394 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
2399 	rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8),
2403 	rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
2406 	rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
2407 	rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0);
2411 		rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2414 		rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2417 	rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2418 			       B_DPD_ORDER_V1, _dpk_order_convert(rtwdev));
2419 	rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD, 0x0);
2420 	rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_SEL, 0x0);
2423 static bool _dpk_reload_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2426 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
2427 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2439 		rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
2443 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
2450 static bool _dpk_main(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2454 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2458 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
2461 	_rfk_rf_direct_cntrl(rtwdev, path, false);
2462 	_rfk_drf_direct_cntrl(rtwdev, path, false);
2464 	_dpk_kip_pwr_clk_on(rtwdev, path);
2465 	_dpk_kip_set_txagc(rtwdev, phy, path, txagc);
2466 	_dpk_rf_setting(rtwdev, gain, path, kidx);
2467 	_dpk_rx_dck(rtwdev, phy, path);
2469 	_dpk_kip_preset(rtwdev, phy, path, kidx);
2470 	_dpk_kip_set_rxagc(rtwdev, phy, path);
2471 	_dpk_table_select(rtwdev, path, kidx, gain);
2473 	txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false, chanctx_idx);
2474 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Adjust txagc = 0x%x\n", txagc);
2479 		_dpk_get_thermal(rtwdev, kidx, path);
2481 		_dpk_idl_mpa(rtwdev, phy, path, kidx, gain);
2483 		rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
2485 		_dpk_fill_result(rtwdev, phy, path, kidx, gain, txagc);
2493 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx,
2499 static void _dpk_cal_select(struct rtw89_dev *rtwdev, bool force,
2503 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2513 			reloaded[path] = _dpk_reload_check(rtwdev, phy, path,
2518 				_dpk_onoff(rtwdev, path, false);
2525 	_rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
2528 		_dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path);
2529 		_rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
2530 		_dpk_information(rtwdev, phy, path, chanctx_idx);
2531 		if (rtwdev->is_tssi_mode[path])
2532 			_dpk_tssi_pause(rtwdev, path, true);
2535 	_dpk_bb_afe_setting(rtwdev, phy, path, kpath, chanctx_idx);
2538 		is_fail = _dpk_main(rtwdev, phy, path, 1, chanctx_idx);
2539 		_dpk_onoff(rtwdev, path, is_fail);
2542 	_dpk_bb_afe_restore(rtwdev, phy, path, kpath, chanctx_idx);
2543 	_rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
2546 		_dpk_kip_restore(rtwdev, path);
2547 		_dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path);
2548 		_rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
2549 		if (rtwdev->is_tssi_mode[path])
2550 			_dpk_tssi_pause(rtwdev, path, false);
2554 static bool _dpk_bypass_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2557 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
2558 	struct rtw89_fem_info *fem = &rtwdev->fem;
2561 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
2565 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
2569 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
2577 static void _dpk_force_bypass(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
2581 	kpath = _kpath(rtwdev, phy);
2585 			_dpk_onoff(rtwdev, path, true);
2589 static void _dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool force,
2592 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
2594 		    RTW8852B_DPK_VER, rtwdev->hal.cv,
2597 	if (_dpk_bypass_check(rtwdev, phy, chanctx_idx))
2598 		_dpk_force_bypass(rtwdev, phy);
2600 		_dpk_cal_select(rtwdev, force, phy, RF_AB, chanctx_idx);
2603 static void _dpk_track(struct rtw89_dev *rtwdev)
2605 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2617 		rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2621 		cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
2623 		rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2634 		txagc_rf = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2637 		if (rtwdev->is_tssi_mode[path]) {
2638 			trk_idx = rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK);
2640 			rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2645 				rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2648 				rtw89_phy_read32_mask(rtwdev, R_TXAGC_TP + (path << 13),
2651 			rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2656 				rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2659 			rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2662 			tmp = rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8),
2666 				rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2673 			tmp = rtw89_phy_read32_mask(rtwdev,
2691 		tmp = rtw89_phy_read32_mask(rtwdev, R_DPK_TRK, B_DPK_TRK_DIS);
2693 			rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2697 			rtw89_phy_write32_mask(rtwdev,
2700 			rtw89_phy_write32_mask(rtwdev,
2707 static void _set_dpd_backoff(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
2709 	struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2712 	kpath = _kpath(rtwdev, phy);
2714 	ofdm_bkof = rtw89_phy_read32_mask(rtwdev, R_DPD_BF + (phy << 13), B_DPD_BF_OFDM);
2715 	tx_scale = rtw89_phy_read32_mask(rtwdev, R_DPD_BF + (phy << 13), B_DPD_BF_SCA);
2724 			rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8),
2726 			rtw89_debug(rtwdev, RTW89_DBG_RFK,
2734 static void _tssi_rf_setting(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2740 		rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1);
2742 		rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1);
2745 static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2750 	rtw89_rfk_parser(rtwdev, &rtw8852b_tssi_sys_defs_tbl);
2753 		rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
2757 		rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
2762 static void _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev *rtwdev,
2766 	rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2771 static void _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev *rtwdev,
2775 	rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2780 static void _tssi_set_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2783 	rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2788 static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2802 	struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
2845 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2848 		rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0);
2849 		rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1);
2852 			rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, 32);
2853 			rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, 32);
2856 				rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0);
2858 				rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2864 			rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, thermal);
2865 			rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL,
2882 				rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, tmp);
2884 				rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2889 		rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1);
2890 		rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0);
2895 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2898 		rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_DIS, 0x0);
2899 		rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_TRK, 0x1);
2902 			rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, 32);
2903 			rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL, 32);
2906 				rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, 0x0);
2908 				rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2914 			rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, thermal);
2915 			rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL,
2932 				rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, tmp);
2934 				rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2939 		rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x1);
2940 		rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x0);
2945 static void _tssi_set_dac_gain_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2948 	rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2953 static void _tssi_slope_cal_org(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2959 		rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
2963 		rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
2968 static void _tssi_alignment_default(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3023 		rtw89_rfk_parser(rtwdev, tbl);
3026 static void _tssi_set_tssi_slope(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3029 	rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3034 static void _tssi_set_tssi_track(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3038 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSIC, B_P0_TSSIC_BYPASS, 0x0);
3040 		rtw89_phy_write32_mask(rtwdev, R_P1_TSSIC, B_P1_TSSIC_BYPASS, 0x0);
3043 static void _tssi_set_txagc_offset_mv_avg(struct rtw89_dev *rtwdev,
3047 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "======>%s   path=%d\n", __func__,
3051 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_MIX, 0x010);
3053 		rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_RFCTM_DEL, 0x010);
3056 static void _tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
3061 		_tssi_set_tssi_track(rtwdev, phy, i);
3062 		_tssi_set_txagc_offset_mv_avg(rtwdev, phy, i);
3065 			rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG,
3067 			rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG,
3069 			rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG,
3071 			rtw89_write_rf(rtwdev, i, RR_TXGA_V1,
3073 			rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
3076 			rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
3078 			rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
3080 			rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK,
3083 			rtwdev->is_tssi_mode[RF_PATH_A] = true;
3085 			rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG,
3087 			rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG,
3089 			rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG,
3091 			rtw89_write_rf(rtwdev, i, RR_TXGA_V1,
3093 			rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
3096 			rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
3098 			rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
3100 			rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK,
3103 			rtwdev->is_tssi_mode[RF_PATH_B] = true;
3108 static void _tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
3110 	rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_EN, 0x0);
3111 	rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_RFC, 0x1);
3112 	rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_CLR, 0x1);
3113 	rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_EN, 0x0);
3114 	rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_RFC, 0x1);
3115 	rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_CLR, 0x1);
3117 	rtwdev->is_tssi_mode[RF_PATH_A] = false;
3118 	rtwdev->is_tssi_mode[RF_PATH_B] = false;
3121 static u32 _tssi_get_cck_group(struct rtw89_dev *rtwdev, u8 ch)
3147 static u32 _tssi_get_ofdm_group(struct rtw89_dev *rtwdev, u8 ch)
3215 static u32 _tssi_get_trim_group(struct rtw89_dev *rtwdev, u8 ch)
3239 static s8 _tssi_get_ofdm_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3242 	struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3249 	gidx = _tssi_get_ofdm_group(rtwdev, ch);
3251 	rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3261 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3267 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3274 static s8 _tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3277 	struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3284 	tgidx = _tssi_get_trim_group(rtwdev, ch);
3286 	rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3297 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3303 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3311 static void _tssi_set_efuse_to_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3314 	struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3322 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
3326 		gidx = _tssi_get_cck_group(rtwdev, ch);
3327 		trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i, chan);
3330 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3334 		rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_long[i], _TSSI_DE_MASK, val);
3335 		rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_short[i], _TSSI_DE_MASK, val);
3337 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3340 			    rtw89_phy_read32_mask(rtwdev, _tssi_de_cck_long[i],
3343 		ofdm_de = _tssi_get_ofdm_de(rtwdev, phy, i, chan);
3344 		trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i, chan);
3347 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3351 		rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_20m[i], _TSSI_DE_MASK, val);
3352 		rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_40m[i], _TSSI_DE_MASK, val);
3353 		rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m[i], _TSSI_DE_MASK, val);
3354 		rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m_80m[i], _TSSI_DE_MASK, val);
3355 		rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_5m[i], _TSSI_DE_MASK, val);
3356 		rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_10m[i], _TSSI_DE_MASK, val);
3358 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3361 			    rtw89_phy_read32_mask(rtwdev, _tssi_de_mcs_20m[i],
3366 static void _tssi_alimentk_dump_result(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
3368 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3372 		    rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K1 + (path << 13), MASKDWORD),
3374 		    rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K2 + (path << 13), MASKDWORD),
3376 		    rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD),
3378 		    rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD),
3380 		    rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K5 + (path << 13), MASKDWORD),
3382 		    rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD),
3384 		    rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD),
3386 		    rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K8 + (path << 13), MASKDWORD));
3389 static void _tssi_alimentk_done(struct rtw89_dev *rtwdev,
3393 	struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3397 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3412 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
3414 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
3416 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
3418 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
3422 	_tssi_alimentk_dump_result(rtwdev, path);
3425 static void _tssi_hw_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3441 		rtw8852bx_bb_set_plcp_tx(rtwdev);
3442 		rtw8852bx_bb_cfg_tx_path(rtwdev, path);
3443 		rtw8852bx_bb_ctrl_rx_path(rtwdev, rx_path, chan);
3444 		rtw8852bx_bb_set_power(rtwdev, pwr_dbm, phy);
3447 	rtw8852bx_bb_set_pmac_pkt_tx(rtwdev, enable, cnt, period, 20, phy, chan);
3450 static void _tssi_backup_bb_registers(struct rtw89_dev *rtwdev,
3457 		reg_backup[i] = rtw89_phy_read32_mask(rtwdev, reg[i], MASKDWORD);
3459 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
3465 static void _tssi_reload_bb_registers(struct rtw89_dev *rtwdev,
3473 		rtw89_phy_write32_mask(rtwdev, reg[i], MASKDWORD, reg_backup[i]);
3475 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
3481 static u8 _tssi_ch_to_idx(struct rtw89_dev *rtwdev, u8 channel)
3499 static bool _tssi_get_cw_report(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3509 		rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x0);
3510 		rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x1);
3512 		tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
3514 		tmp = rtw89_phy_read32_mask(rtwdev, _tssi_trigger[path], MASKDWORD);
3515 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
3520 			_tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], true, chan);
3522 			_tssi_hw_tx(rtwdev, phy, RF_PATH_ABCD, 100, 5000, power[j], true,
3525 		tx_counter_tmp = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
3528 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
3533 			tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path],
3541 				rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
3544 			rtw89_debug(rtwdev, RTW89_DBG_RFK,
3550 			rtw89_debug(rtwdev, RTW89_DBG_RFK,
3554 			_tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false, chan);
3559 			rtw89_phy_read32_mask(rtwdev, _tssi_cw_rpt_addr[path], B_TSSI_CWRPT);
3561 		_tssi_hw_tx(rtwdev, phy, path, 100, 5000, power[j], false, chan);
3563 		tx_counter_tmp = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD);
3566 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
3574 static void _tssi_alimentk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3581 	struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3585 	u8 ch_idx = _tssi_ch_to_idx(rtwdev, channel);
3596 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3601 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
3603 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
3605 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
3607 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
3610 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
3612 		_tssi_alimentk_dump_result(rtwdev, path);
3634 	rtw8852bx_bb_backup_tssi(rtwdev, phy, &tssi_bak);
3635 	_tssi_backup_bb_registers(rtwdev, phy, bb_reg, bb_reg_backup, ARRAY_SIZE(bb_reg_backup));
3637 	rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x8);
3638 	rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x8);
3639 	rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x2);
3640 	rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x2);
3642 	ok = _tssi_get_cw_report(rtwdev, phy, path, power, tssi_cw_rpt, chan);
3647 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
3652 	tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][1],
3659 	tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][2],
3664 	tmp = rtw89_phy_read32_mask(rtwdev, _tssi_cw_default_addr[path][3],
3674 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM1, tmp);
3675 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2, B_P0_TSSI_ALIM2, tmp);
3677 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
3679 			    rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3, B_P0_TSSI_ALIM31),
3680 			    rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM11),
3681 			    rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM12),
3682 			    rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1, B_P0_TSSI_ALIM13));
3688 		rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM1, tmp);
3689 		rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_ALIM2, B_P1_TSSI_ALIM2, tmp);
3691 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
3693 			    rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM3, B_P1_TSSI_ALIM31),
3694 			    rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM11),
3695 			    rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM12),
3696 			    rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_ALIM1, B_P1_TSSI_ALIM13));
3701 		rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD);
3703 		rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD);
3705 		rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD);
3707 		rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD);
3711 		rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD);
3713 		rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD);
3715 		rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD);
3717 		rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD);
3719 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3723 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3727 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3731 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3737 	_tssi_reload_bb_registers(rtwdev, phy, bb_reg, bb_reg_backup, ARRAY_SIZE(bb_reg_backup));
3738 	rtw8852bx_bb_restore_tssi(rtwdev, phy, &tssi_bak);
3739 	rtw8852bx_bb_tx_mode_switch(rtwdev, phy, 0);
3744 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3749 void rtw8852b_dpk_init(struct rtw89_dev *rtwdev)
3751 	_set_dpd_backoff(rtwdev, RTW89_PHY_0);
3754 void rtw8852b_rck(struct rtw89_dev *rtwdev)
3759 		_rck(rtwdev, path);
3762 void rtw8852b_dack(struct rtw89_dev *rtwdev, enum rtw89_chanctx_idx chanctx_idx)
3764 	u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0, chanctx_idx);
3766 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_START);
3767 	_dac_cal(rtwdev, false);
3768 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_STOP);
3771 void rtw8852b_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
3774 	u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3777 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_START);
3778 	rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
3779 	_wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
3781 	_iqk_init(rtwdev);
3782 	_iqk(rtwdev, phy_idx, false, chanctx_idx);
3784 	rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
3785 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_STOP);
3788 void rtw8852b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
3791 	u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3794 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_START);
3795 	rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
3796 	_wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
3798 	_rx_dck(rtwdev, phy_idx);
3800 	rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
3801 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_STOP);
3804 void rtw8852b_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
3807 	u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3810 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START);
3811 	rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
3812 	_wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
3814 	rtwdev->dpk.is_dpk_enable = true;
3815 	rtwdev->dpk.is_dpk_reload_en = false;
3816 	_dpk(rtwdev, phy_idx, false, chanctx_idx);
3818 	rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
3819 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP);
3822 void rtw8852b_dpk_track(struct rtw89_dev *rtwdev)
3824 	_dpk_track(rtwdev);
3827 void rtw8852b_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3830 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
3831 	u8 phy_map = rtw89_btc_phymap(rtwdev, phy, RF_AB, chanctx_idx);
3835 	rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n", __func__, phy);
3836 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
3838 	_tssi_disable(rtwdev, phy);
3841 		_tssi_rf_setting(rtwdev, phy, i, chan);
3842 		_tssi_set_sys(rtwdev, phy, i, chan);
3843 		_tssi_ini_txpwr_ctrl_bb(rtwdev, phy, i);
3844 		_tssi_ini_txpwr_ctrl_bb_he_tb(rtwdev, phy, i);
3845 		_tssi_set_dck(rtwdev, phy, i);
3846 		_tssi_set_tmeter_tbl(rtwdev, phy, i, chan);
3847 		_tssi_set_dac_gain_tbl(rtwdev, phy, i);
3848 		_tssi_slope_cal_org(rtwdev, phy, i, chan);
3849 		_tssi_alignment_default(rtwdev, phy, i, true, chan);
3850 		_tssi_set_tssi_slope(rtwdev, phy, i);
3852 		rtw89_chip_stop_sch_tx(rtwdev, phy, &tx_en, RTW89_SCH_TX_SEL_ALL);
3853 		_tmac_tx_pause(rtwdev, phy, true);
3855 			_tssi_alimentk(rtwdev, phy, i, chan);
3856 		_tmac_tx_pause(rtwdev, phy, false);
3857 		rtw89_chip_resume_sch_tx(rtwdev, phy, tx_en);
3860 	_tssi_enable(rtwdev, phy);
3861 	_tssi_set_efuse_to_de(rtwdev, phy, chan);
3863 	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
3866 void rtw8852b_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3869 	struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3874 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3888 	_tssi_disable(rtwdev, phy);
3891 		_tssi_rf_setting(rtwdev, phy, i, chan);
3892 		_tssi_set_sys(rtwdev, phy, i, chan);
3893 		_tssi_set_tmeter_tbl(rtwdev, phy, i, chan);
3896 			_tssi_alimentk_done(rtwdev, phy, i, chan);
3898 			_tssi_alignment_default(rtwdev, phy, i, true, chan);
3901 	_tssi_enable(rtwdev, phy);
3902 	_tssi_set_efuse_to_de(rtwdev, phy, chan);
3905 static void rtw8852b_tssi_default_txagc(struct rtw89_dev *rtwdev,
3909 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
3912 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "======> %s   ch=%d\n",
3916 		if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B])
3917 			rtw8852b_tssi(rtwdev, phy, true, chanctx_idx);
3921 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3924 		    rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT),
3925 		    rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT));
3927 	rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT, 0xc0);
3928 	rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT,  0xc0);
3929 	rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
3930 	rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1);
3931 	rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x0);
3932 	rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x1);
3934 	_tssi_alimentk_done(rtwdev, phy, RF_PATH_A, chan);
3935 	_tssi_alimentk_done(rtwdev, phy, RF_PATH_B, chan);
3937 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3940 		    rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT),
3941 		    rtw89_phy_read32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT));
3943 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
3947 void rtw8852b_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
3952 		rtw8852b_tssi_default_txagc(rtwdev, phy_idx, true, chanctx_idx);
3954 		rtw8852b_tssi_default_txagc(rtwdev, phy_idx, false, chanctx_idx);
3957 static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
3963 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
3965 	rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
3967 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
3986 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]Fail to set CH\n");
3992 	rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
3994 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n",
3996 		    rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
3999 static void _ctrl_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
4002 	_bw_setting(rtwdev, RF_PATH_A, bw, true);
4003 	_bw_setting(rtwdev, RF_PATH_B, bw, true);
4004 	_bw_setting(rtwdev, RF_PATH_A, bw, false);
4005 	_bw_setting(rtwdev, RF_PATH_B, bw, false);
4008 static bool _set_s0_arfc18(struct rtw89_dev *rtwdev, u32 val)
4014 	bak = rtw89_read_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK);
4015 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RR_LDO_SEL, 0x1);
4016 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK, val);
4019 				       false, rtwdev, RF_PATH_A, RR_LPF, RR_LPF_BUSY);
4021 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]LCK timeout\n");
4023 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK, bak);
4028 static void _lck_check(struct rtw89_dev *rtwdev)
4032 	if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
4033 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN MMD reset\n");
4035 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x1);
4036 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x0);
4037 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x1);
4038 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x0);
4043 	if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
4044 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]re-set RF 0x18\n");
4046 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
4047 		tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
4048 		_set_s0_arfc18(rtwdev, tmp);
4049 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
4052 	if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
4053 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN off/on\n");
4055 		tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK);
4056 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK, tmp);
4057 		tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK);
4058 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK, tmp);
4060 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x1);
4061 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0);
4062 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3);
4063 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x0);
4065 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
4066 		tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
4067 		_set_s0_arfc18(rtwdev, tmp);
4068 		rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
4070 		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]0xb2=%x, 0xc5=%x\n",
4071 			    rtw89_read_rf(rtwdev, RF_PATH_A, RR_VCO, RFREG_MASK),
4072 			    rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RFREG_MASK));
4076 static void _set_ch(struct rtw89_dev *rtwdev, u32 val)
4080 	timeout = _set_s0_arfc18(rtwdev, val);
4082 		_lck_check(rtwdev);
4085 static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
4092 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
4094 	rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
4108 		_set_ch(rtwdev, rf_reg18);
4110 		rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
4112 	rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0);
4113 	rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1);
4115 	rtw89_debug(rtwdev, RTW89_DBG_RFK,
4118 		    rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
4121 static void _ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch)
4123 	_ch_setting(rtwdev, RF_PATH_A, central_ch, true);
4124 	_ch_setting(rtwdev, RF_PATH_B, central_ch, true);
4125 	_ch_setting(rtwdev, RF_PATH_A, central_ch, false);
4126 	_ch_setting(rtwdev, RF_PATH_B, central_ch, false);
4129 static void _set_rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_bandwidth bw,
4132 	rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
4133 	rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12);
4136 		rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b);
4138 		rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13);
4140 		rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb);
4142 		rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3);
4144 	rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path,
4145 		    rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB));
4147 	rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
4150 static void _rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
4155 	kpath = _kpath(rtwdev, phy);
4161 		_set_rxbb_bw(rtwdev, bw, path);
4165 static void rtw8852b_ctrl_bw_ch(struct rtw89_dev *rtwdev,
4169 	_ctrl_ch(rtwdev, central_ch);
4170 	_ctrl_bw(rtwdev, phy, bw);
4171 	_rxbb_bw(rtwdev, phy, bw);
4174 void rtw8852b_set_channel_rf(struct rtw89_dev *rtwdev,
4178 	rtw8852b_ctrl_bw_ch(rtwdev, phy_idx, chan->channel, chan->band_type,