Lines Matching refs:rtwdev
246 static void rtw8852b_pwr_sps_ana(struct rtw89_dev *rtwdev)
248 struct rtw89_efuse *efuse = &rtwdev->efuse;
251 rtw89_write16(rtwdev, R_AX_SPS_ANA_ON_CTRL2, RTL8852B_RFE_05_SPS_ANA);
254 static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev)
259 rtw8852b_pwr_sps_ana(rtwdev);
261 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
263 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
264 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
265 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
266 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
269 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
273 rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN);
275 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL);
279 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1);
280 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3);
281 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
282 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
285 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
289 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
290 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
291 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
292 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
294 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
295 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
297 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
299 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
304 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
306 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
310 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
314 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
318 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
321 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
325 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
329 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
332 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
335 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
338 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
342 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
343 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
344 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
348 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
349 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
351 if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid)
354 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9);
355 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA);
357 if (rtwdev->hal.cv == CHIP_CBV) {
358 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
359 rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA);
360 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
364 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
371 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
377 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
383 static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev)
388 rtw8852b_pwr_sps_ana(rtwdev);
390 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
394 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
397 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
400 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
403 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
406 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
410 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
413 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
417 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
418 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
419 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
420 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
422 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
426 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
428 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
432 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
435 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
439 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
440 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
441 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3);
442 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
447 static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
451 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
453 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
455 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
457 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
458 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
460 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
461 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
462 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
464 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
467 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
471 static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev,
474 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
475 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
476 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
477 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
478 rtw8852bx_bb_reset_all(rtwdev, phy_idx);
479 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
480 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
481 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
482 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
485 static void rtw8852b_set_channel(struct rtw89_dev *rtwdev,
490 rtw8852bx_set_channel_mac(rtwdev, chan, mac_idx);
491 rtw8852bx_set_channel_bb(rtwdev, chan, phy_idx);
492 rtw8852b_set_channel_rf(rtwdev, chan, phy_idx);
495 static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
502 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0);
503 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0);
505 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1);
506 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1);
510 static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
513 if (!rtwdev->dbcc_en) {
514 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
515 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
518 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
520 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
524 static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en)
527 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
529 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
532 static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
539 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
540 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
541 rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
542 rtw8852b_adc_en(rtwdev, false);
544 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
546 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
547 rtw8852b_adc_en(rtwdev, true);
548 rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
549 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
550 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
554 static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev)
556 rtwdev->is_tssi_mode[RF_PATH_A] = false;
557 rtwdev->is_tssi_mode[RF_PATH_B] = false;
559 rtw8852b_dpk_init(rtwdev);
560 rtw8852b_rck(rtwdev);
561 rtw8852b_dack(rtwdev, RTW89_CHANCTX_0);
562 rtw8852b_rx_dck(rtwdev, RTW89_PHY_0, RTW89_CHANCTX_0);
565 static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev,
571 rtw8852b_rx_dck(rtwdev, phy_idx, chanctx_idx);
572 rtw8852b_iqk(rtwdev, phy_idx, chanctx_idx);
573 rtw8852b_tssi(rtwdev, phy_idx, true, chanctx_idx);
574 rtw8852b_dpk(rtwdev, phy_idx, chanctx_idx);
577 static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev,
581 rtw8852b_tssi_scan(rtwdev, phy_idx, chan);
584 static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev,
588 rtw8852b_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx,
592 static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev)
594 rtw8852b_dpk_track(rtwdev);
597 static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev)
599 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
600 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
603 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
604 md->md_v7.kt_ver = rtwdev->hal.cv;
623 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
624 rtwdev->btc.ant_type = md->md_v7.ant.type;
626 md->md.rfe_type = rtwdev->efuse.rfe_type;
627 md->md.cv = rtwdev->hal.cv;
646 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
647 rtwdev->btc.ant_type = md->md.ant.type;
673 rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
686 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \