Lines Matching full:path

94 	u8 path;
98 for (path = 0; path < RF_PATH_MAX; path++) {
99 if (!(kpath & BIT(path)))
103 2, 5000, false, rtwdev, path, 0x00,
107 path, ret);
254 enum rtw89_rf_path path, u8 index)
266 if (path == RF_PATH_A)
275 tmp |= dack->msbk_d[path][index][i + 12] << (i * 8);
283 tmp |= dack->msbk_d[path][index][i + 8] << (i * 8);
291 tmp |= dack->msbk_d[path][index][i + 4] << (i * 8);
299 tmp |= dack->msbk_d[path][index][i] << (i * 8);
306 tmp = (dack->biask_d[path][index] << 22) |
307 (dack->dadck_d[path][index] << 14);
312 static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
317 _dack_reload_by_path(rtwdev, path, i);
319 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
325 static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
331 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
345 "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im);
395 static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
397 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
401 _check_addc(rtwdev, path);
403 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
552 static void _iqk_read_fft_dbcc0(struct rtw89_dev *rtwdev, u8 path)
572 path, i, fft[i]);
575 static void _iqk_read_xym_dbcc0(struct rtw89_dev *rtwdev, u8 path)
581 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path);
587 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
589 path, BIT(path), tmp);
593 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000);
598 static void _iqk_read_txcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path,
609 if (path >= RTW8852A_IQK_SS) {
610 rtw89_warn(rtwdev, "cfir path %d out of range\n", path);
619 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001);
621 base_addr = base_addrs[path][group];
630 if (path == 0x0) {
651 rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD);
652 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xc);
654 tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD);
655 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path,
656 BIT(path), tmp);
659 static void _iqk_read_rxcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path,
670 if (path >= RTW8852A_IQK_SS) {
671 rtw89_warn(rtwdev, "cfir path %d out of range\n", path);
680 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001);
682 base_addr = base_addrs[path][group];
690 if (path == 0x0) {
711 rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD);
712 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xd);
713 tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD);
714 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path,
715 BIT(path), tmp);
718 static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path)
744 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
749 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
762 switch (iqk_info->iqk_band[path]) {
764 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2);
765 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1);
768 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2);
769 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x5);
770 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1);
775 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
776 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp);
777 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
778 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
779 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1);
783 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype)
794 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret);
797 "[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp);
803 enum rtw89_phy_idx phy_idx, u8 path, u8 ktype,
809 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy_idx, path, chanctx_idx);
812 if (path == RF_PATH_A)
820 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1);
825 iqk_cmd = 0x108 | (1 << (4 + path));
830 iqk_cmd = 0x208 | (1 << (4 + path));
835 iqk_cmd = 0x008 | (1 << (path + 4)) |
836 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
839 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
844 iqk_cmd = 0x008 | (1 << (path + 4)) |
845 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8);
850 iqk_cmd = 0x308 | (1 << (4 + path));
855 iqk_cmd = 0x608 | (1 << (4 + path));
864 fail = _iqk_check_cal(rtwdev, path, ktype);
866 _iqk_read_xym_dbcc0(rtwdev, path);
868 _iqk_read_fft_dbcc0(rtwdev, path);
870 _iqk_sram(rtwdev, path);
873 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x0);
874 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x1);
875 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x2);
876 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x3);
878 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x0);
879 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x1);
880 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x2);
881 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x3);
893 enum rtw89_phy_idx phy_idx, u8 path,
908 switch (iqk_info->iqk_band[path]) {
910 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_g[gp]);
911 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, attc2_g[gp]);
912 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, attc1_g[gp]);
915 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_a[gp]);
916 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, attc2_a[gp]);
917 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, attc1_a[gp]);
923 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
927 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR);
928 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
929 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
930 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp);
933 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK, chanctx_idx);
934 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail);
937 switch (iqk_info->iqk_band[path]) {
939 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0);
940 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
943 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
944 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
945 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0);
950 iqk_info->nb_rxcfir[path] = 0x40000000;
951 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
953 iqk_info->is_wb_rxiqk[path] = true;
958 enum rtw89_phy_idx phy_idx, u8 path,
972 switch (iqk_info->iqk_band[path]) {
974 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_g);
975 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, idxattc2_g);
976 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, idxattc1_g);
979 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_a);
980 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, idxattc2_a);
981 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, idxattc1_a);
987 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
991 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR);
992 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
993 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
994 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
998 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK, chanctx_idx);
1000 switch (iqk_info->iqk_band[path]) {
1002 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0);
1003 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
1006 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
1007 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
1008 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0);
1014 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD);
1015 iqk_info->nb_rxcfir[path] = tmp | 0x2;
1017 iqk_info->nb_rxcfir[path] = 0x40000002;
1022 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
1026 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) {
1028 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8),
1030 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13),
1032 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON);
1036 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8),
1038 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13),
1040 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON);
1047 enum rtw89_phy_idx phy_idx, u8 path,
1061 switch (iqk_info->iqk_band[path]) {
1063 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8),
1065 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL,
1067 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1,
1069 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0,
1071 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1075 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8),
1077 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL,
1079 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1085 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR);
1086 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
1087 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
1088 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1091 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK, chanctx_idx);
1092 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(8 + gp + path * 4), fail);
1095 iqk_info->nb_txcfir[path] = 0x40000000;
1096 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8),
1098 iqk_info->is_wb_txiqk[path] = true;
1099 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1100 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path,
1101 BIT(path), tmp);
1106 enum rtw89_phy_idx phy_idx, u8 path,
1118 switch (iqk_info->iqk_band[path]) {
1120 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8),
1122 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, g_mode_txgain);
1123 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, attsmxr);
1124 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, attsmxr);
1127 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8),
1129 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, a_mode_txgain);
1134 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR);
1135 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
1136 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3);
1137 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, group);
1138 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt);
1140 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK, chanctx_idx);
1142 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1143 iqk_info->nb_txcfir[path] = tmp | 0x2;
1145 iqk_info->nb_txcfir[path] = 0x40000002;
1147 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1148 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path,
1149 BIT(path), tmp);
1153 static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias)
1157 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias);
1158 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2);
1159 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1160 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0);
1162 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1);
1163 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias);
1164 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
1167 static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path)
1174 tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK);
1176 path, tmp);
1179 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, i = 0x%x\n", path, core_i);
1180 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, q = 0x%x\n", path, core_q);
1188 enum rtw89_phy_idx phy_idx, u8 path,
1197 switch (iqk_info->iqk_band[path]) {
1199 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe5e0);
1203 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe4e0);
1210 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
1213 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR);
1214 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
1215 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, 0x1);
1216 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, 0x0);
1219 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt);
1220 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE, chanctx_idx);
1221 iqk_info->lok_cor_fail[0][path] = tmp;
1223 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt);
1224 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE, chanctx_idx);
1225 iqk_info->lok_fin_fail[0][path] = tmp;
1226 fail = _lok_finetune_check(rtwdev, path);
1230 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
1234 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
1244 switch (iqk_info->iqk_band[path]) {
1246 rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW, 0x00);
1247 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f);
1248 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0);
1249 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x1);
1250 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1);
1251 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0);
1252 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1253 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0);
1254 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x000);
1255 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200);
1256 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200);
1257 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
1262 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00);
1263 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f);
1264 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x7);
1265 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0);
1266 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1267 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0);
1268 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x100);
1269 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200);
1270 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200);
1271 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x1);
1272 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x0);
1273 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
1282 static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path)
1284 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08);
1288 u8 path)
1294 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %lu\n", path,
1295 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]));
1296 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_COR_fail= %d\n", path,
1297 iqk_info->lok_cor_fail[0][path]);
1298 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_FIN_fail= %d\n", path,
1299 iqk_info->lok_fin_fail[0][path]);
1300 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_TXIQK_fail = %d\n", path,
1301 iqk_info->iqk_tx_fail[0][path]);
1302 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_RXIQK_fail= %d,\n", path,
1303 iqk_info->iqk_rx_fail[0][path]);
1304 flag = iqk_info->lok_cor_fail[0][path];
1305 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(0) << (path * 4), flag);
1306 flag = iqk_info->lok_fin_fail[0][path];
1307 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(1) << (path * 4), flag);
1308 flag = iqk_info->iqk_tx_fail[0][path];
1309 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(2) << (path * 4), flag);
1310 flag = iqk_info->iqk_rx_fail[0][path];
1311 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(3) << (path * 4), flag);
1313 tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD);
1314 iqk_info->bp_iqkenable[path] = tmp;
1315 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD);
1316 iqk_info->bp_txkresult[path] = tmp;
1317 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD);
1318 iqk_info->bp_rxkresult[path] = tmp;
1323 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, 0x0000000f << (path * 4));
1326 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x00ff0000 << (path * 4),
1331 void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path,
1339 _iqk_txclk_setting(rtwdev, path);
1342 _lok_res_table(rtwdev, path, ibias++);
1343 _iqk_txk_setting(rtwdev, path);
1344 lok_is_fail = _iqk_lok(rtwdev, phy_idx, path, chanctx_idx);
1349 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path,
1352 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path,
1355 _iqk_rxclk_setting(rtwdev, path);
1356 _iqk_rxk_setting(rtwdev, path);
1357 if (iqk_info->is_nbiqk || rtwdev->dbcc_en || iqk_info->iqk_band[path] == RTW89_BAND_2G)
1358 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path,
1361 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path,
1364 _iqk_info_iqk(rtwdev, phy_idx, path);
1368 enum rtw89_phy_idx phy, u8 path,
1379 if (iqk_info->iqk_mcc_ch[idx][path] == 0) {
1385 idx = iqk_info->iqk_table_idx[path] + 1;
1389 reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
1393 iqk_info->iqk_band[path] = chan->band_type;
1394 iqk_info->iqk_bw[path] = chan->band_width;
1395 iqk_info->iqk_ch[path] = chan->channel;
1398 "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path,
1399 iqk_info->iqk_band[path]);
1401 path, iqk_info->iqk_bw[path]);
1403 path, iqk_info->iqk_ch[path]);
1405 "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", path, phy,
1407 iqk_info->iqk_band[path] == 0 ? "2G" :
1408 iqk_info->iqk_band[path] == 1 ? "5G" : "6G",
1409 iqk_info->iqk_ch[path],
1410 iqk_info->iqk_bw[path] == 0 ? "20M" :
1411 iqk_info->iqk_bw[path] == 1 ? "40M" : "80M");
1418 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x000f << (path * 16),
1419 (u8)iqk_info->iqk_band[path]);
1420 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x00f0 << (path * 16),
1421 (u8)iqk_info->iqk_bw[path]);
1422 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0xff00 << (path * 16),
1423 (u8)iqk_info->iqk_ch[path]);
1429 u8 path, enum rtw89_chanctx_idx chanctx_idx)
1431 _iqk_by_path(rtwdev, phy_idx, path, chanctx_idx);
1434 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
1438 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD,
1439 iqk_info->nb_txcfir[path]);
1440 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
1441 iqk_info->nb_rxcfir[path]);
1447 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000);
1448 rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN);
1449 rtw89_phy_write32_mask(rtwdev, R_CFIR_MAP + (path << 8), MASKDWORD, 0xe4e4e4e4);
1450 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL);
1451 rtw89_phy_write32_clr(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW);
1452 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD, 0x00000002);
1453 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1454 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x0);
1455 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1456 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
1457 rtw89_write_rf(rtwdev, path, RR_TXRSV, RR_TXRSV_GAPK, 0x0);
1458 rtw89_write_rf(rtwdev, path, RR_BIAS, RR_BIAS_GAPK, 0x0);
1459 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1463 enum rtw89_phy_idx phy_idx, u8 path)
1482 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
1485 u8 idx = iqk_info->iqk_table_idx[path];
1488 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
1489 B_COEF_SEL_IQC, path & 0x1);
1490 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1491 B_CFIR_LUT_G2, path & 0x1);
1493 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
1495 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8),
1498 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1504 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD);
1508 enum rtw89_phy_idx phy_idx, u8 path)
1529 static void _iqk_dbcc(struct rtw89_dev *rtwdev, u8 path,
1537 if (path == 0x0)
1542 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx);
1543 _iqk_macbb_setting(rtwdev, phy_idx, path);
1544 _iqk_preset(rtwdev, path);
1545 _iqk_start_iqk(rtwdev, phy_idx, path, chanctx_idx);
1546 _iqk_restore(rtwdev, path);
1547 _iqk_afebb_restore(rtwdev, phy_idx, path);
1550 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
1556 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
1558 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
1560 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1561 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
1564 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
1567 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
1570 false, rtwdev, path, 0x1c, BIT(3));
1574 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
1575 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
1578 rtw89_write_rf(rtwdev, path, RR_RCKO, RR_RCKO_OFF, 0x4);
1580 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x1);
1581 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x0);
1583 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
1587 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK),
1588 rtw89_read_rf(rtwdev, path, RR_RCKS, RFREG_MASK),
1589 rtw89_read_rf(rtwdev, path, RR_RCKO, RFREG_MASK));
1595 u8 ch, path;
1612 for (path = 0; path < RTW8852A_IQK_SS; path++) {
1613 iqk_info->lok_cor_fail[ch][path] = false;
1614 iqk_info->lok_fin_fail[ch][path] = false;
1615 iqk_info->iqk_tx_fail[ch][path] = false;
1616 iqk_info->iqk_rx_fail[ch][path] = false;
1617 iqk_info->iqk_mcc_ch[ch][path] = 0x0;
1618 iqk_info->iqk_table_idx[path] = 0x0;
1624 enum rtw89_phy_idx phy_idx, u8 path,
1640 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx);
1642 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1643 _iqk_macbb_setting(rtwdev, phy_idx, path);
1644 _iqk_preset(rtwdev, path);
1645 _iqk_start_iqk(rtwdev, phy_idx, path, chanctx_idx);
1646 _iqk_restore(rtwdev, path);
1647 _iqk_afebb_restore(rtwdev, phy_idx, path);
1649 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1675 enum rtw89_rf_path path, bool is_afe,
1678 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path, chanctx_idx);
1683 path, is_afe ? "AFE" : "RFC");
1685 ori_val = rtw89_phy_read32_mask(rtwdev, R_P0_RXCK + (path << 13), MASKDWORD);
1688 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
1689 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON);
1690 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13),
1692 rtw89_phy_write32_set(rtwdev, R_S0_RXDC2 + (path << 13), B_S0_RXDC2_MEN);
1693 rtw89_phy_write32_mask(rtwdev, R_S0_RXDC2 + (path << 13),
1702 rtw89_write_rf(rtwdev, path, RR_DCK2, RR_DCK2_CYCLE, 0x3f);
1703 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_SEL, is_afe);
1707 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
1708 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
1714 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
1717 rtw89_phy_write32_clr(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG);
1718 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13),
1726 u8 path, kpath, dck_tune;
1736 for (path = 0; path < 2; path++) {
1737 if (!(kpath & BIT(path)))
1740 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
1741 dck_tune = (u8)rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE);
1743 if (rtwdev->is_tssi_mode[path]) {
1744 addr = 0x5818 + (path << 13);
1749 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1750 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0);
1751 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
1752 _set_rx_dck(rtwdev, phy, path, is_afe, chanctx_idx);
1753 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune);
1754 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
1756 if (rtwdev->is_tssi_mode[path]) {
1757 addr = 0x5818 + (path << 13);
1780 enum rtw89_rf_path path, bool is_bybb)
1783 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1785 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1789 enum rtw89_rf_path path, bool off);
1793 u8 path)
1798 reg_bkup[path][i] = rtw89_phy_read32_mask(rtwdev,
1799 reg[i] + (path << 8),
1802 reg[i] + (path << 8), reg_bkup[path][i]);
1807 u32 reg_bkup[][RTW8852A_DPK_KIP_REG_NUM], u8 path)
1812 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8),
1813 MASKDWORD, reg_bkup[path][i]);
1815 reg[i] + (path << 8), reg_bkup[path][i]);
1820 enum rtw89_rf_path path, enum rtw8852a_dpk_id id,
1823 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path, chanctx_idx);
1828 dpk_cmd = (u16)((id << 8) | (0x19 + (path << 4)));
1862 enum rtw89_rf_path path,
1865 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3);
1866 _set_rx_dck(rtwdev, phy, path, false, chanctx_idx);
1871 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx)
1875 u8 kidx = dpk->cur_idx[path];
1877 dpk->bp[path][kidx].band = chan->band_type;
1878 dpk->bp[path][kidx].ch = chan->channel;
1879 dpk->bp[path][kidx].bw = chan->band_width;
1883 path, dpk->cur_idx[path], phy,
1884 rtwdev->is_tssi_mode[path] ? "on" : "off",
1886 dpk->bp[path][kidx].band == 0 ? "2G" :
1887 dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1888 dpk->bp[path][kidx].ch,
1889 dpk->bp[path][kidx].bw == 0 ? "20M" :
1890 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
1895 enum rtw89_rf_path path, u8 kpath)
1926 enum rtw89_rf_path path, u8 kpath)
1946 enum rtw89_rf_path path, bool is_pause)
1948 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
1951 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
1956 enum rtw89_rf_path path, u8 kidx)
1961 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08);
1963 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path); /*subpage_id*/
1964 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8) + (kidx << 2),
1966 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
1970 path, kidx);
1974 enum rtw89_rf_path path)
1978 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000);
1982 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), BIT(15), 0x1);
1984 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
1989 enum rtw89_rf_path path,
1994 cur_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB);
1998 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
1999 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1);
2000 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x2);
2001 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK,
2002 rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK));
2003 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
2004 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
2005 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1);
2009 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTL, 0x1f);
2012 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x3);
2014 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x1);
2016 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x0);
2020 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK, chanctx_idx);
2022 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
2025 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0);
2026 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x0);
2027 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); /*POW IQKPLL*/
2028 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_DPK);
2034 enum rtw89_rf_path path)
2038 dpk->bp[path][kidx].ther_dpk =
2039 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
2042 dpk->bp[path][kidx].ther_dpk);
2046 enum rtw89_rf_path path)
2050 rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc_ori);
2056 enum rtw89_rf_path path, u8 kidx)
2060 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
2061 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x280b);
2062 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x0);
2063 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x4);
2064 rtw89_write_rf(rtwdev, path, RR_MIXER, RR_MIXER_GN, 0x0);
2066 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x282e);
2067 rtw89_write_rf(rtwdev, path, RR_BIASA2, RR_BIASA2_LB, 0x7);
2068 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW, 0x3);
2069 rtw89_write_rf(rtwdev, path, RR_RXA, RR_RXA_DPK, 0x3);
2071 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1);
2072 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
2073 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0);
2077 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK),
2078 rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK),
2079 rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK));
2083 enum rtw89_rf_path path, bool is_manual)
2088 rtw89_phy_write32_mask(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN, 0x1);
2089 tmp_pad = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_PAD);
2090 rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8),
2093 tmp_txbb = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_BB);
2094 rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8),
2097 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8),
2099 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8),
2102 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), BIT(1), 0x1);
2108 rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN);
2115 enum rtw89_rf_path path, bool is_bypass)
2118 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
2120 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
2123 "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path,
2124 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
2127 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2);
2128 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS);
2130 "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path,
2131 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8),
2137 void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2141 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80)
2143 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40)
2149 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
2150 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
2154 enum rtw89_rf_path path, u8 kidx, u8 gain)
2159 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val);
2166 enum rtw89_rf_path path)
2181 "[DPK] S%d Corr_idx / Corr_val = %d / %d\n", path, corr_idx,
2184 dpk->corr_idx[path][0] = corr_idx;
2185 dpk->corr_val[path][0] = corr_val;
2196 path, dc_i, dc_q);
2198 dpk->dc_i[path][0] = dc_i;
2199 dpk->dc_q[path][0] = dc_q;
2209 enum rtw89_rf_path path, u8 kidx,
2212 _dpk_tpg_sel(rtwdev, path, kidx);
2213 _dpk_one_shot(rtwdev, phy, path, SYNC, chanctx_idx);
2214 return _dpk_sync_check(rtwdev, path); /*1= fail*/
2265 enum rtw89_phy_idx phy, enum rtw89_rf_path path,
2268 _dpk_table_select(rtwdev, path, kidx, 1);
2269 _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS, chanctx_idx);
2277 enum rtw89_rf_path path, s8 gain_offset)
2281 txagc = (u8)rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK);
2290 rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc);
2345 enum rtw89_rf_path path, u8 kidx, u8 init_txagc,
2368 if (_dpk_sync(rtwdev, phy, path, kidx, chanctx_idx)) {
2383 tmp_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB);
2396 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, tmp_rxbb);
2402 _dpk_bypass_rxcfir(rtwdev, path, true);
2404 _dpk_lbk_rxiqk(rtwdev, phy, path,
2416 _dpk_gainloss(rtwdev, phy, path, kidx, chanctx_idx);
2434 tmp_txagc = _dpk_set_offset(rtwdev, path, 3);
2446 tmp_txagc = _dpk_set_offset(rtwdev, path, -2);
2453 tmp_txagc = _dpk_set_offset(rtwdev, path, tmp_gl_idx);
2500 enum rtw89_rf_path path, u8 kidx, u8 gain,
2504 _dpk_table_select(rtwdev, path, kidx, 1);
2505 _dpk_one_shot(rtwdev, phy, path, MDPK_IDL, chanctx_idx);
2509 enum rtw89_rf_path path, u8 kidx, u8 gain,
2517 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_MDPD, kidx);
2523 dpk->bp[path][kidx].txagc_dpk = txagc;
2524 rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8),
2527 dpk->bp[path][kidx].pwsf = pwsf;
2528 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
2531 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
2532 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD);
2534 dpk->bp[path][kidx].gs = gs;
2535 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2538 rtw89_phy_write32_clr(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD);
2544 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx)
2555 if (cur_band != dpk->bp[path][idx].band ||
2556 cur_ch != dpk->bp[path][idx].ch)
2559 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8),
2561 dpk->cur_idx[path] = idx;
2564 "[DPK] reload S%d[%d] success\n", path, idx);
2571 enum rtw89_rf_path path, u8 gain,
2575 u8 txagc = 0, kidx = dpk->cur_idx[path];
2579 "[DPK] ========= S%d[%d] DPK Start =========\n", path,
2582 _rf_direct_cntrl(rtwdev, path, false);
2583 txagc = _dpk_set_tx_pwr(rtwdev, gain, path);
2584 _dpk_rf_setting(rtwdev, gain, path, kidx);
2585 _dpk_rx_dck(rtwdev, phy, path, chanctx_idx);
2587 _dpk_kip_setting(rtwdev, path, kidx);
2588 _dpk_manual_txcfir(rtwdev, path, true);
2589 txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false, chanctx_idx);
2592 _dpk_get_thermal(rtwdev, kidx, path);
2594 _dpk_idl_mpa(rtwdev, phy, path, kidx, gain, chanctx_idx);
2595 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
2596 _dpk_fill_result(rtwdev, path, kidx, gain, txagc);
2597 _dpk_manual_txcfir(rtwdev, path, false);
2600 dpk->bp[path][kidx].path_ok = true;
2602 dpk->bp[path][kidx].path_ok = false;
2604 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx,
2619 u8 path;
2623 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2624 if (!(kpath & BIT(path)))
2627 reloaded[path] = _dpk_reload_check(rtwdev, phy, path,
2629 if (!reloaded[path] && dpk->bp[path][0].ch != 0)
2630 dpk->cur_idx[path] = !dpk->cur_idx[path];
2632 _dpk_onoff(rtwdev, path, false);
2635 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++)
2636 dpk->cur_idx[path] = 0;
2646 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2647 if (!(kpath & BIT(path)) || reloaded[path])
2649 if (rtwdev->is_tssi_mode[path])
2650 _dpk_tssi_pause(rtwdev, path, true);
2651 _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path);
2652 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
2653 _dpk_information(rtwdev, phy, path, chanctx_idx);
2656 _dpk_bb_afe_setting(rtwdev, phy, path, kpath);
2658 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2659 if (!(kpath & BIT(path)) || reloaded[path])
2662 is_fail = _dpk_main(rtwdev, phy, path, 1, chanctx_idx);
2663 _dpk_onoff(rtwdev, path, is_fail);
2666 _dpk_bb_afe_restore(rtwdev, phy, path, kpath);
2669 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2670 if (!(kpath & BIT(path)) || reloaded[path])
2673 _dpk_kip_restore(rtwdev, path);
2674 _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path);
2675 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
2676 if (rtwdev->is_tssi_mode[path])
2677 _dpk_tssi_pause(rtwdev, path, false);
2702 u8 path, kpath;
2706 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2707 if (kpath & BIT(path))
2708 _dpk_onoff(rtwdev, path, true);
2728 enum rtw89_rf_path path, bool off)
2731 u8 val, kidx = dpk->cur_idx[path];
2733 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok;
2735 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2738 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
2746 u8 path, kidx;
2753 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2754 kidx = dpk->cur_idx[path];
2758 path, kidx, dpk->bp[path][kidx].ch);
2760 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
2765 if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0)
2766 delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther;
2768 if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
2769 delta_ther[path] = delta_ther[path] * 3 / 2;
2771 delta_ther[path] = delta_ther[path] * 5 / 2;
2773 txagc_rf = (u8)rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2776 if (rtwdev->is_tssi_mode[path]) {
2777 trk_idx = (u8)rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK);
2785 R_TXAGC_BB + (path << 13),
2789 R_TXAGC_TP + (path << 13),
2798 R_TXAGC_BB + (path << 13),
2803 txagc_ofst, delta_ther[path]);
2805 if (rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8),
2810 ini_diff = txagc_ofst + delta_ther[path];
2812 if (rtw89_phy_read32_mask(rtwdev, R_P0_TXDPD + (path << 13),
2814 pwsf[0] = dpk->bp[path][kidx].pwsf + txagc_bb_tp -
2816 tssi_info->extra_ofst[path];
2817 pwsf[1] = dpk->bp[path][kidx].pwsf + txagc_bb_tp -
2819 tssi_info->extra_ofst[path];
2821 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff +
2822 tssi_info->extra_ofst[path];
2823 pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff +
2824 tssi_info->extra_ofst[path];
2828 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2829 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2838 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
2840 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2),
2847 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2852 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1);
2854 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1);
2869 enum rtw89_rf_path path,
2874 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2884 enum rtw89_rf_path path)
2886 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2892 enum rtw89_rf_path path)
2894 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
2900 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2953 if (path == RF_PATH_A) {
3057 enum rtw89_rf_path path)
3059 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3065 enum rtw89_rf_path path)
3067 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3073 enum rtw89_rf_path path)
3075 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3081 enum rtw89_rf_path path)
3083 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3089 enum rtw89_rf_path path)
3091 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3098 enum rtw89_rf_path path)
3100 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3106 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3113 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3118 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3123 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3128 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A,
3281 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3293 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
3294 path, gidx);
3299 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
3300 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
3304 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3305 path, val, de_1st, de_2nd);
3307 val = tssi_info->tssi_mcs[path][gidx];
3310 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3318 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3330 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3331 path, tgidx);
3336 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
3337 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
3341 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3342 path, val, tde_1st, tde_2nd);
3344 val = tssi_info->tssi_trim[path][tgidx];
3347 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3348 path, val);
3382 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
3399 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
3425 u8 path;
3438 for (path = RF_PATH_A; path < RF_PATH_NUM_8852A; path++) {
3439 if (!tssi_info->tssi_tracking_check[path]) {
3445 R_TSSI_THER + (path << 13),
3448 if (cur_ther == 0 || tssi_info->base_thermal[path] == 0)
3451 delta_ther = cur_ther - tssi_info->base_thermal[path];
3455 tssi_info->extra_ofst[path] = gain_offset;
3458 "[TSSI][TRK] base_thermal=%d gain_offset=0x%x path=%d\n",
3459 tssi_info->base_thermal[path], gain_offset, path);
3469 rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_EN + (path << 13),
3472 rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13),
3475 rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_ADDR + (path << 13),
3478 rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13),
3523 u8 path, s16 pwr_dbm, u8 enable, const struct rtw89_chan *chan)
3526 rtw8852a_bb_cfg_tx_path(rtwdev, path);
3621 u8 path;
3623 for (path = 0; path < 2; path++)
3624 _rck(rtwdev, path);