Lines Matching +full:0 +full:x45c
29 static const u32 rtw8852a_backup_bb_regs[] = {0x2344, 0x58f0, 0x78f0};
30 static const u32 rtw8852a_backup_rf_regs[] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5};
38 for (i = 0; i < BACKUP_BB_REGS_NR; i++) { in _rfk_backup_bb_reg()
53 for (i = 0; i < BACKUP_RF_REGS_NR; i++) { in _rfk_backup_rf_reg()
68 for (i = 0; i < BACKUP_BB_REGS_NR; i++) { in _rfk_restore_bb_reg()
82 for (i = 0; i < BACKUP_RF_REGS_NR; i++) { in _rfk_restore_rf_reg()
98 for (path = 0; path < RF_PATH_MAX; path++) { in _wait_rx_mode()
103 2, 5000, false, rtwdev, path, 0x00, in _wait_rx_mode()
118 "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
119 dack->addck_d[0][0], dack->addck_d[0][1]); in _dack_dump()
121 "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
122 dack->addck_d[1][0], dack->addck_d[1][1]); in _dack_dump()
124 "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
125 dack->dadck_d[0][0], dack->dadck_d[0][1]); in _dack_dump()
127 "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
128 dack->dadck_d[1][0], dack->dadck_d[1][1]); in _dack_dump()
131 "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n", in _dack_dump()
132 dack->biask_d[0][0], dack->biask_d[0][1]); in _dack_dump()
134 "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n", in _dack_dump()
135 dack->biask_d[1][0], dack->biask_d[1][1]); in _dack_dump()
138 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_dump()
139 t = dack->msbk_d[0][0][i]; in _dack_dump()
140 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
143 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_dump()
144 t = dack->msbk_d[0][1][i]; in _dack_dump()
145 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
148 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_dump()
149 t = dack->msbk_d[1][0][i]; in _dack_dump()
150 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
153 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_dump()
155 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
169 dack->addck_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK, in _addck_backup()
171 dack->addck_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK, in _addck_backup()
175 dack->addck_d[1][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK, in _addck_backup()
185 rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_I, dack->addck_d[0][0]); in _addck_reload()
187 (dack->addck_d[0][1] >> 6)); in _addck_reload()
189 (dack->addck_d[0][1] & 0x3f)); in _addck_reload()
191 rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_I, dack->addck_d[1][0]); in _addck_reload()
195 (dack->addck_d[1][1] & 0x3f)); in _addck_reload()
208 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_backup_s0()
210 dack->msbk_d[0][0][i] = in _dack_backup_s0()
213 dack->msbk_d[0][1][i] = in _dack_backup_s0()
216 dack->biask_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI2, in _dack_backup_s0()
218 dack->biask_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ2, in _dack_backup_s0()
220 dack->dadck_d[0][0] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI8, in _dack_backup_s0()
222 dack->dadck_d[0][1] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ8, in _dack_backup_s0()
235 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_backup_s1()
237 dack->msbk_d[1][0][i] = in _dack_backup_s1()
243 dack->biask_d[1][0] = in _dack_backup_s1()
247 dack->dadck_d[1][0] = in _dack_backup_s1()
257 u32 tmp = 0, tmp_offset, tmp_reg; in _dack_reload_by_path()
261 if (index == 0) in _dack_reload_by_path()
262 idx_offset = 0; in _dack_reload_by_path()
264 idx_offset = 0x50; in _dack_reload_by_path()
267 path_offset = 0; in _dack_reload_by_path()
269 path_offset = 0x2000; in _dack_reload_by_path()
273 tmp = 0x0; in _dack_reload_by_path()
274 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) in _dack_reload_by_path()
276 tmp_reg = 0x5e14 + tmp_offset; in _dack_reload_by_path()
278 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, in _dack_reload_by_path()
281 tmp = 0x0; in _dack_reload_by_path()
282 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) in _dack_reload_by_path()
284 tmp_reg = 0x5e18 + tmp_offset; in _dack_reload_by_path()
286 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, in _dack_reload_by_path()
289 tmp = 0x0; in _dack_reload_by_path()
290 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) in _dack_reload_by_path()
292 tmp_reg = 0x5e1c + tmp_offset; in _dack_reload_by_path()
294 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, in _dack_reload_by_path()
296 /* msbk_d: 3/2/1/0 */ in _dack_reload_by_path()
297 tmp = 0x0; in _dack_reload_by_path()
298 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) in _dack_reload_by_path()
300 tmp_reg = 0x5e20 + tmp_offset; in _dack_reload_by_path()
302 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, in _dack_reload_by_path()
305 tmp = 0x0; in _dack_reload_by_path()
308 tmp_reg = 0x5e24 + tmp_offset; in _dack_reload_by_path()
316 for (i = 0; i < 2; i++) in _dack_reload()
327 s32 dc_re = 0, dc_im = 0; in _check_addc()
335 for (i = 0; i < ADDC_T_AVG; i++) { in _check_addc()
337 dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11); in _check_addc()
338 dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11); in _check_addc()
345 "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im); in _check_addc()
363 false, rtwdev, 0x1e00, BIT(0)); in _addck()
366 dack->addck_timeout[0] = true; in _addck()
383 false, rtwdev, 0x3e00, BIT(0)); in _addck()
417 false, rtwdev, 0x5e28, BIT(15)); in _dack_s0()
419 false, rtwdev, 0x5e78, BIT(15)); in _dack_s0()
422 dack->msbk_timeout[0] = true; in _dack_s0()
429 false, rtwdev, 0x5e48, BIT(17)); in _dack_s0()
431 false, rtwdev, 0x5e98, BIT(17)); in _dack_s0()
434 dack->dadck_timeout[0] = true; in _dack_s0()
458 false, rtwdev, 0x7e28, BIT(15)); in _dack_s1()
460 false, rtwdev, 0x7e78, BIT(15)); in _dack_s1()
470 false, rtwdev, 0x7e48, BIT(17)); in _dack_s1()
472 false, rtwdev, 0x7e98, BIT(17)); in _dack_s1()
508 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0); in _dac_cal()
509 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0); in _dac_cal()
510 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x30001); in _dac_cal()
511 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x30001); in _dac_cal()
517 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x40001); in _dac_cal()
518 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x40001); in _dac_cal()
519 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0); in _dac_cal()
520 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0); in _dac_cal()
528 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1); in _dac_cal()
529 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1); in _dac_cal()
534 #define RTW8852A_NCTL_VER 0xd
535 #define RTW8852A_IQK_VER 0x2a
553 u8 i = 0x0; in _iqk_read_fft_dbcc0()
554 u32 fft[6] = {0x0}; in _iqk_read_fft_dbcc0()
557 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00160000); in _iqk_read_fft_dbcc0()
558 fft[0] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); in _iqk_read_fft_dbcc0()
559 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00170000); in _iqk_read_fft_dbcc0()
561 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00180000); in _iqk_read_fft_dbcc0()
563 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00190000); in _iqk_read_fft_dbcc0()
565 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001a0000); in _iqk_read_fft_dbcc0()
567 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001b0000); in _iqk_read_fft_dbcc0()
569 for (i = 0; i < 6; i++) in _iqk_read_fft_dbcc0()
576 u8 i = 0x0; in _iqk_read_xym_dbcc0()
577 u32 tmp = 0x0; in _iqk_read_xym_dbcc0()
581 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX, 0x1); in _iqk_read_xym_dbcc0()
583 for (i = 0x0; i < 0x18; i++) { in _iqk_read_xym_dbcc0()
584 rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x000000c0 + i); in _iqk_read_xym_dbcc0()
587 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = %x\n", in _iqk_read_xym_dbcc0()
592 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000); in _iqk_read_xym_dbcc0()
593 rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x80010100); in _iqk_read_xym_dbcc0()
601 {0x8f20, 0x8f54, 0x8f88, 0x8fbc}, in _iqk_read_txcfir_dbcc0()
602 {0x9320, 0x9354, 0x9388, 0x93bc}, in _iqk_read_txcfir_dbcc0()
604 u8 idx = 0x0; in _iqk_read_txcfir_dbcc0()
605 u32 tmp = 0x0; in _iqk_read_txcfir_dbcc0()
618 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001); in _iqk_read_txcfir_dbcc0()
622 for (idx = 0; idx < 0x0d; idx++) { in _iqk_read_txcfir_dbcc0()
629 if (path == 0x0) { in _iqk_read_txcfir_dbcc0()
632 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f50 = %x\n", tmp); in _iqk_read_txcfir_dbcc0()
634 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f84 = %x\n", tmp); in _iqk_read_txcfir_dbcc0()
636 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fb8 = %x\n", tmp); in _iqk_read_txcfir_dbcc0()
638 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fec = %x\n", tmp); in _iqk_read_txcfir_dbcc0()
642 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9350 = %x\n", tmp); in _iqk_read_txcfir_dbcc0()
644 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9384 = %x\n", tmp); in _iqk_read_txcfir_dbcc0()
646 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93b8 = %x\n", tmp); in _iqk_read_txcfir_dbcc0()
648 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93ec = %x\n", tmp); in _iqk_read_txcfir_dbcc0()
651 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xc); in _iqk_read_txcfir_dbcc0()
654 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path, in _iqk_read_txcfir_dbcc0()
662 {0x8d00, 0x8d44, 0x8d88, 0x8dcc}, in _iqk_read_rxcfir_dbcc0()
663 {0x9100, 0x9144, 0x9188, 0x91cc}, in _iqk_read_rxcfir_dbcc0()
665 u8 idx = 0x0; in _iqk_read_rxcfir_dbcc0()
666 u32 tmp = 0x0; in _iqk_read_rxcfir_dbcc0()
679 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001); in _iqk_read_rxcfir_dbcc0()
682 for (idx = 0; idx < 0x10; idx++) { in _iqk_read_rxcfir_dbcc0()
689 if (path == 0x0) { in _iqk_read_rxcfir_dbcc0()
692 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d40 = %x\n", tmp); in _iqk_read_rxcfir_dbcc0()
694 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d84 = %x\n", tmp); in _iqk_read_rxcfir_dbcc0()
696 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8dc8 = %x\n", tmp); in _iqk_read_rxcfir_dbcc0()
698 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8e0c = %x\n", tmp); in _iqk_read_rxcfir_dbcc0()
702 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9140 = %x\n", tmp); in _iqk_read_rxcfir_dbcc0()
704 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9184 = %x\n", tmp); in _iqk_read_rxcfir_dbcc0()
706 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x91c8 = %x\n", tmp); in _iqk_read_rxcfir_dbcc0()
708 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x920c = %x\n", tmp); in _iqk_read_rxcfir_dbcc0()
711 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xd); in _iqk_read_rxcfir_dbcc0()
713 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path, in _iqk_read_rxcfir_dbcc0()
719 u32 tmp = 0x0; in _iqk_sram()
720 u32 i = 0x0; in _iqk_sram()
723 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00020000); in _iqk_sram()
724 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX2, MASKDWORD, 0x00000080); in _iqk_sram()
725 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000); in _iqk_sram()
726 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009); in _iqk_sram()
728 for (i = 0; i <= 0x9f; i++) { in _iqk_sram()
729 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i); in _iqk_sram()
731 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp); in _iqk_sram()
734 for (i = 0; i <= 0x9f; i++) { in _iqk_sram()
735 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i); in _iqk_sram()
737 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp); in _iqk_sram()
746 u32 tmp = 0x0; in _iqk_rxk_setting()
749 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x3); in _iqk_rxk_setting()
750 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041); in _iqk_rxk_setting()
752 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x3); in _iqk_rxk_setting()
753 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0); in _iqk_rxk_setting()
755 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1); in _iqk_rxk_setting()
756 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x0); in _iqk_rxk_setting()
758 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303); in _iqk_rxk_setting()
759 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000); in _iqk_rxk_setting()
764 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1); in _iqk_rxk_setting()
768 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x5); in _iqk_rxk_setting()
769 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1); in _iqk_rxk_setting()
776 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13); in _iqk_rxk_setting()
777 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _iqk_rxk_setting()
778 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1); in _iqk_rxk_setting()
788 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, 1, 8200, in _iqk_check_cal()
789 false, rtwdev, 0xbff8, MASKBYTE0); in _iqk_check_cal()
796 "[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp); in _iqk_check_cal()
806 u32 iqk_cmd = 0x0; in _iqk_one_shot()
808 u32 addr_rfc_ctl = 0x0; in _iqk_one_shot()
811 addr_rfc_ctl = 0x5864; in _iqk_one_shot()
813 addr_rfc_ctl = 0x7864; in _iqk_one_shot()
818 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
821 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); in _iqk_one_shot()
822 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009); in _iqk_one_shot()
823 iqk_cmd = 0x108 | (1 << (4 + path)); in _iqk_one_shot()
826 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); in _iqk_one_shot()
827 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009); in _iqk_one_shot()
828 iqk_cmd = 0x208 | (1 << (4 + path)); in _iqk_one_shot()
831 rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000); in _iqk_one_shot()
832 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025); in _iqk_one_shot()
833 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
834 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
837 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
840 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); in _iqk_one_shot()
841 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011); in _iqk_one_shot()
842 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
843 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
846 rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000); in _iqk_one_shot()
847 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025); in _iqk_one_shot()
848 iqk_cmd = 0x308 | (1 << (4 + path)); in _iqk_one_shot()
851 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); in _iqk_one_shot()
852 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011); in _iqk_one_shot()
853 iqk_cmd = 0x608 | (1 << (4 + path)); in _iqk_one_shot()
871 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x0); in _iqk_one_shot()
872 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x1); in _iqk_one_shot()
873 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x2); in _iqk_one_shot()
874 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x3); in _iqk_one_shot()
876 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x0); in _iqk_one_shot()
877 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x1); in _iqk_one_shot()
878 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x2); in _iqk_one_shot()
879 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x3); in _iqk_one_shot()
883 rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000); in _iqk_one_shot()
894 static const u32 rxgn_a[4] = {0x18C, 0x1A0, 0x28C, 0x2A0}; in _rxk_group_sel()
895 static const u32 attc2_a[4] = {0x0, 0x0, 0x07, 0x30}; in _rxk_group_sel()
896 static const u32 attc1_a[4] = {0x7, 0x5, 0x1, 0x1}; in _rxk_group_sel()
897 static const u32 rxgn_g[4] = {0x1CC, 0x1E0, 0x2CC, 0x2E0}; in _rxk_group_sel()
898 static const u32 attc2_g[4] = {0x0, 0x15, 0x3, 0x1a}; in _rxk_group_sel()
899 static const u32 attc1_g[4] = {0x1, 0x0, 0x1, 0x0}; in _rxk_group_sel()
900 u8 gp = 0x0; in _rxk_group_sel()
902 u32 rf0 = 0x0; in _rxk_group_sel()
904 for (gp = 0; gp < 0x4; gp++) { in _rxk_group_sel()
923 rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100); in _rxk_group_sel()
928 rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN, 0x1); in _rxk_group_sel()
936 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); in _rxk_group_sel()
937 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _rxk_group_sel()
940 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _rxk_group_sel()
941 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _rxk_group_sel()
942 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0); in _rxk_group_sel()
947 iqk_info->nb_rxcfir[path] = 0x40000000; in _rxk_group_sel()
949 B_IQK_RES_RXCFIR, 0x5); in _rxk_group_sel()
958 u8 group = 0x0; in _iqk_nbrxk()
959 u32 rf0 = 0x0, tmp = 0x0; in _iqk_nbrxk()
960 u32 idxrxgain_a = 0x1a0; in _iqk_nbrxk()
961 u32 idxattc2_a = 0x00; in _iqk_nbrxk()
962 u32 idxattc1_a = 0x5; in _iqk_nbrxk()
963 u32 idxrxgain_g = 0x1E0; in _iqk_nbrxk()
964 u32 idxattc2_g = 0x15; in _iqk_nbrxk()
965 u32 idxattc1_g = 0x0; in _iqk_nbrxk()
986 rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100); in _iqk_nbrxk()
998 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); in _iqk_nbrxk()
999 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _iqk_nbrxk()
1002 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _iqk_nbrxk()
1003 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _iqk_nbrxk()
1004 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0); in _iqk_nbrxk()
1011 iqk_info->nb_rxcfir[path] = tmp | 0x2; in _iqk_nbrxk()
1013 iqk_info->nb_rxcfir[path] = 0x40000002; in _iqk_nbrxk()
1025 MASKDWORD, 0x4d000a08); in _iqk_rxclk_setting()
1027 B_P0_RXCK_VAL, 0x2); in _iqk_rxclk_setting()
1030 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x1); in _iqk_rxclk_setting()
1033 MASKDWORD, 0x44000a08); in _iqk_rxclk_setting()
1035 B_P0_RXCK_VAL, 0x1); in _iqk_rxclk_setting()
1045 static const u32 a_txgain[4] = {0xE466, 0x646D, 0xE4E2, 0x64ED}; in _txk_group_sel()
1046 static const u32 g_txgain[4] = {0x60e8, 0x60f0, 0x61e8, 0x61ED}; in _txk_group_sel()
1047 static const u32 a_itqt[4] = {0x12, 0x12, 0x12, 0x1b}; in _txk_group_sel()
1048 static const u32 g_itqt[4] = {0x09, 0x12, 0x12, 0x12}; in _txk_group_sel()
1049 static const u32 g_attsmxr[4] = {0x0, 0x1, 0x1, 0x1}; in _txk_group_sel()
1052 u8 gp = 0x0; in _txk_group_sel()
1053 u32 tmp = 0x0; in _txk_group_sel()
1055 for (gp = 0x0; gp < 0x4; gp++) { in _txk_group_sel()
1059 B_RFGAIN_BND, 0x08); in _txk_group_sel()
1071 B_RFGAIN_BND, 0x04); in _txk_group_sel()
1090 iqk_info->nb_txcfir[path] = 0x40000000; in _txk_group_sel()
1092 B_IQK_RES_TXCFIR, 0x5); in _txk_group_sel()
1095 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path, in _txk_group_sel()
1104 u8 group = 0x2; in _iqk_nbtxk()
1105 u32 a_mode_txgain = 0x64e2; in _iqk_nbtxk()
1106 u32 g_mode_txgain = 0x61e8; in _iqk_nbtxk()
1107 u32 attsmxr = 0x1; in _iqk_nbtxk()
1108 u32 itqt = 0x12; in _iqk_nbtxk()
1109 u32 tmp = 0x0; in _iqk_nbtxk()
1115 B_RFGAIN_BND, 0x08); in _iqk_nbtxk()
1122 B_RFGAIN_BND, 0x04); in _iqk_nbtxk()
1137 iqk_info->nb_txcfir[path] = tmp | 0x2; in _iqk_nbtxk()
1139 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_nbtxk()
1142 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path, in _iqk_nbtxk()
1152 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2); in _lok_res_table()
1154 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0); in _lok_res_table()
1156 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1); in _lok_res_table()
1158 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); in _lok_res_table()
1164 u32 tmp = 0x0; in _lok_finetune_check()
1165 u32 core_i = 0x0; in _lok_finetune_check()
1166 u32 core_q = 0x0; in _lok_finetune_check()
1169 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK][FineLOK] S%x, 0x58 = 0x%x\n", in _lok_finetune_check()
1173 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, i = 0x%x\n", path, core_i); in _lok_finetune_check()
1174 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, q = 0x%x\n", path, core_q); in _lok_finetune_check()
1176 if (core_i < 0x2 || core_i > 0x1d || core_q < 0x2 || core_q > 0x1d) in _lok_finetune_check()
1185 u32 rf0 = 0x0; in _iqk_lok()
1186 u8 itqt = 0x12; in _iqk_lok()
1192 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe5e0); in _iqk_lok()
1193 itqt = 0x09; in _iqk_lok()
1196 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe4e0); in _iqk_lok()
1197 itqt = 0x12; in _iqk_lok()
1207 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); in _iqk_lok()
1208 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, 0x1); in _iqk_lok()
1209 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, 0x0); in _iqk_lok()
1214 iqk_info->lok_cor_fail[0][path] = tmp; in _iqk_lok()
1218 iqk_info->lok_fin_fail[0][path] = tmp; in _iqk_lok()
1228 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f); in _iqk_txk_setting()
1230 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13); in _iqk_txk_setting()
1231 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001); in _iqk_txk_setting()
1233 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041); in _iqk_txk_setting()
1235 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303); in _iqk_txk_setting()
1236 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000); in _iqk_txk_setting()
1239 rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW, 0x00); in _iqk_txk_setting()
1240 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f); in _iqk_txk_setting()
1241 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0); in _iqk_txk_setting()
1242 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x1); in _iqk_txk_setting()
1243 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1); in _iqk_txk_setting()
1244 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0); in _iqk_txk_setting()
1245 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1246 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0); in _iqk_txk_setting()
1247 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x000); in _iqk_txk_setting()
1248 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1249 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1251 0x403e0 | iqk_info->syn1to2); in _iqk_txk_setting()
1255 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00); in _iqk_txk_setting()
1256 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f); in _iqk_txk_setting()
1257 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x7); in _iqk_txk_setting()
1258 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0); in _iqk_txk_setting()
1259 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1260 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0); in _iqk_txk_setting()
1261 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x100); in _iqk_txk_setting()
1262 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1263 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1264 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x1); in _iqk_txk_setting()
1265 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x0); in _iqk_txk_setting()
1267 0x403e0 | iqk_info->syn1to2); in _iqk_txk_setting()
1277 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); in _iqk_txclk_setting()
1284 u32 tmp = 0x0; in _iqk_info_iqk()
1285 bool flag = 0x0; in _iqk_info_iqk()
1290 iqk_info->lok_cor_fail[0][path]); in _iqk_info_iqk()
1292 iqk_info->lok_fin_fail[0][path]); in _iqk_info_iqk()
1294 iqk_info->iqk_tx_fail[0][path]); in _iqk_info_iqk()
1296 iqk_info->iqk_rx_fail[0][path]); in _iqk_info_iqk()
1297 flag = iqk_info->lok_cor_fail[0][path]; in _iqk_info_iqk()
1298 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(0) << (path * 4), flag); in _iqk_info_iqk()
1299 flag = iqk_info->lok_fin_fail[0][path]; in _iqk_info_iqk()
1301 flag = iqk_info->iqk_tx_fail[0][path]; in _iqk_info_iqk()
1303 flag = iqk_info->iqk_rx_fail[0][path]; in _iqk_info_iqk()
1316 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, 0x0000000f << (path * 4)); in _iqk_info_iqk()
1317 if (tmp != 0x0) in _iqk_info_iqk()
1319 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x00ff0000 << (path * 4), in _iqk_info_iqk()
1328 u8 ibias = 0x1; in _iqk_by_path()
1329 u8 i = 0; in _iqk_by_path()
1333 for (i = 0; i < 3; i++) { in _iqk_by_path()
1341 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path); in _iqk_by_path()
1343 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path); in _iqk_by_path()
1348 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path); in _iqk_by_path()
1350 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path); in _iqk_by_path()
1360 u32 reg_rf18 = 0x0, reg_35c = 0x0; in _iqk_get_ch_info()
1361 u8 idx = 0; in _iqk_get_ch_info()
1365 for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) { in _iqk_get_ch_info()
1366 if (iqk_info->iqk_mcc_ch[idx][path] == 0) { in _iqk_get_ch_info()
1374 idx = 0; in _iqk_get_ch_info()
1378 reg_35c = rtw89_phy_read32_mask(rtwdev, 0x35c, 0x00000c00); in _iqk_get_ch_info()
1385 "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path, in _iqk_get_ch_info()
1387 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_bw[%x] = 0x%x\n", in _iqk_get_ch_info()
1389 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_ch[%x] = 0x%x\n", in _iqk_get_ch_info()
1394 iqk_info->iqk_band[path] == 0 ? "2G" : in _iqk_get_ch_info()
1397 iqk_info->iqk_bw[path] == 0 ? "20M" : in _iqk_get_ch_info()
1399 if (reg_35c == 0x01) in _iqk_get_ch_info()
1400 iqk_info->syn1to2 = 0x1; in _iqk_get_ch_info()
1402 iqk_info->syn1to2 = 0x0; in _iqk_get_ch_info()
1405 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x000f << (path * 16), in _iqk_get_ch_info()
1407 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x00f0 << (path * 16), in _iqk_get_ch_info()
1409 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0xff00 << (path * 16), in _iqk_get_ch_info()
1412 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x000000ff, RTW8852A_NCTL_VER); in _iqk_get_ch_info()
1431 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000); in _iqk_restore()
1434 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000); in _iqk_restore()
1436 rtw89_phy_write32_mask(rtwdev, R_CFIR_MAP + (path << 8), MASKDWORD, 0xe4e4e4e4); in _iqk_restore()
1439 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD, 0x00000002); in _iqk_restore()
1440 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1441 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x0); in _iqk_restore()
1442 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1444 rtw89_write_rf(rtwdev, path, RR_TXRSV, RR_TXRSV_GAPK, 0x0); in _iqk_restore()
1445 rtw89_write_rf(rtwdev, path, RR_BIAS, RR_BIAS_GAPK, 0x0); in _iqk_restore()
1446 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _iqk_restore()
1476 B_COEF_SEL_IQC, path & 0x1); in _iqk_preset()
1478 B_CFIR_LUT_G2, path & 0x1); in _iqk_preset()
1485 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _iqk_preset()
1486 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080); in _iqk_preset()
1488 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a); in _iqk_preset()
1489 rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, MASKDWORD, 0x00200000); in _iqk_preset()
1490 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, MASKDWORD, 0x80000000); in _iqk_preset()
1519 u8 phy_idx = 0x0; in _iqk_dbcc()
1523 if (path == 0x0) in _iqk_dbcc()
1538 u32 rf_reg5, rck_val = 0; in _rck()
1546 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rck()
1549 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%x\n", in _rck()
1553 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240); in _rck()
1556 false, rtwdev, path, 0x1c, BIT(3)); in _rck()
1564 rtw89_write_rf(rtwdev, path, RR_RCKO, RR_RCKO_OFF, 0x4); in _rck()
1566 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x1); in _rck()
1567 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x0); in _rck()
1572 "[RCK] RF 0x1b / 0x1c / 0x1d = 0x%x / 0x%x / 0x%x\n", in _rck()
1594 iqk_info->iqk_times = 0x0; in _iqk_init()
1596 for (ch = 0; ch < RTW89_IQK_CHS_NR; ch++) { in _iqk_init()
1597 iqk_info->iqk_channel[ch] = 0x0; in _iqk_init()
1598 for (path = 0; path < RTW8852A_IQK_SS; path++) { in _iqk_init()
1603 iqk_info->iqk_mcc_ch[ch][path] = 0x0; in _iqk_init()
1604 iqk_info->iqk_table_idx[path] = 0x0; in _iqk_init()
1624 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version); in _doiqk()
1626 _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]); in _doiqk()
1627 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1633 _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]); in _doiqk()
1634 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1656 #define RXDCK_VER_8852A 0xe
1674 B_P0_RXCK_VAL, 0x3); in _set_rx_dck()
1677 B_S0_RXDC2_AVG, 0x3); in _set_rx_dck()
1678 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3); in _set_rx_dck()
1682 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_CRXBB, 0x1); in _set_rx_dck()
1685 rtw89_write_rf(rtwdev, path, RR_DCK2, RR_DCK2_CYCLE, 0x3f); in _set_rx_dck()
1690 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _set_rx_dck()
1691 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); in _set_rx_dck()
1697 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _set_rx_dck()
1714 "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, Cv: %d) ******\n", in _rx_dck()
1719 for (path = 0; path < 2; path++) { in _rx_dck()
1727 addr = 0x5818 + (path << 13); in _rx_dck()
1732 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rx_dck()
1733 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0); in _rx_dck()
1740 addr = 0x5818 + (path << 13); in _rx_dck()
1748 #define RTW8852A_DPK_VER 0x10
1754 LBK_RXIQK = 0x06,
1755 SYNC = 0x10,
1756 MDPK_IDL = 0x11,
1757 MDPK_MPA = 0x12,
1758 GAIN_LOSS = 0x13,
1759 GAIN_CAL = 0x14,
1766 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _rf_direct_cntrl()
1768 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rf_direct_cntrl()
1780 for (i = 0; i < RTW8852A_DPK_KIP_REG_NUM; i++) { in _dpk_bkup_kip()
1784 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n", in _dpk_bkup_kip()
1794 for (i = 0; i < RTW8852A_DPK_KIP_REG_NUM; i++) { in _dpk_reload_kip()
1797 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Reload 0x%x = %x\n", in _dpk_reload_kip()
1806 u16 dpk_cmd = 0x0; in _dpk_one_shot()
1810 dpk_cmd = (u16)((id << 8) | (0x19 + (path << 4))); in _dpk_one_shot()
1817 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, in _dpk_one_shot()
1818 10, 20000, false, rtwdev, 0xbff8, MASKBYTE0); in _dpk_one_shot()
1825 "[DPK] one-shot for %s = 0x%x (ret=%d)\n", in _dpk_one_shot()
1826 id == 0x06 ? "LBK_RXIQK" : in _dpk_one_shot()
1827 id == 0x10 ? "SYNC" : in _dpk_one_shot()
1828 id == 0x11 ? "MDPK_IDL" : in _dpk_one_shot()
1829 id == 0x12 ? "MDPK_MPA" : in _dpk_one_shot()
1830 id == 0x13 ? "GAIN_LOSS" : "PWR_CAL", in _dpk_one_shot()
1839 return 0; in _dpk_one_shot()
1846 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3); in _dpk_rx_dck()
1867 dpk->bp[path][kidx].band == 0 ? "2G" : in _dpk_information()
1870 dpk->bp[path][kidx].bw == 0 ? "20M" : in _dpk_information()
1882 if (rtw89_phy_read32_mask(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL) == 0x0) in _dpk_bb_afe_setting()
1890 if (rtw89_phy_read32_mask(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL) == 0x1) in _dpk_bb_afe_setting()
1939 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080); in _dpk_kip_setting()
1940 rtw89_phy_write32_mask(rtwdev, R_KIP_CLK, MASKDWORD, 0x00093f3f); in _dpk_kip_setting()
1941 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a); in _dpk_kip_setting()
1942 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); in _dpk_kip_setting()
1943 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG, B_DPK_CFG_IDX, 0x2); in _dpk_kip_setting()
1946 MASKDWORD, 0x003f2e2e); in _dpk_kip_setting()
1948 MASKDWORD, 0x005b5b5b); in _dpk_kip_setting()
1958 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000); in _dpk_kip_restore()
1959 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000); in _dpk_kip_restore()
1963 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), BIT(15), 0x1); in _dpk_kip_restore()
1978 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _dpk_lbk_rxiqk()
1979 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1); in _dpk_lbk_rxiqk()
1980 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x2); in _dpk_lbk_rxiqk()
1983 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13); in _dpk_lbk_rxiqk()
1984 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _dpk_lbk_rxiqk()
1985 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1); in _dpk_lbk_rxiqk()
1989 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTL, 0x1f); in _dpk_lbk_rxiqk()
1991 if (cur_rxbb <= 0xa) in _dpk_lbk_rxiqk()
1992 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x3); in _dpk_lbk_rxiqk()
1993 else if (cur_rxbb <= 0x10 && cur_rxbb >= 0xb) in _dpk_lbk_rxiqk()
1994 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x1); in _dpk_lbk_rxiqk()
1996 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x0); in _dpk_lbk_rxiqk()
1998 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11); in _dpk_lbk_rxiqk()
2002 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path, in _dpk_lbk_rxiqk()
2005 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0); in _dpk_lbk_rxiqk()
2006 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x0); in _dpk_lbk_rxiqk()
2007 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); /*POW IQKPLL*/ in _dpk_lbk_rxiqk()
2021 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] thermal@DPK = 0x%x\n", in _dpk_get_thermal()
2028 u8 txagc_ori = 0x38; in _dpk_set_tx_pwr()
2041 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x280b); in _dpk_rf_setting()
2042 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x0); in _dpk_rf_setting()
2043 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x4); in _dpk_rf_setting()
2044 rtw89_write_rf(rtwdev, path, RR_MIXER, RR_MIXER_GN, 0x0); in _dpk_rf_setting()
2046 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x282e); in _dpk_rf_setting()
2047 rtw89_write_rf(rtwdev, path, RR_BIASA2, RR_BIASA2_LB, 0x7); in _dpk_rf_setting()
2048 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW, 0x3); in _dpk_rf_setting()
2049 rtw89_write_rf(rtwdev, path, RR_RXA, RR_RXA_DPK, 0x3); in _dpk_rf_setting()
2051 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1); in _dpk_rf_setting()
2053 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0); in _dpk_rf_setting()
2056 "[DPK] RF 0x0/0x1/0x1a = 0x%x/ 0x%x/ 0x%x\n", in _dpk_rf_setting()
2068 rtw89_phy_write32_mask(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN, 0x1); in _dpk_manual_txcfir()
2078 B_LOAD_COEF_CFIR, 0x1); in _dpk_manual_txcfir()
2082 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), BIT(1), 0x1); in _dpk_manual_txcfir()
2085 "[DPK] PAD_man / TXBB_man = 0x%x / 0x%x\n", tmp_pad, in _dpk_manual_txcfir()
2099 B_RXIQC_BYPASS2, 0x1); in _dpk_bypass_rxcfir()
2101 B_RXIQC_BYPASS, 0x1); in _dpk_bypass_rxcfir()
2103 "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path, in _dpk_bypass_rxcfir()
2110 "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path, in _dpk_bypass_rxcfir()
2124 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2); in _dpk_tpg_sel()
2126 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1); in _dpk_tpg_sel()
2138 val = 0x80 + kidx * 0x20 + gain * 0x10; in _dpk_table_select()
2141 "[DPK] table select for Kidx[%d], Gain[%d] (0x%x)\n", kidx, in _dpk_table_select()
2164 dpk->corr_idx[path][0] = corr_idx; in _dpk_sync_check()
2165 dpk->corr_val[path][0] = corr_val; in _dpk_sync_check()
2167 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9); in _dpk_sync_check()
2178 dpk->dc_i[path][0] = dc_i; in _dpk_sync_check()
2179 dpk->dc_q[path][0] = dc_q; in _dpk_sync_check()
2198 u16 dgain = 0x0; in _dpk_dgain_read()
2206 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x (%d)\n", dgain, in _dpk_dgain_read()
2216 if (dgain >= 0x783) in _dpk_dgain_mapping()
2217 offset = 0x6; in _dpk_dgain_mapping()
2218 else if (dgain <= 0x782 && dgain >= 0x551) in _dpk_dgain_mapping()
2219 offset = 0x3; in _dpk_dgain_mapping()
2220 else if (dgain <= 0x550 && dgain >= 0x3c4) in _dpk_dgain_mapping()
2221 offset = 0x0; in _dpk_dgain_mapping()
2222 else if (dgain <= 0x3c3 && dgain >= 0x2aa) in _dpk_dgain_mapping()
2224 else if (dgain <= 0x2a9 && dgain >= 0x1e3) in _dpk_dgain_mapping()
2226 else if (dgain <= 0x1e2 && dgain >= 0x156) in _dpk_dgain_mapping()
2228 else if (dgain <= 0x155) in _dpk_dgain_mapping()
2231 offset = 0x0; in _dpk_dgain_mapping()
2238 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6); in _dpk_gainloss_read()
2239 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1); in _dpk_gainloss_read()
2251 #define DPK_TXAGC_LOWER 0x2e
2252 #define DPK_TXAGC_UPPER 0x3f
2253 #define DPK_TXAGC_INVAL 0xff
2271 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp_txagc (GL=%d) = 0x%x\n", in _dpk_set_offset()
2287 u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0; in _dpk_pas_read()
2293 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00); in _dpk_pas_read()
2298 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f); in _dpk_pas_read()
2304 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n", in _dpk_pas_read()
2309 for (i = 0; i < 32; i++) { in _dpk_pas_read()
2312 "[DPK] PAS_Read[%02d]= 0x%08x\n", i, in _dpk_pas_read()
2320 return 0; in _dpk_pas_read()
2330 #define DPK_RXBB_UPPER 0x1f in _dpk_agc()
2331 #define DPK_RXBB_LOWER 0 in _dpk_agc()
2334 u8 tmp_txagc, tmp_rxbb = 0, tmp_gl_idx = 0; in _dpk_agc()
2335 u8 agc_cnt = 0; in _dpk_agc()
2337 s8 offset = 0; in _dpk_agc()
2338 u16 dgain = 0; in _dpk_agc()
2377 "[DPK] Adjust RXBB (%d) = 0x%x\n", offset, in _dpk_agc()
2379 if (offset != 0 || agc_cnt == 0) { in _dpk_agc()
2397 if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true)) || in _dpk_agc()
2400 else if (tmp_gl_idx == 0) in _dpk_agc()
2443 "[DPK] Txagc / RXBB for DPK = 0x%x / 0x%x\n", tmp_txagc, in _dpk_agc()
2452 case 0: in _dpk_set_mdpd_para()
2454 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x3); in _dpk_set_mdpd_para()
2455 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x1); in _dpk_set_mdpd_para()
2469 "[DPK] Wrong MDPD order!!(0x%x)\n", order); in _dpk_set_mdpd_para()
2474 "[DPK] Set MDPD order to 0x%x for IDL\n", order); in _dpk_set_mdpd_para()
2480 _dpk_set_mdpd_para(rtwdev, 0x0); in _dpk_idl_mpa()
2491 u16 pwsf = 0x78; in _dpk_fill_result()
2492 u8 gs = 0x5b; in _dpk_fill_result()
2497 "[DPK] Fill txagc/ pwsf/ gs = 0x%x/ 0x%x/ 0x%x\n", txagc, in _dpk_fill_result()
2502 0x3F << ((gain << 3) + (kidx << 4)), txagc); in _dpk_fill_result()
2506 0x1FF << (gain << 4), pwsf); in _dpk_fill_result()
2508 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1); in _dpk_fill_result()
2513 MASKDWORD, 0x065b5b5b); in _dpk_fill_result()
2531 for (idx = 0; idx < RTW89_DPK_BKUP_NUM; idx++) { in _dpk_reload_check()
2551 u8 txagc = 0, kidx = dpk->cur_idx[path]; in _dpk_main()
2592 u32 kip_bkup[RTW8852A_DPK_RF_PATH][RTW8852A_DPK_KIP_REG_NUM] = {{0}}; in _dpk_cal_select()
2598 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2603 if (!reloaded[path] && dpk->bp[path][0].ch != 0) in _dpk_cal_select()
2609 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) in _dpk_cal_select()
2610 dpk->cur_idx[path] = 0; in _dpk_cal_select()
2618 _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]); in _dpk_cal_select()
2620 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2626 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2632 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2641 _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]); in _dpk_cal_select()
2643 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2649 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2679 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_force_bypass()
2688 "[DPK] ****** DPK Start (Ver: 0x%x, Cv: %d, RF_para: %d) ******\n", in _dpk()
2707 MASKBYTE3, 0x6 | val); in _dpk_onoff()
2718 u8 trk_idx = 0, txagc_rf = 0; in _dpk_track()
2719 s8 txagc_bb = 0, txagc_bb_tp = 0, ini_diff = 0, txagc_ofst = 0; in _dpk_track()
2722 s8 delta_ther[2] = {0}; in _dpk_track()
2724 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_track()
2736 if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0) in _dpk_track()
2751 "[DPK_TRK] txagc_RF / track_idx = 0x%x / %d\n", in _dpk_track()
2764 "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n", in _dpk_track()
2777 BIT(15)) == 0x1) in _dpk_track()
2778 txagc_ofst = 0; in _dpk_track()
2780 if (txagc_rf != 0 && cur_ther != 0) in _dpk_track()
2784 B_P0_TXDPD) == 0x0) { in _dpk_track()
2785 pwsf[0] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - in _dpk_track()
2792 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff + in _dpk_track()
2799 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2800 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2803 if (rtw89_phy_read32_mask(rtwdev, R_DPK_TRK, B_DPK_TRK_DIS) == 0x0 && in _dpk_track()
2804 txagc_rf != 0) { in _dpk_track()
2806 "[DPK_TRK] New pwsf[0] / pwsf[1] = 0x%x / 0x%x\n", in _dpk_track()
2807 pwsf[0], pwsf[1]); in _dpk_track()
2810 0x000001FF, pwsf[0]); in _dpk_track()
2812 0x01FF0000, pwsf[1]); in _dpk_track()
2824 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1); in _tssi_rf_setting()
2826 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1); in _tssi_rf_setting()
2878 u32 __val = 0; \ in _tssi_set_tmeter_tbl()
2879 for (__i = 0; __i < 4; __i++) { \ in _tssi_set_tmeter_tbl()
2893 u8 thermal = 0xff; in _tssi_set_tmeter_tbl()
2894 s8 thm_ofst[64] = {0}; in _tssi_set_tmeter_tbl()
2895 u32 tmp = 0; in _tssi_set_tmeter_tbl()
2907 thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[0]; in _tssi_set_tmeter_tbl()
2908 thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[0]; in _tssi_set_tmeter_tbl()
2909 thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[0]; in _tssi_set_tmeter_tbl()
2910 thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[0]; in _tssi_set_tmeter_tbl()
2930 "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal); in _tssi_set_tmeter_tbl()
2932 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0); in _tssi_set_tmeter_tbl()
2933 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1); in _tssi_set_tmeter_tbl()
2935 if (thermal == 0xff) { in _tssi_set_tmeter_tbl()
2939 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
2940 rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0); in _tssi_set_tmeter_tbl()
2943 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
2944 0x5c00 + i, 0x0); in _tssi_set_tmeter_tbl()
2952 i = 0; in _tssi_set_tmeter_tbl()
2953 for (j = 0; j < 32; j++) in _tssi_set_tmeter_tbl()
2964 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
2969 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
2970 0x5c00 + i, tmp); in _tssi_set_tmeter_tbl()
2973 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1); in _tssi_set_tmeter_tbl()
2974 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0); in _tssi_set_tmeter_tbl()
2980 "[TSSI] ch=%d thermal_pathB=0x%x\n", ch, thermal); in _tssi_set_tmeter_tbl()
2982 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_DIS, 0x0); in _tssi_set_tmeter_tbl()
2983 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_TRK, 0x1); in _tssi_set_tmeter_tbl()
2985 if (thermal == 0xff) { in _tssi_set_tmeter_tbl()
2989 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
2990 rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, 0x0); in _tssi_set_tmeter_tbl()
2993 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
2994 0x7c00 + i, 0x0); in _tssi_set_tmeter_tbl()
3002 i = 0; in _tssi_set_tmeter_tbl()
3003 for (j = 0; j < 32; j++) in _tssi_set_tmeter_tbl()
3014 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
3019 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
3020 0x7c00 + i, tmp); in _tssi_set_tmeter_tbl()
3023 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x1); in _tssi_set_tmeter_tbl()
3024 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x0); in _tssi_set_tmeter_tbl()
3114 for (i = 0; i < RF_PATH_NUM_8852A; i++) { in _tssi_enable()
3140 return 0; in _tssi_get_cck_group()
3153 return 0; in _tssi_get_cck_group()
3166 return 0; in _tssi_get_ofdm_group()
3227 return 0; in _tssi_get_ofdm_group()
3234 return 0; in _tssi_get_trim_group()
3251 return 0; in _tssi_get_trim_group()
3261 s8 de_1st = 0; in _tssi_get_ofdm_de()
3262 s8 de_2nd = 0; in _tssi_get_ofdm_de()
3268 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", in _tssi_get_ofdm_de()
3299 s8 tde_1st = 0; in _tssi_get_ofdm_trim_de()
3300 s8 tde_2nd = 0; in _tssi_get_ofdm_trim_de()
3306 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", in _tssi_get_ofdm_trim_de()
3333 #define __DE_MASK 0x003ff000 in _tssi_set_efuse_to_de()
3336 static const u32 r_cck_long[RF_PATH_NUM_8852A] = {0x5858, 0x7858}; in _tssi_set_efuse_to_de()
3337 static const u32 r_cck_short[RF_PATH_NUM_8852A] = {0x5860, 0x7860}; in _tssi_set_efuse_to_de()
3338 static const u32 r_mcs_20m[RF_PATH_NUM_8852A] = {0x5838, 0x7838}; in _tssi_set_efuse_to_de()
3339 static const u32 r_mcs_40m[RF_PATH_NUM_8852A] = {0x5840, 0x7840}; in _tssi_set_efuse_to_de()
3340 static const u32 r_mcs_80m[RF_PATH_NUM_8852A] = {0x5848, 0x7848}; in _tssi_set_efuse_to_de()
3341 static const u32 r_mcs_80m_80m[RF_PATH_NUM_8852A] = {0x5850, 0x7850}; in _tssi_set_efuse_to_de()
3342 static const u32 r_mcs_5m[RF_PATH_NUM_8852A] = {0x5828, 0x7828}; in _tssi_set_efuse_to_de()
3343 static const u32 r_mcs_10m[RF_PATH_NUM_8852A] = {0x5830, 0x7830}; in _tssi_set_efuse_to_de()
3353 for (i = 0; i < RF_PATH_NUM_8852A; i++) { in _tssi_set_efuse_to_de()
3359 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3366 "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n", in _tssi_set_efuse_to_de()
3376 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3387 "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n", in _tssi_set_efuse_to_de()
3398 0x400, 0x40e, 0x41d, 0x427, 0x43c, 0x44c, 0x45c, 0x46c, in _tssi_track()
3399 0x400, 0x39d, 0x3ab, 0x3b8, 0x3c6, 0x3d4, 0x3e2, 0x3f1 in _tssi_track()
3404 s32 delta_ther = 0, gain_offset_int, gain_offset_float; in _tssi_track()
3425 if (cur_ther == 0 || tssi_info->base_thermal[path] == 0) in _tssi_track()
3435 "[TSSI][TRK] base_thermal=%d gain_offset=0x%x path=%d\n", in _tssi_track()
3447 B_DPD_OFT_EN, 0x1); in _tssi_track()
3450 B_TXGAIN_SCALE_EN, 0x1); in _tssi_track()
3492 tssi_info->extra_ofst[RF_PATH_A] = 0; in _tssi_high_power()
3493 tssi_info->extra_ofst[RF_PATH_B] = 0; in _tssi_high_power()
3505 rtw8852a_bb_set_pmac_pkt_tx(rtwdev, enable, 20, 5000, 0, phy); in _tssi_hw_tx()
3517 u8 phy_map = rtw89_btc_phymap(rtwdev, phy, 0); in _tssi_pre_tx()
3520 u32 i, tx_counter = 0; in _tssi_pre_tx()
3556 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, MASKHWORD) != 0xc000 && in _tssi_pre_tx()
3557 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, MASKHWORD) != 0x0) { in _tssi_pre_tx()
3558 for (i = 0; i < 6; i++) { in _tssi_pre_tx()
3563 if (tssi_info->default_txagc_offset[RF_PATH_A] != 0x0) in _tssi_pre_tx()
3568 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, MASKHWORD) != 0xc000 && in _tssi_pre_tx()
3569 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, MASKHWORD) != 0x0) { in _tssi_pre_tx()
3570 for (i = 0; i < 6; i++) { in _tssi_pre_tx()
3575 if (tssi_info->default_txagc_offset[RF_PATH_B] != 0x0) in _tssi_pre_tx()
3585 "[TSSI] Backup R_TXAGC_BB=0x%x R_TXAGC_BB_S1=0x%x\n", in _tssi_pre_tx()
3589 rtw8852a_bb_tx_mode_switch(rtwdev, phy, 0); in _tssi_pre_tx()
3599 for (path = 0; path < 2; path++) in rtw8852a_rck()
3605 u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0); in rtw8852a_dack()
3615 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); in rtw8852a_iqk()
3635 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); in rtw8852a_rx_dck()
3650 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); in rtw8852a_dpk()
3737 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x0); in _rtw8852a_tssi_avg_scan()
3738 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x0); in _rtw8852a_tssi_avg_scan()
3740 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x0); in _rtw8852a_tssi_avg_scan()
3741 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x0); in _rtw8852a_tssi_avg_scan()
3756 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x4); in _rtw8852a_tssi_set_avg()
3757 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x2); in _rtw8852a_tssi_set_avg()
3759 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x4); in _rtw8852a_tssi_set_avg()
3760 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x2); in _rtw8852a_tssi_set_avg()
3791 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, B_TXAGC_BB_OFT) != 0xc000 && in rtw8852a_tssi_default_txagc()
3792 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, B_TXAGC_BB_OFT) != 0x0) { in rtw8852a_tssi_default_txagc()
3793 for (i = 0; i < 6; i++) { in rtw8852a_tssi_default_txagc()
3802 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, B_TXAGC_BB_S1_OFT) != 0xc000 && in rtw8852a_tssi_default_txagc()
3803 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, B_TXAGC_BB_S1_OFT) != 0x0) { in rtw8852a_tssi_default_txagc()
3804 for (i = 0; i < 6; i++) { in rtw8852a_tssi_default_txagc()
3818 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0); in rtw8852a_tssi_default_txagc()
3819 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1); in rtw8852a_tssi_default_txagc()
3821 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x0); in rtw8852a_tssi_default_txagc()
3822 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x1); in rtw8852a_tssi_default_txagc()