Lines Matching +full:0 +full:x40e
29 static const u32 rtw8852a_backup_bb_regs[] = {0x2344, 0x58f0, 0x78f0};
30 static const u32 rtw8852a_backup_rf_regs[] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5};
38 for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
53 for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
68 for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
82 for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
98 for (path = 0; path < RF_PATH_MAX; path++) {
103 2, 5000, false, rtwdev, path, 0x00,
118 "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n",
119 dack->addck_d[0][0], dack->addck_d[0][1]);
121 "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n",
122 dack->addck_d[1][0], dack->addck_d[1][1]);
124 "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
125 dack->dadck_d[0][0], dack->dadck_d[0][1]);
127 "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
128 dack->dadck_d[1][0], dack->dadck_d[1][1]);
131 "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n",
132 dack->biask_d[0][0], dack->biask_d[0][1]);
134 "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n",
135 dack->biask_d[1][0], dack->biask_d[1][1]);
138 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
139 t = dack->msbk_d[0][0][i];
140 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
143 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
144 t = dack->msbk_d[0][1][i];
145 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
148 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
149 t = dack->msbk_d[1][0][i];
150 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
153 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
155 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
169 dack->addck_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK,
171 dack->addck_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK,
175 dack->addck_d[1][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK,
185 rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_I, dack->addck_d[0][0]);
187 (dack->addck_d[0][1] >> 6));
189 (dack->addck_d[0][1] & 0x3f));
191 rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_I, dack->addck_d[1][0]);
195 (dack->addck_d[1][1] & 0x3f));
208 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
210 dack->msbk_d[0][0][i] =
213 dack->msbk_d[0][1][i] =
216 dack->biask_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI2,
218 dack->biask_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ2,
220 dack->dadck_d[0][0] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI8,
222 dack->dadck_d[0][1] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ8,
235 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
237 dack->msbk_d[1][0][i] =
243 dack->biask_d[1][0] =
247 dack->dadck_d[1][0] =
257 u32 tmp = 0, tmp_offset, tmp_reg;
261 if (index == 0)
262 idx_offset = 0;
264 idx_offset = 0x50;
267 path_offset = 0;
269 path_offset = 0x2000;
273 tmp = 0x0;
274 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
276 tmp_reg = 0x5e14 + tmp_offset;
278 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
281 tmp = 0x0;
282 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
284 tmp_reg = 0x5e18 + tmp_offset;
286 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
289 tmp = 0x0;
290 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
292 tmp_reg = 0x5e1c + tmp_offset;
294 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
296 /* msbk_d: 3/2/1/0 */
297 tmp = 0x0;
298 for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++)
300 tmp_reg = 0x5e20 + tmp_offset;
302 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg,
305 tmp = 0x0;
308 tmp_reg = 0x5e24 + tmp_offset;
316 for (i = 0; i < 2; i++)
327 s32 dc_re = 0, dc_im = 0;
335 for (i = 0; i < ADDC_T_AVG; i++) {
337 dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11);
338 dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11);
345 "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im);
363 false, rtwdev, 0x1e00, BIT(0));
366 dack->addck_timeout[0] = true;
383 false, rtwdev, 0x3e00, BIT(0));
417 false, rtwdev, 0x5e28, BIT(15));
419 false, rtwdev, 0x5e78, BIT(15));
422 dack->msbk_timeout[0] = true;
429 false, rtwdev, 0x5e48, BIT(17));
431 false, rtwdev, 0x5e98, BIT(17));
434 dack->dadck_timeout[0] = true;
458 false, rtwdev, 0x7e28, BIT(15));
460 false, rtwdev, 0x7e78, BIT(15));
470 false, rtwdev, 0x7e48, BIT(17));
472 false, rtwdev, 0x7e98, BIT(17));
509 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0);
510 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0);
511 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x30001);
512 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x30001);
518 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x40001);
519 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x40001);
520 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0);
521 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0);
529 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1);
530 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1);
535 #define RTW8852A_NCTL_VER 0xd
536 #define RTW8852A_IQK_VER 0x2a
554 u8 i = 0x0;
555 u32 fft[6] = {0x0};
558 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00160000);
559 fft[0] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD);
560 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00170000);
562 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00180000);
564 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00190000);
566 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001a0000);
568 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001b0000);
570 for (i = 0; i < 6; i++)
577 u8 i = 0x0;
578 u32 tmp = 0x0;
582 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX, 0x1);
584 for (i = 0x0; i < 0x18; i++) {
585 rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x000000c0 + i);
588 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = %x\n",
593 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000);
594 rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x80010100);
602 {0x8f20, 0x8f54, 0x8f88, 0x8fbc},
603 {0x9320, 0x9354, 0x9388, 0x93bc},
605 u8 idx = 0x0;
606 u32 tmp = 0x0;
619 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001);
623 for (idx = 0; idx < 0x0d; idx++) {
630 if (path == 0x0) {
633 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f50 = %x\n", tmp);
635 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f84 = %x\n", tmp);
637 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fb8 = %x\n", tmp);
639 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fec = %x\n", tmp);
643 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9350 = %x\n", tmp);
645 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9384 = %x\n", tmp);
647 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93b8 = %x\n", tmp);
649 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93ec = %x\n", tmp);
652 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xc);
655 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path,
663 {0x8d00, 0x8d44, 0x8d88, 0x8dcc},
664 {0x9100, 0x9144, 0x9188, 0x91cc},
666 u8 idx = 0x0;
667 u32 tmp = 0x0;
680 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001);
683 for (idx = 0; idx < 0x10; idx++) {
690 if (path == 0x0) {
693 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d40 = %x\n", tmp);
695 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d84 = %x\n", tmp);
697 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8dc8 = %x\n", tmp);
699 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8e0c = %x\n", tmp);
703 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9140 = %x\n", tmp);
705 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9184 = %x\n", tmp);
707 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x91c8 = %x\n", tmp);
709 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x920c = %x\n", tmp);
712 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xd);
714 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path,
720 u32 tmp = 0x0;
721 u32 i = 0x0;
724 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00020000);
725 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX2, MASKDWORD, 0x00000080);
726 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000);
727 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
729 for (i = 0; i <= 0x9f; i++) {
730 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i);
732 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp);
735 for (i = 0; i <= 0x9f; i++) {
736 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i);
738 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp);
747 u32 tmp = 0x0;
750 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x3);
751 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041);
753 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x3);
754 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0);
756 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1);
757 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x0);
759 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303);
760 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000);
765 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1);
769 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x5);
770 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1);
777 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
778 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
779 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1);
789 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, 1, 8200,
790 false, rtwdev, 0xbff8, MASKBYTE0);
797 "[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp);
808 u32 iqk_cmd = 0x0;
810 u32 addr_rfc_ctl = 0x0;
813 addr_rfc_ctl = 0x5864;
815 addr_rfc_ctl = 0x7864;
820 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1);
823 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
824 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
825 iqk_cmd = 0x108 | (1 << (4 + path));
828 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
829 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
830 iqk_cmd = 0x208 | (1 << (4 + path));
833 rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
834 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025);
835 iqk_cmd = 0x008 | (1 << (path + 4)) |
836 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
839 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1);
842 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
843 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
844 iqk_cmd = 0x008 | (1 << (path + 4)) |
845 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8);
848 rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
849 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025);
850 iqk_cmd = 0x308 | (1 << (4 + path));
853 rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000);
854 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
855 iqk_cmd = 0x608 | (1 << (4 + path));
873 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x0);
874 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x1);
875 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x2);
876 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x3);
878 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x0);
879 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x1);
880 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x2);
881 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x3);
885 rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000);
897 static const u32 rxgn_a[4] = {0x18C, 0x1A0, 0x28C, 0x2A0};
898 static const u32 attc2_a[4] = {0x0, 0x0, 0x07, 0x30};
899 static const u32 attc1_a[4] = {0x7, 0x5, 0x1, 0x1};
900 static const u32 rxgn_g[4] = {0x1CC, 0x1E0, 0x2CC, 0x2E0};
901 static const u32 attc2_g[4] = {0x0, 0x15, 0x3, 0x1a};
902 static const u32 attc1_g[4] = {0x1, 0x0, 0x1, 0x0};
903 u8 gp = 0x0;
905 u32 rf0 = 0x0;
907 for (gp = 0; gp < 0x4; gp++) {
926 rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100);
931 rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN, 0x1);
939 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0);
940 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
943 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
944 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
945 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0);
950 iqk_info->nb_rxcfir[path] = 0x40000000;
952 B_IQK_RES_RXCFIR, 0x5);
962 u8 group = 0x0;
963 u32 rf0 = 0x0, tmp = 0x0;
964 u32 idxrxgain_a = 0x1a0;
965 u32 idxattc2_a = 0x00;
966 u32 idxattc1_a = 0x5;
967 u32 idxrxgain_g = 0x1E0;
968 u32 idxattc2_g = 0x15;
969 u32 idxattc1_g = 0x0;
990 rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100);
1002 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0);
1003 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
1006 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0);
1007 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
1008 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0);
1015 iqk_info->nb_rxcfir[path] = tmp | 0x2;
1017 iqk_info->nb_rxcfir[path] = 0x40000002;
1029 MASKDWORD, 0x4d000a08);
1031 B_P0_RXCK_VAL, 0x2);
1034 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x1);
1037 MASKDWORD, 0x44000a08);
1039 B_P0_RXCK_VAL, 0x1);
1050 static const u32 a_txgain[4] = {0xE466, 0x646D, 0xE4E2, 0x64ED};
1051 static const u32 g_txgain[4] = {0x60e8, 0x60f0, 0x61e8, 0x61ED};
1052 static const u32 a_itqt[4] = {0x12, 0x12, 0x12, 0x1b};
1053 static const u32 g_itqt[4] = {0x09, 0x12, 0x12, 0x12};
1054 static const u32 g_attsmxr[4] = {0x0, 0x1, 0x1, 0x1};
1057 u8 gp = 0x0;
1058 u32 tmp = 0x0;
1060 for (gp = 0x0; gp < 0x4; gp++) {
1064 B_RFGAIN_BND, 0x08);
1076 B_RFGAIN_BND, 0x04);
1095 iqk_info->nb_txcfir[path] = 0x40000000;
1097 B_IQK_RES_TXCFIR, 0x5);
1100 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path,
1110 u8 group = 0x2;
1111 u32 a_mode_txgain = 0x64e2;
1112 u32 g_mode_txgain = 0x61e8;
1113 u32 attsmxr = 0x1;
1114 u32 itqt = 0x12;
1115 u32 tmp = 0x0;
1121 B_RFGAIN_BND, 0x08);
1128 B_RFGAIN_BND, 0x04);
1143 iqk_info->nb_txcfir[path] = tmp | 0x2;
1145 iqk_info->nb_txcfir[path] = 0x40000002;
1148 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path,
1158 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2);
1160 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0);
1162 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1);
1164 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
1170 u32 tmp = 0x0;
1171 u32 core_i = 0x0;
1172 u32 core_q = 0x0;
1175 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK][FineLOK] S%x, 0x58 = 0x%x\n",
1179 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, i = 0x%x\n", path, core_i);
1180 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, q = 0x%x\n", path, core_q);
1182 if (core_i < 0x2 || core_i > 0x1d || core_q < 0x2 || core_q > 0x1d)
1192 u32 rf0 = 0x0;
1193 u8 itqt = 0x12;
1199 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe5e0);
1200 itqt = 0x09;
1203 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe4e0);
1204 itqt = 0x12;
1214 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1);
1215 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, 0x1);
1216 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, 0x0);
1221 iqk_info->lok_cor_fail[0][path] = tmp;
1225 iqk_info->lok_fin_fail[0][path] = tmp;
1235 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f);
1237 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13);
1238 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001);
1240 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041);
1242 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303);
1243 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000);
1246 rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW, 0x00);
1247 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f);
1248 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0);
1249 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x1);
1250 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1);
1251 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0);
1252 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1253 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0);
1254 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x000);
1255 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200);
1256 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200);
1258 0x403e0 | iqk_info->syn1to2);
1262 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00);
1263 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f);
1264 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x7);
1265 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0);
1266 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1);
1267 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0);
1268 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x100);
1269 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200);
1270 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200);
1271 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x1);
1272 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x0);
1274 0x403e0 | iqk_info->syn1to2);
1284 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08);
1291 u32 tmp = 0x0;
1292 bool flag = 0x0;
1297 iqk_info->lok_cor_fail[0][path]);
1299 iqk_info->lok_fin_fail[0][path]);
1301 iqk_info->iqk_tx_fail[0][path]);
1303 iqk_info->iqk_rx_fail[0][path]);
1304 flag = iqk_info->lok_cor_fail[0][path];
1305 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(0) << (path * 4), flag);
1306 flag = iqk_info->lok_fin_fail[0][path];
1308 flag = iqk_info->iqk_tx_fail[0][path];
1310 flag = iqk_info->iqk_rx_fail[0][path];
1323 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, 0x0000000f << (path * 4));
1324 if (tmp != 0x0)
1326 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x00ff0000 << (path * 4),
1336 u8 ibias = 0x1;
1337 u8 i = 0;
1341 for (i = 0; i < 3; i++) {
1349 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path,
1352 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path,
1358 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path,
1361 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path,
1373 u32 reg_rf18 = 0x0, reg_35c = 0x0;
1374 u8 idx = 0;
1378 for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) {
1379 if (iqk_info->iqk_mcc_ch[idx][path] == 0) {
1387 idx = 0;
1391 reg_35c = rtw89_phy_read32_mask(rtwdev, 0x35c, 0x00000c00);
1398 "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path,
1400 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_bw[%x] = 0x%x\n",
1402 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_ch[%x] = 0x%x\n",
1407 iqk_info->iqk_band[path] == 0 ? "2G" :
1410 iqk_info->iqk_bw[path] == 0 ? "20M" :
1412 if (reg_35c == 0x01)
1413 iqk_info->syn1to2 = 0x1;
1415 iqk_info->syn1to2 = 0x0;
1418 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x000f << (path * 16),
1420 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x00f0 << (path * 16),
1422 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0xff00 << (path * 16),
1425 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x000000ff, RTW8852A_NCTL_VER);
1444 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000);
1447 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000);
1449 rtw89_phy_write32_mask(rtwdev, R_CFIR_MAP + (path << 8), MASKDWORD, 0xe4e4e4e4);
1452 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD, 0x00000002);
1453 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1454 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x0);
1455 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1457 rtw89_write_rf(rtwdev, path, RR_TXRSV, RR_TXRSV_GAPK, 0x0);
1458 rtw89_write_rf(rtwdev, path, RR_BIAS, RR_BIAS_GAPK, 0x0);
1459 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1489 B_COEF_SEL_IQC, path & 0x1);
1491 B_CFIR_LUT_G2, path & 0x1);
1498 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1499 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
1501 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a);
1502 rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, MASKDWORD, 0x00200000);
1503 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, MASKDWORD, 0x80000000);
1533 u8 phy_idx = 0x0;
1537 if (path == 0x0)
1552 u32 rf_reg5, rck_val = 0;
1560 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1563 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%x\n",
1567 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
1570 false, rtwdev, path, 0x1c, BIT(3));
1578 rtw89_write_rf(rtwdev, path, RR_RCKO, RR_RCKO_OFF, 0x4);
1580 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x1);
1581 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x0);
1586 "[RCK] RF 0x1b / 0x1c / 0x1d = 0x%x / 0x%x / 0x%x\n",
1608 iqk_info->iqk_times = 0x0;
1610 for (ch = 0; ch < RTW89_IQK_CHS_NR; ch++) {
1611 iqk_info->iqk_channel[ch] = 0x0;
1612 for (path = 0; path < RTW8852A_IQK_SS; path++) {
1617 iqk_info->iqk_mcc_ch[ch][path] = 0x0;
1618 iqk_info->iqk_table_idx[path] = 0x0;
1639 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
1641 _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
1642 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1648 _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
1649 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1672 #define RXDCK_VER_8852A 0xe
1691 B_P0_RXCK_VAL, 0x3);
1694 B_S0_RXDC2_AVG, 0x3);
1695 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3);
1699 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_CRXBB, 0x1);
1702 rtw89_write_rf(rtwdev, path, RR_DCK2, RR_DCK2_CYCLE, 0x3f);
1707 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
1708 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
1714 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
1731 "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, Cv: %d) ******\n",
1736 for (path = 0; path < 2; path++) {
1744 addr = 0x5818 + (path << 13);
1749 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1750 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0);
1757 addr = 0x5818 + (path << 13);
1765 #define RTW8852A_DPK_VER 0x10
1771 LBK_RXIQK = 0x06,
1772 SYNC = 0x10,
1773 MDPK_IDL = 0x11,
1774 MDPK_MPA = 0x12,
1775 GAIN_LOSS = 0x13,
1776 GAIN_CAL = 0x14,
1783 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
1785 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1797 for (i = 0; i < RTW8852A_DPK_KIP_REG_NUM; i++) {
1801 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n",
1811 for (i = 0; i < RTW8852A_DPK_KIP_REG_NUM; i++) {
1814 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Reload 0x%x = %x\n",
1824 u16 dpk_cmd = 0x0;
1828 dpk_cmd = (u16)((id << 8) | (0x19 + (path << 4)));
1835 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
1836 10, 20000, false, rtwdev, 0xbff8, MASKBYTE0);
1843 "[DPK] one-shot for %s = 0x%x (ret=%d)\n",
1844 id == 0x06 ? "LBK_RXIQK" :
1845 id == 0x10 ? "SYNC" :
1846 id == 0x11 ? "MDPK_IDL" :
1847 id == 0x12 ? "MDPK_MPA" :
1848 id == 0x13 ? "GAIN_LOSS" : "PWR_CAL",
1857 return 0;
1865 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3);
1886 dpk->bp[path][kidx].band == 0 ? "2G" :
1889 dpk->bp[path][kidx].bw == 0 ? "20M" :
1901 if (rtw89_phy_read32_mask(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL) == 0x0)
1909 if (rtw89_phy_read32_mask(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL) == 0x1)
1958 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
1959 rtw89_phy_write32_mask(rtwdev, R_KIP_CLK, MASKDWORD, 0x00093f3f);
1960 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a);
1961 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08);
1962 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG, B_DPK_CFG_IDX, 0x2);
1965 MASKDWORD, 0x003f2e2e);
1967 MASKDWORD, 0x005b5b5b);
1977 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000);
1978 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000);
1982 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), BIT(15), 0x1);
1998 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
1999 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1);
2000 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x2);
2003 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
2004 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
2005 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1);
2009 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTL, 0x1f);
2011 if (cur_rxbb <= 0xa)
2012 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x3);
2013 else if (cur_rxbb <= 0x10 && cur_rxbb >= 0xb)
2014 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x1);
2016 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x0);
2018 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11);
2022 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
2025 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0);
2026 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x0);
2027 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); /*POW IQKPLL*/
2041 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] thermal@DPK = 0x%x\n",
2048 u8 txagc_ori = 0x38;
2061 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x280b);
2062 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x0);
2063 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x4);
2064 rtw89_write_rf(rtwdev, path, RR_MIXER, RR_MIXER_GN, 0x0);
2066 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x282e);
2067 rtw89_write_rf(rtwdev, path, RR_BIASA2, RR_BIASA2_LB, 0x7);
2068 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW, 0x3);
2069 rtw89_write_rf(rtwdev, path, RR_RXA, RR_RXA_DPK, 0x3);
2071 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1);
2073 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0);
2076 "[DPK] RF 0x0/0x1/0x1a = 0x%x/ 0x%x/ 0x%x\n",
2088 rtw89_phy_write32_mask(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN, 0x1);
2098 B_LOAD_COEF_CFIR, 0x1);
2102 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), BIT(1), 0x1);
2105 "[DPK] PAD_man / TXBB_man = 0x%x / 0x%x\n", tmp_pad,
2119 B_RXIQC_BYPASS2, 0x1);
2121 B_RXIQC_BYPASS, 0x1);
2123 "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path,
2130 "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path,
2144 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2);
2146 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1);
2158 val = 0x80 + kidx * 0x20 + gain * 0x10;
2161 "[DPK] table select for Kidx[%d], Gain[%d] (0x%x)\n", kidx,
2184 dpk->corr_idx[path][0] = corr_idx;
2185 dpk->corr_val[path][0] = corr_val;
2187 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9);
2198 dpk->dc_i[path][0] = dc_i;
2199 dpk->dc_q[path][0] = dc_q;
2219 u16 dgain = 0x0;
2227 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x (%d)\n", dgain,
2237 if (dgain >= 0x783)
2238 offset = 0x6;
2239 else if (dgain <= 0x782 && dgain >= 0x551)
2240 offset = 0x3;
2241 else if (dgain <= 0x550 && dgain >= 0x3c4)
2242 offset = 0x0;
2243 else if (dgain <= 0x3c3 && dgain >= 0x2aa)
2245 else if (dgain <= 0x2a9 && dgain >= 0x1e3)
2247 else if (dgain <= 0x1e2 && dgain >= 0x156)
2249 else if (dgain <= 0x155)
2252 offset = 0x0;
2259 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6);
2260 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1);
2272 #define DPK_TXAGC_LOWER 0x2e
2273 #define DPK_TXAGC_UPPER 0x3f
2274 #define DPK_TXAGC_INVAL 0xff
2292 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp_txagc (GL=%d) = 0x%x\n",
2308 u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0;
2314 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00);
2319 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f);
2325 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n",
2330 for (i = 0; i < 32; i++) {
2333 "[DPK] PAS_Read[%02d]= 0x%08x\n", i,
2341 return 0;
2351 #define DPK_RXBB_UPPER 0x1f
2352 #define DPK_RXBB_LOWER 0
2355 u8 tmp_txagc, tmp_rxbb = 0, tmp_gl_idx = 0;
2356 u8 agc_cnt = 0;
2358 s8 offset = 0;
2359 u16 dgain = 0;
2398 "[DPK] Adjust RXBB (%d) = 0x%x\n", offset,
2400 if (offset != 0 || agc_cnt == 0) {
2419 if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true)) ||
2422 else if (tmp_gl_idx == 0)
2465 "[DPK] Txagc / RXBB for DPK = 0x%x / 0x%x\n", tmp_txagc,
2474 case 0:
2476 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x3);
2477 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x1);
2491 "[DPK] Wrong MDPD order!!(0x%x)\n", order);
2496 "[DPK] Set MDPD order to 0x%x for IDL\n", order);
2503 _dpk_set_mdpd_para(rtwdev, 0x0);
2514 u16 pwsf = 0x78;
2515 u8 gs = 0x5b;
2520 "[DPK] Fill txagc/ pwsf/ gs = 0x%x/ 0x%x/ 0x%x\n", txagc,
2525 0x3F << ((gain << 3) + (kidx << 4)), txagc);
2529 0x1FF << (gain << 4), pwsf);
2531 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
2536 MASKDWORD, 0x065b5b5b);
2554 for (idx = 0; idx < RTW89_DPK_BKUP_NUM; idx++) {
2575 u8 txagc = 0, kidx = dpk->cur_idx[path];
2617 u32 kip_bkup[RTW8852A_DPK_RF_PATH][RTW8852A_DPK_KIP_REG_NUM] = {{0}};
2623 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2629 if (!reloaded[path] && dpk->bp[path][0].ch != 0)
2635 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++)
2636 dpk->cur_idx[path] = 0;
2644 _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
2646 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2652 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
2658 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2667 _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
2669 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2675 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
2706 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2716 "[DPK] ****** DPK Start (Ver: 0x%x, Cv: %d, RF_para: %d) ******\n",
2736 MASKBYTE3, 0x6 | val);
2747 u8 trk_idx = 0, txagc_rf = 0;
2748 s8 txagc_bb = 0, txagc_bb_tp = 0, ini_diff = 0, txagc_ofst = 0;
2751 s8 delta_ther[2] = {0};
2753 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) {
2765 if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0)
2780 "[DPK_TRK] txagc_RF / track_idx = 0x%x / %d\n",
2793 "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n",
2806 BIT(15)) == 0x1)
2807 txagc_ofst = 0;
2809 if (txagc_rf != 0 && cur_ther != 0)
2813 B_P0_TXDPD) == 0x0) {
2814 pwsf[0] = dpk->bp[path][kidx].pwsf + txagc_bb_tp -
2821 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff +
2828 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2829 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2832 if (rtw89_phy_read32_mask(rtwdev, R_DPK_TRK, B_DPK_TRK_DIS) == 0x0 &&
2833 txagc_rf != 0) {
2835 "[DPK_TRK] New pwsf[0] / pwsf[1] = 0x%x / 0x%x\n",
2836 pwsf[0], pwsf[1]);
2839 0x000001FF, pwsf[0]);
2841 0x01FF0000, pwsf[1]);
2852 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1);
2854 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1);
2906 u32 __val = 0; \
2907 for (__i = 0; __i < 4; __i++) { \
2920 u8 thermal = 0xff;
2921 s8 thm_ofst[64] = {0};
2922 u32 tmp = 0;
2934 thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[0];
2935 thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[0];
2936 thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[0];
2937 thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[0];
2957 "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal);
2959 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0);
2960 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1);
2962 if (thermal == 0xff) {
2966 for (i = 0; i < 64; i += 4) {
2967 rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0);
2970 "[TSSI] write 0x%x val=0x%08x\n",
2971 0x5c00 + i, 0x0);
2979 i = 0;
2980 for (j = 0; j < 32; j++)
2991 for (i = 0; i < 64; i += 4) {
2996 "[TSSI] write 0x%x val=0x%08x\n",
2997 0x5c00 + i, tmp);
3000 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1);
3001 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0);
3007 "[TSSI] ch=%d thermal_pathB=0x%x\n", ch, thermal);
3009 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_DIS, 0x0);
3010 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_TRK, 0x1);
3012 if (thermal == 0xff) {
3016 for (i = 0; i < 64; i += 4) {
3017 rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, 0x0);
3020 "[TSSI] write 0x%x val=0x%08x\n",
3021 0x7c00 + i, 0x0);
3029 i = 0;
3030 for (j = 0; j < 32; j++)
3041 for (i = 0; i < 64; i += 4) {
3046 "[TSSI] write 0x%x val=0x%08x\n",
3047 0x7c00 + i, tmp);
3050 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x1);
3051 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x0);
3140 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
3166 return 0;
3179 return 0;
3192 return 0;
3253 return 0;
3260 return 0;
3277 return 0;
3286 s8 de_1st = 0;
3287 s8 de_2nd = 0;
3293 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
3323 s8 tde_1st = 0;
3324 s8 tde_2nd = 0;
3330 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3357 #define __DE_MASK 0x003ff000
3359 static const u32 r_cck_long[RF_PATH_NUM_8852A] = {0x5858, 0x7858};
3360 static const u32 r_cck_short[RF_PATH_NUM_8852A] = {0x5860, 0x7860};
3361 static const u32 r_mcs_20m[RF_PATH_NUM_8852A] = {0x5838, 0x7838};
3362 static const u32 r_mcs_40m[RF_PATH_NUM_8852A] = {0x5840, 0x7840};
3363 static const u32 r_mcs_80m[RF_PATH_NUM_8852A] = {0x5848, 0x7848};
3364 static const u32 r_mcs_80m_80m[RF_PATH_NUM_8852A] = {0x5850, 0x7850};
3365 static const u32 r_mcs_5m[RF_PATH_NUM_8852A] = {0x5828, 0x7828};
3366 static const u32 r_mcs_10m[RF_PATH_NUM_8852A] = {0x5830, 0x7830};
3376 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
3382 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
3389 "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n",
3399 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
3410 "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n",
3421 0x400, 0x40e, 0x41d, 0x427, 0x43c, 0x44c, 0x45c, 0x46c,
3422 0x400, 0x39d, 0x3ab, 0x3b8, 0x3c6, 0x3d4, 0x3e2, 0x3f1
3427 s32 delta_ther = 0, gain_offset_int, gain_offset_float;
3448 if (cur_ther == 0 || tssi_info->base_thermal[path] == 0)
3458 "[TSSI][TRK] base_thermal=%d gain_offset=0x%x path=%d\n",
3470 B_DPD_OFT_EN, 0x1);
3473 B_TXGAIN_SCALE_EN, 0x1);
3515 tssi_info->extra_ofst[RF_PATH_A] = 0;
3516 tssi_info->extra_ofst[RF_PATH_B] = 0;
3528 rtw8852a_bb_set_pmac_pkt_tx(rtwdev, enable, 20, 5000, 0, phy, chan);
3541 u8 phy_map = rtw89_btc_phymap(rtwdev, phy, 0, chanctx_idx);
3544 u32 i, tx_counter = 0;
3580 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, MASKHWORD) != 0xc000 &&
3581 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, MASKHWORD) != 0x0) {
3582 for (i = 0; i < 6; i++) {
3587 if (tssi_info->default_txagc_offset[RF_PATH_A] != 0x0)
3592 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, MASKHWORD) != 0xc000 &&
3593 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, MASKHWORD) != 0x0) {
3594 for (i = 0; i < 6; i++) {
3599 if (tssi_info->default_txagc_offset[RF_PATH_B] != 0x0)
3609 "[TSSI] Backup R_TXAGC_BB=0x%x R_TXAGC_BB_S1=0x%x\n",
3613 rtw8852a_bb_tx_mode_switch(rtwdev, phy, 0);
3623 for (path = 0; path < 2; path++)
3630 u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0, chanctx_idx);
3641 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3661 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3677 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3767 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x0);
3768 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x0);
3770 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x0);
3771 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x0);
3786 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x4);
3787 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x2);
3789 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x4);
3790 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x2);
3821 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, B_TXAGC_BB_OFT) != 0xc000 &&
3822 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, B_TXAGC_BB_OFT) != 0x0) {
3823 for (i = 0; i < 6; i++) {
3832 if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, B_TXAGC_BB_S1_OFT) != 0xc000 &&
3833 rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, B_TXAGC_BB_S1_OFT) != 0x0) {
3834 for (i = 0; i < 6; i++) {
3848 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
3849 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1);
3851 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x0);
3852 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x1);