Lines Matching refs:rtwdev
541 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
544 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
556 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
566 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
572 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
575 struct rtw89_efuse *efuse = &rtwdev->efuse;
582 rtw8852a_efuse_parsing_tssi(rtwdev, map);
584 switch (rtwdev->hci.type) {
592 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
597 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
599 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
601 u32 addr = rtwdev->chip->phycap_addr;
619 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
625 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
631 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
634 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
636 u32 addr = rtwdev->chip->phycap_addr;
642 rtw89_debug(rtwdev, RTW89_DBG_RFK,
651 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev)
658 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
662 rtw89_debug(rtwdev, RTW89_DBG_RFK,
670 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
672 rtw89_debug(rtwdev, RTW89_DBG_RFK,
679 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
682 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
684 u32 addr = rtwdev->chip->phycap_addr;
690 rtw89_debug(rtwdev, RTW89_DBG_RFK,
699 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev)
701 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
706 rtw89_debug(rtwdev, RTW89_DBG_RFK,
716 rtw89_debug(rtwdev, RTW89_DBG_RFK,
720 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
721 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
725 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
727 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map);
728 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
729 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
734 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev)
736 rtw8852a_thermal_trim(rtwdev);
737 rtw8852a_pa_bias_trim(rtwdev);
740 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev,
744 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
745 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
746 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
751 txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
755 txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
764 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
765 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
768 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
769 rtw89_write32(rtwdev, sub_carr, txsc20);
772 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
773 rtw89_write32(rtwdev, sub_carr, 0);
780 rtw89_write8_set(rtwdev, chk_rate,
783 rtw89_write8_clr(rtwdev, chk_rate,
797 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
810 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
813 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
815 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
821 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch,
826 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
828 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
835 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
866 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch,
874 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A);
876 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
880 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
885 if (!rtwdev->dbcc_en) {
886 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
888 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
892 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
897 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND,
900 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND,
905 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
909 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
911 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
915 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
920 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
926 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1,
929 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0,
934 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
936 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
938 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45,
940 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
942 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
944 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
945 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
946 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
949 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
951 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
953 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
954 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
956 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
958 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB,
960 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD,
962 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
967 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
973 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
975 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
981 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
982 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
986 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
987 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
991 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
992 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
996 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
997 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1001 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1002 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1006 rtw89_warn(rtwdev, "Fail to set ADC\n");
1009 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
1013 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1019 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1021 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1,
1023 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1027 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1029 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2,
1031 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1035 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1037 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1039 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1043 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
1045 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1047 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1051 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1053 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1056 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
1058 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1060 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1065 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1070 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A);
1071 if (!rtwdev->dbcc_en)
1072 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1074 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1078 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch)
1081 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1083 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1085 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0);
1086 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1088 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1090 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1093 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1095 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1097 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40);
1098 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1100 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1102 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1105 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1107 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1109 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740);
1110 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1112 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1114 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1117 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1119 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1121 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1126 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev,
1129 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1131 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1133 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1137 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev,
1141 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1145 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1150 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev,
1153 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1154 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1155 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1156 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1157 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1158 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1159 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1160 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1161 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1164 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1171 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1174 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev)
1176 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1177 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
1179 if (rtwdev->hal.cv <= CHIP_CCV) {
1180 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG);
1181 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000);
1182 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F);
1183 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF);
1184 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST);
1185 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1186 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1187 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME);
1189 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f);
1190 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c);
1191 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1192 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1);
1193 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK);
1194 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK);
1196 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1199 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev,
1202 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1203 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1204 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1205 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1206 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1210 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev,
1218 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel,
1222 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx);
1223 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1225 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1227 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1228 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx);
1230 rtw8852a_spur_elimination(rtwdev, chan->channel);
1231 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
1233 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1236 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev,
1241 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx);
1242 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx);
1245 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en)
1248 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1250 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1253 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1260 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0);
1261 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0);
1263 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1);
1264 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1);
1268 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1271 if (!rtwdev->dbcc_en) {
1272 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1273 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1276 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1278 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1282 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en)
1285 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1288 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1292 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1299 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en,
1301 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
1302 rtw8852a_dfs_en(rtwdev, false);
1303 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
1304 rtw8852a_adc_en(rtwdev, false);
1306 rtw8852a_bb_reset_en(rtwdev, phy_idx, false);
1308 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
1309 rtw8852a_adc_en(rtwdev, true);
1310 rtw8852a_dfs_en(rtwdev, true);
1311 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
1312 rtw8852a_bb_reset_en(rtwdev, phy_idx, true);
1313 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en);
1317 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev)
1319 struct rtw89_efuse *efuse = &rtwdev->efuse;
1328 rtwdev->fem.epa_2g = true;
1329 rtwdev->fem.elna_2g = true;
1335 rtwdev->fem.epa_5g = true;
1336 rtwdev->fem.elna_5g = true;
1343 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev)
1345 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1346 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1348 rtw8852a_rck(rtwdev);
1349 rtw8852a_dack(rtwdev, RTW89_CHANCTX_0);
1350 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true, RTW89_CHANCTX_0);
1353 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev,
1359 rtw8852a_rx_dck(rtwdev, phy_idx, true, chanctx_idx);
1360 rtw8852a_iqk(rtwdev, phy_idx, chanctx_idx);
1361 rtw8852a_tssi(rtwdev, phy_idx, chanctx_idx);
1362 rtw8852a_dpk(rtwdev, phy_idx, chanctx_idx);
1365 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev,
1369 rtw8852a_tssi_scan(rtwdev, phy_idx, chan);
1372 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev,
1376 rtw8852a_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx);
1379 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev)
1381 rtw8852a_dpk_track(rtwdev);
1382 rtw8852a_tssi_track(rtwdev);
1385 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1404 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1412 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1420 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n",
1424 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1425 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1427 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1428 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t);
1430 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1431 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t);
1432 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n",
1436 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev,
1448 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1450 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1453 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1454 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1457 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1460 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1461 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1464 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1468 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev,
1472 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1473 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1474 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1475 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1478 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1481 rtw8852a_set_txpwr_ref(rtwdev, phy_idx);
1485 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1489 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1493 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004);
1497 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1504 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
1512 rtw89_phy_write32(rtwdev, addr, val);
1516 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev,
1520 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
1522 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0,
1525 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0,
1529 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev,
1538 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1,
1540 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
1542 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1,
1544 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
1546 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
1548 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
1550 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
1551 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
1554 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
1559 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx);
1560 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
1562 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
1565 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
1566 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
1567 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
1568 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f,
1570 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
1571 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
1572 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1573 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
1574 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx);
1577 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
1589 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx, chan);
1592 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
1595 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
1596 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1597 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
1600 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
1605 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
1606 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1);
1607 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
1608 if (!rtwdev->dbcc_en) {
1610 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1612 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1615 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1617 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1620 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1622 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1625 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
1628 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK,
1630 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2,
1632 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK,
1634 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4,
1640 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1641 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1643 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
1644 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
1648 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
1653 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
1654 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
1655 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
1656 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
1657 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
1658 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
1659 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
1660 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
1663 static void rtw8852a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
1666 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852a_btc_preagc_en_defs_tbl :
1670 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1672 if (rtwdev->is_tssi_mode[rf_path]) {
1675 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
1678 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1679 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1680 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1684 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1687 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev)
1689 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
1690 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
1693 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
1694 md->md_v7.kt_ver = rtwdev->hal.cv;
1713 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
1714 rtwdev->btc.ant_type = md->md_v7.ant.type;
1716 md->md.rfe_type = rtwdev->efuse.rfe_type;
1717 md->md.cv = rtwdev->hal.cv;
1736 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
1737 rtwdev->btc.ant_type = md->md.ant.type;
1742 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1744 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000);
1745 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group);
1746 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val);
1747 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0);
1750 static void rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
1754 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1);
1755 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3);
1756 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1758 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0);
1759 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0);
1760 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
1761 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
1765 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev)
1767 struct rtw89_btc *btc = &rtwdev->btc;
1768 const struct rtw89_chip_info *chip = rtwdev->chip;
1775 rtw89_mac_coex_init(rtwdev, &coex_params);
1778 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1779 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1782 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0);
1783 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0);
1787 rtw8852a_set_trx_mask(rtwdev,
1789 rtw8852a_set_trx_mask(rtwdev,
1792 rtw8852a_set_trx_mask(rtwdev,
1795 rtw8852a_set_trx_mask(rtwdev,
1797 rtw8852a_set_trx_mask(rtwdev,
1802 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
1805 rtw89_write32_set(rtwdev,
1811 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
1830 rtw89_write32_set(rtwdev, reg, bitmap);
1832 rtw89_write32_clr(rtwdev, reg, bitmap);
1872 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
1883 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1885 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\
1887 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1892 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\
1893 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1905 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
1956 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
1958 struct rtw89_btc *btc = &rtwdev->btc;
1966 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH);
1970 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW);
1975 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1976 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1977 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1978 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1982 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
1984 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
1985 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
1986 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1);
1990 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
1993 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
1996 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1999 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
2008 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2009 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2010 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
2011 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2012 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2013 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2016 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2017 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2018 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
2019 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2020 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2021 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2026 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2028 struct rtw89_btc *btc = &rtwdev->btc;
2033 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
2037 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0);
2041 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
2046 rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2);
2049 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2064 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
2074 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2079 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);