Lines Matching defs:rtwdev
527 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
530 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
542 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
552 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
558 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
561 struct rtw89_efuse *efuse = &rtwdev->efuse;
568 rtw8852a_efuse_parsing_tssi(rtwdev, map);
570 switch (rtwdev->hci.type) {
578 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
583 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
585 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
587 u32 addr = rtwdev->chip->phycap_addr;
605 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
611 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
617 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
620 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
622 u32 addr = rtwdev->chip->phycap_addr;
628 rtw89_debug(rtwdev, RTW89_DBG_RFK,
637 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev)
644 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
648 rtw89_debug(rtwdev, RTW89_DBG_RFK,
656 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
658 rtw89_debug(rtwdev, RTW89_DBG_RFK,
665 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
668 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
670 u32 addr = rtwdev->chip->phycap_addr;
676 rtw89_debug(rtwdev, RTW89_DBG_RFK,
685 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev)
687 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
692 rtw89_debug(rtwdev, RTW89_DBG_RFK,
702 rtw89_debug(rtwdev, RTW89_DBG_RFK,
706 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
707 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
711 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
713 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map);
714 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
715 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
720 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev)
722 rtw8852a_thermal_trim(rtwdev);
723 rtw8852a_pa_bias_trim(rtwdev);
726 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev,
730 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
731 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
732 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
737 txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
741 txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
750 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
751 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
754 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
755 rtw89_write32(rtwdev, sub_carr, txsc20);
758 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
759 rtw89_write32(rtwdev, sub_carr, 0);
766 rtw89_write8_set(rtwdev, chk_rate,
769 rtw89_write8_clr(rtwdev, chk_rate,
783 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
796 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
799 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
801 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
807 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch,
812 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
814 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
821 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
852 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch,
860 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A);
862 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
866 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
871 if (!rtwdev->dbcc_en) {
872 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
874 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
878 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
883 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND,
886 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND,
891 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
895 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
897 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
901 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
906 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
912 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1,
915 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0,
920 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
922 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
924 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45,
926 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
928 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
930 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
931 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
932 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
935 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
937 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
939 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
940 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
942 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
944 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB,
946 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD,
948 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
953 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
959 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
961 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
967 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
968 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
972 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
973 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
977 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
978 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
982 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
983 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
987 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
988 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
992 rtw89_warn(rtwdev, "Fail to set ADC\n");
995 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
999 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1005 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1007 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1,
1009 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1013 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1015 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2,
1017 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1021 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1023 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1025 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1029 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
1031 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1033 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1037 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1039 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1042 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
1044 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1046 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1051 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1056 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A);
1057 if (!rtwdev->dbcc_en)
1058 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1060 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1064 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch)
1067 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1069 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1071 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0);
1072 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1074 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1076 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1079 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1081 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1083 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40);
1084 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1086 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1088 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1091 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1093 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1095 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740);
1096 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1098 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1100 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1103 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1105 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1107 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1112 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev,
1115 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1117 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1119 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1123 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev,
1127 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1131 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1136 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev,
1139 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1140 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1141 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1142 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1143 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1144 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1145 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1146 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1147 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1150 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1157 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1160 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev)
1162 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1163 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
1165 if (rtwdev->hal.cv <= CHIP_CCV) {
1166 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG);
1167 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000);
1168 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F);
1169 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF);
1170 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST);
1171 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1172 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1173 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME);
1175 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f);
1176 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c);
1177 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1178 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1);
1179 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK);
1180 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK);
1182 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1185 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev,
1188 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1189 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1190 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1191 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1192 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1196 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev,
1204 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel,
1208 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx);
1209 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1211 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1213 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1214 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx);
1216 rtw8852a_spur_elimination(rtwdev, chan->channel);
1217 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
1219 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1222 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev,
1227 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx);
1228 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx);
1231 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en)
1234 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1236 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1239 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1246 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0);
1247 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0);
1249 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1);
1250 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1);
1254 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1257 if (!rtwdev->dbcc_en) {
1258 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1259 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1262 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1264 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1268 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en)
1271 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1274 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1278 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1285 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en,
1287 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
1288 rtw8852a_dfs_en(rtwdev, false);
1289 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
1290 rtw8852a_adc_en(rtwdev, false);
1292 rtw8852a_bb_reset_en(rtwdev, phy_idx, false);
1294 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
1295 rtw8852a_adc_en(rtwdev, true);
1296 rtw8852a_dfs_en(rtwdev, true);
1297 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
1298 rtw8852a_bb_reset_en(rtwdev, phy_idx, true);
1299 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en);
1303 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev)
1305 struct rtw89_efuse *efuse = &rtwdev->efuse;
1314 rtwdev->fem.epa_2g = true;
1315 rtwdev->fem.elna_2g = true;
1321 rtwdev->fem.epa_5g = true;
1322 rtwdev->fem.elna_5g = true;
1329 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev)
1331 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1332 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1334 rtw8852a_rck(rtwdev);
1335 rtw8852a_dack(rtwdev);
1336 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true);
1339 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev)
1343 rtw8852a_rx_dck(rtwdev, phy_idx, true);
1344 rtw8852a_iqk(rtwdev, phy_idx);
1345 rtw8852a_tssi(rtwdev, phy_idx);
1346 rtw8852a_dpk(rtwdev, phy_idx);
1349 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev,
1352 rtw8852a_tssi_scan(rtwdev, phy_idx);
1355 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1357 rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1360 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev)
1362 rtw8852a_dpk_track(rtwdev);
1363 rtw8852a_tssi_track(rtwdev);
1366 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1385 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1393 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1401 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n",
1405 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1406 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1408 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1409 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t);
1411 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1412 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t);
1413 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n",
1417 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev,
1429 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1431 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1434 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1435 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1438 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1441 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1442 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1445 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1449 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev,
1453 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1454 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1455 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1456 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1459 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1462 rtw8852a_set_txpwr_ref(rtwdev, phy_idx);
1466 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1470 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1474 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004);
1478 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1485 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
1493 rtw89_phy_write32(rtwdev, addr, val);
1497 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev,
1501 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
1503 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0,
1506 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0,
1510 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev,
1519 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1,
1521 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
1523 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1,
1525 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
1527 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
1529 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
1531 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
1532 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
1535 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
1539 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1542 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx);
1543 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
1545 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
1548 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
1549 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
1550 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
1551 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f,
1553 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
1554 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
1555 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1556 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
1557 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx);
1560 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
1572 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx);
1575 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
1578 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
1579 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1580 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
1583 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
1588 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
1589 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1);
1590 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
1591 if (!rtwdev->dbcc_en) {
1593 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1595 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1598 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1600 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1603 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1605 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1608 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
1611 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK,
1613 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2,
1615 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK,
1617 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4,
1623 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1624 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1626 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
1627 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
1631 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
1636 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
1637 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
1638 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
1639 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
1640 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
1641 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
1642 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
1643 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
1646 static void rtw8852a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
1649 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852a_btc_preagc_en_defs_tbl :
1653 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1655 if (rtwdev->is_tssi_mode[rf_path]) {
1658 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
1661 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1662 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1663 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1667 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1670 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev)
1672 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
1673 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
1676 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
1677 md->md_v7.kt_ver = rtwdev->hal.cv;
1696 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
1697 rtwdev->btc.ant_type = md->md_v7.ant.type;
1699 md->md.rfe_type = rtwdev->efuse.rfe_type;
1700 md->md.cv = rtwdev->hal.cv;
1719 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
1720 rtwdev->btc.ant_type = md->md.ant.type;
1725 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1727 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000);
1728 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group);
1729 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val);
1730 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0);
1733 static void rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
1737 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1);
1738 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3);
1739 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1741 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0);
1742 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0);
1743 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
1744 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
1748 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev)
1750 struct rtw89_btc *btc = &rtwdev->btc;
1751 const struct rtw89_chip_info *chip = rtwdev->chip;
1758 rtw89_mac_coex_init(rtwdev, &coex_params);
1761 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1762 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1765 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0);
1766 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0);
1770 rtw8852a_set_trx_mask(rtwdev,
1772 rtw8852a_set_trx_mask(rtwdev,
1775 rtw8852a_set_trx_mask(rtwdev,
1778 rtw8852a_set_trx_mask(rtwdev,
1780 rtw8852a_set_trx_mask(rtwdev,
1785 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
1788 rtw89_write32_set(rtwdev,
1794 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
1813 rtw89_write32_set(rtwdev, reg, bitmap);
1815 rtw89_write32_clr(rtwdev, reg, bitmap);
1855 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
1866 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1868 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\
1870 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1875 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\
1876 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1888 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
1939 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
1941 struct rtw89_btc *btc = &rtwdev->btc;
1949 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH);
1953 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW);
1958 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1959 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1960 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1961 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1965 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
1967 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
1968 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
1969 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1);
1973 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
1976 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
1979 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1982 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
1991 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
1992 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
1993 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
1994 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
1995 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1996 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1999 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2000 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2001 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
2002 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2003 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2004 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2009 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2011 struct rtw89_btc *btc = &rtwdev->btc;
2016 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
2020 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0);
2024 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
2029 rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2);
2032 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2047 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
2055 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2060 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);