Lines Matching refs:rtwdev

281 static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev)
287 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
289 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
290 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
291 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
292 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
295 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
299 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
300 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
303 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
307 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
308 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
309 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
310 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
312 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
313 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
315 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
319 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
323 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
326 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
330 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
334 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
337 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
340 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
343 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
346 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH);
350 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
351 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
352 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
356 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
357 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
358 rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN,
361 if (rtwdev->hal.cv == CHIP_CAV) {
362 ret = rtw89_read_efuse_ver(rtwdev, &val8);
364 rtwdev->hal.cv = val8;
367 rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
369 if (rtwdev->hal.cv != CHIP_CAV) {
370 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
371 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
374 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
381 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
387 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
393 static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev)
395 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR);
396 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM);
397 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM);
398 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM);
401 static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev)
406 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
410 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
413 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
416 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
419 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
423 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
426 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
430 rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
432 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
433 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
434 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
436 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
439 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
443 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
445 if (rtwdev->hal.cv == CHIP_CAV) {
446 rtw8851b_patch_swr_pfm2pwm(rtwdev);
448 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
449 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
452 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
465 static void rtw8851b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
468 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
479 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
489 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
505 static void rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
508 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
530 static int rtw8851b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
533 struct rtw89_efuse *efuse = &rtwdev->efuse;
540 rtw8851b_efuse_parsing_tssi(rtwdev, map);
541 rtw8851b_efuse_parsing_gain_offset(rtwdev, map);
543 switch (rtwdev->hci.type) {
551 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
556 static void rtw8851b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
558 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
560 u32 addr = rtwdev->chip->phycap_addr;
578 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
584 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
590 static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
593 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
595 u32 addr = rtwdev->chip->phycap_addr;
601 rtw89_debug(rtwdev, RTW89_DBG_RFK,
610 static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev)
617 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
621 rtw89_debug(rtwdev, RTW89_DBG_RFK,
629 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
631 rtw89_debug(rtwdev, RTW89_DBG_RFK,
638 static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
641 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
643 u32 addr = rtwdev->chip->phycap_addr;
649 rtw89_debug(rtwdev, RTW89_DBG_RFK,
658 static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev)
660 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
665 rtw89_debug(rtwdev, RTW89_DBG_RFK,
675 rtw89_debug(rtwdev, RTW89_DBG_RFK,
679 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
680 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
684 static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
689 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
690 u32 phycap_addr = rtwdev->chip->phycap_addr;
708 static int rtw8851b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
710 rtw8851b_phycap_parsing_tssi(rtwdev, phycap_map);
711 rtw8851b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
712 rtw8851b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
713 rtw8851b_phycap_parsing_gain_comp(rtwdev, phycap_map);
718 static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv,
730 rtw89_phy_write32_mask(rtwdev, addr, mask, RF_PATH_A);
731 rtw89_phy_write32_mask(rtwdev, R_RFE_INV0, BIT(gpio_idx), inv);
737 rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel);
740 static void rtw8851b_set_mac_gpio(struct rtw89_dev *rtwdev, u8 func)
758 rtw89_warn(rtwdev, "undefined gpio func %d\n", func);
762 rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data);
765 static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev)
767 u8 rfe_type = rtwdev->efuse.rfe_type;
773 rtw8851b_set_bb_gpio(rtwdev, 16, true, RFE_SEL0_SRC_ANTSEL_0);
774 rtw8851b_set_bb_gpio(rtwdev, 17, false, RFE_SEL0_SRC_ANTSEL_0);
776 rtw8851b_set_mac_gpio(rtwdev, 16);
777 rtw8851b_set_mac_gpio(rtwdev, 17);
781 static void rtw8851b_power_trim(struct rtw89_dev *rtwdev)
783 rtw8851b_thermal_trim(rtwdev);
784 rtw8851b_pa_bias_trim(rtwdev);
787 static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev,
791 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
792 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
793 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
798 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
801 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
809 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
810 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
813 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
814 rtw89_write32(rtwdev, sub_carr, txsc20);
817 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
818 rtw89_write32(rtwdev, sub_carr, 0);
825 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
826 rtw89_write8_set(rtwdev, chk_rate,
829 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
830 rtw89_write8_clr(rtwdev, chk_rate,
845 static void rtw8851b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
849 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
851 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
913 static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev,
917 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
932 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
943 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
947 static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev,
953 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
966 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
979 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
986 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
990 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
995 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
1001 void rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
1003 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1011 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
1012 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
1018 rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
1019 rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
1025 rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
1026 rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
1029 static void rtw8851b_ctrl_ch(struct rtw89_dev *rtwdev,
1039 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1042 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1046 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
1053 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
1054 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
1055 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
1056 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
1057 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
1058 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
1059 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
1060 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
1062 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
1063 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
1064 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
1065 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
1066 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
1067 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
1068 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
1069 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
1072 rtw8851b_set_gain_error(rtwdev, subband, RF_PATH_A);
1073 rtw8851b_set_gain_offset(rtwdev, subband, phy_idx);
1074 rtw8851b_set_rxsc_rpl_comp(rtwdev, subband);
1077 static void rtw8851b_bw_setting(struct rtw89_dev *rtwdev, u8 bw)
1079 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8);
1080 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2);
1081 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2);
1082 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0x4);
1083 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0xf);
1084 rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_LP, 0xa);
1085 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92);
1089 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1090 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x0);
1091 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x1);
1094 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1095 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x1);
1096 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1099 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1100 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1101 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1104 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1105 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1106 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1109 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0);
1110 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1111 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1114 rtw89_warn(rtwdev, "Fail to set ADC\n");
1118 static void rtw8851b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1123 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1124 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
1125 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1128 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1129 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
1130 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1133 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1134 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1135 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1138 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
1139 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1140 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1144 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1146 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1150 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
1151 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1152 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1156 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1160 rtw8851b_bw_setting(rtwdev, bw);
1163 static void rtw8851b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
1166 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1167 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1169 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1171 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1172 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1174 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1178 static u32 rtw8851b_spur_freq(struct rtw89_dev *rtwdev,
1202 static void rtw8851b_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1209 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1211 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN,
1220 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX,
1222 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
1234 static void rtw8851b_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1244 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1246 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1248 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1279 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1281 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1283 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1285 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1287 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1290 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1292 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1294 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1296 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1298 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1303 static void rtw8851b_set_cfr(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan)
1308 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1310 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1312 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1314 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1317 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1319 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1321 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1323 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1328 static void rtw8851b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1353 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
1354 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1360 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1361 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1362 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
1363 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
1365 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1366 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1367 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
1368 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
1370 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1374 static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1376 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1378 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1379 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1380 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1381 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1384 static void rtw8851b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1388 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1390 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1392 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
1393 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1395 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
1396 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1397 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1400 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1404 static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev,
1407 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1409 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1410 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1411 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1413 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1417 void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1431 rtw89_phy_write32_mask(rtwdev, R_P0_TRSW,
1435 static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev)
1437 rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);
1438 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X);
1439 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2);
1440 rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777);
1441 rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777);
1443 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1444 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1445 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1446 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1448 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1449 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1450 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1451 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1452 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1453 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1454 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1455 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1458 static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1465 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1468 static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev)
1470 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1472 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1474 rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1475 rtw8851b_bb_gpio_init(rtwdev);
1477 rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE);
1478 rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN);
1482 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
1484 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
1487 static void rtw8851b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1495 rtw8851b_ctrl_sco_cck(rtwdev, chan->primary_channel);
1497 rtw8851b_ctrl_ch(rtwdev, chan, phy_idx);
1498 rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1499 rtw8851b_ctrl_cck_en(rtwdev, cck_en);
1500 rtw8851b_set_nbi_tone_idx(rtwdev, chan);
1501 rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx);
1504 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1506 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1508 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1509 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1510 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1512 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1515 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1516 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx);
1517 rtw8851b_5m_mask(rtwdev, chan, phy_idx);
1518 rtw8851b_set_cfr(rtwdev, chan);
1519 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1522 static void rtw8851b_set_channel(struct rtw89_dev *rtwdev,
1527 rtw8851b_set_channel_mac(rtwdev, chan, mac_idx);
1528 rtw8851b_set_channel_bb(rtwdev, chan, phy_idx);
1529 rtw8851b_set_channel_rf(rtwdev, chan, phy_idx);
1532 static void rtw8851b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1536 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0);
1537 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x0);
1539 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1);
1540 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x1);
1544 static void rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1547 rtw8851b_tssi_cont_en(rtwdev, en, RF_PATH_A);
1550 static void rtw8851b_adc_en(struct rtw89_dev *rtwdev, bool en)
1553 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
1555 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
1558 static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1565 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1566 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
1567 rtw8851b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
1568 rtw8851b_adc_en(rtwdev, false);
1570 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1572 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
1573 rtw8851b_adc_en(rtwdev, true);
1574 rtw8851b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
1575 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1576 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1580 static void rtw8851b_rfk_init(struct rtw89_dev *rtwdev)
1582 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1583 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1584 rtw8851b_lck_init(rtwdev);
1586 rtw8851b_dpk_init(rtwdev);
1587 rtw8851b_aack(rtwdev);
1588 rtw8851b_rck(rtwdev);
1589 rtw8851b_dack(rtwdev);
1590 rtw8851b_rx_dck(rtwdev, RTW89_PHY_0, RTW89_CHANCTX_0);
1593 static void rtw8851b_rfk_channel(struct rtw89_dev *rtwdev,
1599 rtw8851b_rx_dck(rtwdev, phy_idx, chanctx_idx);
1600 rtw8851b_iqk(rtwdev, phy_idx, chanctx_idx);
1601 rtw8851b_tssi(rtwdev, phy_idx, true, chanctx_idx);
1602 rtw8851b_dpk(rtwdev, phy_idx, chanctx_idx);
1605 static void rtw8851b_rfk_band_changed(struct rtw89_dev *rtwdev,
1609 rtw8851b_tssi_scan(rtwdev, phy_idx, chan);
1612 static void rtw8851b_rfk_scan(struct rtw89_dev *rtwdev,
1616 rtw8851b_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx,
1620 static void rtw8851b_rfk_track(struct rtw89_dev *rtwdev)
1622 rtw8851b_dpk_track(rtwdev);
1623 rtw8851b_lck_track(rtwdev);
1626 static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1645 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1654 static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev,
1666 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1668 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1671 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1672 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1675 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1678 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1679 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1682 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1686 static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1719 rtw89_warn(rtwdev,
1731 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1733 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
1743 static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev,
1747 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
1749 u8 regd = rtw89_regd_get(rtwdev, band);
1754 rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1756 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
1760 static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev,
1764 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1765 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1766 rtw8851b_set_tx_shape(rtwdev, chan, phy_idx);
1767 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1768 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1771 static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1774 rtw8851b_set_txpwr_ref(rtwdev, phy_idx);
1778 void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1784 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1788 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1789 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1791 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1792 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1795 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1796 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
1800 rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1804 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1808 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1812 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1816 rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1822 static void rtw8851b_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
1825 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1827 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8851b_btc_preagc_en_defs_tbl :
1832 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1834 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1837 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1839 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1845 static void rtw8851b_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
1848 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1851 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1853 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1855 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1857 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1859 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1860 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
1861 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x1);
1862 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1864 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
1866 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1868 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1871 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1873 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1876 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1878 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1881 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
1882 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1883 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1884 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1886 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1890 static void rtw8851b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
1893 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1897 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
1898 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
1899 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
1900 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1901 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1902 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1903 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1904 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1907 rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
1911 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1912 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1916 static void rtw8851b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
1918 rtw8851b_bb_ctrl_rx_path(rtwdev, RF_A);
1920 if (rtwdev->hal.rx_nss == 1) {
1921 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1922 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1923 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1924 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1927 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1930 static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1932 if (rtwdev->is_tssi_mode[rf_path]) {
1935 return rtw89_phy_read32_mask(rtwdev, addr, B_TSSI_THER);
1938 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1939 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1940 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1944 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1947 static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev)
1949 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
1950 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
1953 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
1954 md->md_v7.kt_ver = rtwdev->hal.cv;
1958 md->md_v7.kt_ver_adie = rtwdev->hal.acv;
1986 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
1987 rtwdev->btc.ant_type = md->md_v7.ant.type;
1989 md->md.rfe_type = rtwdev->efuse.rfe_type;
1990 md->md.cv = rtwdev->hal.cv;
1994 md->md.kt_ver_adie = rtwdev->hal.acv;
2022 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
2023 rtwdev->btc.ant_type = md->md.ant.type;
2028 void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2033 if (rtwdev->btc.ant_type == BTC_ANT_SHARED) /* 1-Ant */
2036 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2037 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2040 static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev)
2046 const struct rtw89_chip_info *chip = rtwdev->chip;
2047 struct rtw89_btc *btc = &rtwdev->btc;
2053 rtw89_mac_coex_init(rtwdev, &coex_params);
2056 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
2057 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
2078 rtw89_write_rf(rtwdev, path, RR_WLSEL, RFREG_MASK, 0x0);
2081 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17));
2084 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff);
2087 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df);
2093 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f);
2095 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff);
2098 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0);
2102 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
2105 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
2111 void rtw8851b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2134 rtw89_write32_set(rtwdev, reg, bitmap);
2136 rtw89_write32_clr(rtwdev, reg, bitmap);
2161 rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2174 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2207 s8 rtw8851b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2216 void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2221 static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2223 struct rtw89_btc *btc = &rtwdev->btc;
2225 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000);
2226 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWA, RFREG_MASK, 0x1);
2227 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110);
2231 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c);
2233 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208);
2235 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x0);
2243 static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2249 struct rtw89_btc *btc = &rtwdev->btc;
2280 rtw89_write_rf(rtwdev, btc->btg_pos, rf->addr, LNA2_51B_MA, val);
2284 static void rtw8851b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2295 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band);
2300 static void rtw8851b_query_ppdu(struct rtw89_dev *rtwdev,
2310 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2315 rtw8851b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2318 static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2322 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2324 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2325 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2326 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2328 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
2333 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
2338 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
2343 static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2349 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2350 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2353 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
2357 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
2362 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
2366 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,