Lines Matching refs:phy_idx
949 enum rtw89_phy_idx phy_idx)
986 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
990 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
1031 enum rtw89_phy_idx phy_idx)
1040 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
1043 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
1046 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
1073 rtw8851b_set_gain_offset(rtwdev, subband, phy_idx);
1119 enum rtw89_phy_idx phy_idx)
1123 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1124 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
1125 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1128 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1129 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
1130 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1133 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1134 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1135 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1138 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
1139 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1141 pri_ch, phy_idx);
1150 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
1151 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1153 pri_ch, phy_idx);
1204 enum rtw89_phy_idx phy_idx)
1212 0, phy_idx);
1221 csi_tone_idx, phy_idx);
1222 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
1329 enum rtw89_phy_idx phy_idx)
1355 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
1371 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
1374 static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1376 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1378 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1379 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1380 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1381 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1385 enum rtw89_phy_idx phy_idx, bool en)
1389 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1390 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1398 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1400 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1405 enum rtw89_phy_idx phy_idx)
1410 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1459 enum rtw89_phy_idx phy_idx)
1465 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1488 enum rtw89_phy_idx phy_idx)
1497 rtw8851b_ctrl_ch(rtwdev, chan, phy_idx);
1498 rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1501 rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx);
1517 rtw8851b_5m_mask(rtwdev, chan, phy_idx);
1519 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1525 enum rtw89_phy_idx phy_idx)
1528 rtw8851b_set_channel_bb(rtwdev, chan, phy_idx);
1529 rtw8851b_set_channel_rf(rtwdev, chan, phy_idx);
1545 u8 phy_idx)
1562 enum rtw89_phy_idx phy_idx)
1570 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1575 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1597 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
1599 rtw8851b_rx_dck(rtwdev, phy_idx, chanctx_idx);
1600 rtw8851b_iqk(rtwdev, phy_idx, chanctx_idx);
1601 rtw8851b_tssi(rtwdev, phy_idx, true, chanctx_idx);
1602 rtw8851b_dpk(rtwdev, phy_idx, chanctx_idx);
1606 enum rtw89_phy_idx phy_idx,
1609 rtw8851b_tssi_scan(rtwdev, phy_idx, chan);
1616 rtw8851b_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx,
1627 enum rtw89_phy_idx phy_idx, s16 ref)
1655 enum rtw89_phy_idx phy_idx)
1668 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1672 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1676 phy_idx);
1679 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1683 phy_idx);
1689 enum rtw89_phy_idx phy_idx)
1734 phy_idx);
1745 enum rtw89_phy_idx phy_idx)
1754 rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1762 enum rtw89_phy_idx phy_idx)
1764 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1765 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1766 rtw8851b_set_tx_shape(rtwdev, chan, phy_idx);
1767 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1768 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1772 enum rtw89_phy_idx phy_idx)
1774 rtw8851b_set_txpwr_ref(rtwdev, phy_idx);
1800 rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1804 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1808 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1812 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1816 rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1823 enum rtw89_phy_idx phy_idx)
1846 enum rtw89_phy_idx phy_idx)