Lines Matching refs:gain

508 	struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
512 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
515 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
518 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
521 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
524 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
527 	gain->offset_valid = valid;
689 	struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
702 						    &gain->comp[path][i]);
705 	gain->comp_valid = valid;
917 	const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
931 		val = gain->lna_gain[gain_band][path][i];
942 		val = gain->tia_gain[gain_band][path][i];
1003 	const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1007 	val = u32_encode_bits(gain->rpl_ofst_20[band][RF_PATH_A], B_P0_RPL1_20_MASK) |
1008 	      u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][0], B_P0_RPL1_40_MASK) |
1009 	      u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][1], B_P0_RPL1_41_MASK);
1014 	val = u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][2], B_P0_RTL2_42_MASK) |
1015 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][0], B_P0_RTL2_80_MASK) |
1016 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][1], B_P0_RTL2_81_MASK) |
1017 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][10], B_P0_RTL2_8A_MASK);
1021 	val = u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][2], B_P0_RTL3_82_MASK) |
1022 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][3], B_P0_RTL3_83_MASK) |
1023 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][4], B_P0_RTL3_84_MASK) |
1024 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][9], B_P0_RTL3_89_MASK);
1470 	struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1481 	gain->offset_base[RTW89_PHY_0] =
1483 	gain->rssi_base[RTW89_PHY_0] =