Lines Matching +full:106 +full:- +full:db
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2022-2023 Realtek Corporation
227 {255, 0, 0, 7}, /* 0 -> original */
228 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
229 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
230 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
231 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
232 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
239 {255, 0, 0, 7}, /* 0 -> original */
240 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
241 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
242 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
243 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
244 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
352 if (rtwdev->hal.cv == CHIP_CAV) {
355 rtwdev->hal.cv = val8;
360 if (rtwdev->hal.cv != CHIP_CAV) {
436 if (rtwdev->hal.cv == CHIP_CAV) {
451 ether_addr_copy(efuse->addr, map->e.mac_addr);
452 efuse->rfe_type = map->rfe_type;
453 efuse->xtal_cap = map->xtal_k;
459 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
460 struct rtw8851b_tssi_offset *ofst[] = {&map->path_a_tssi};
463 tssi->thermal[RF_PATH_A] = map->path_a_therm;
466 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
467 sizeof(ofst[i]->cck_tssi));
472 i, j, tssi->tssi_cck[i][j]);
474 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
475 sizeof(ofst[i]->bw40_tssi));
476 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
477 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
482 i, j, tssi->tssi_mcs[i][j]);
499 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
502 valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
503 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
505 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
506 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
508 valid |= _decode_efuse_gain(map->rx_gain_5g_low,
509 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
511 valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
512 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
514 valid |= _decode_efuse_gain(map->rx_gain_5g_high,
515 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
518 gain->offset_valid = valid;
524 struct rtw89_efuse *efuse = &rtwdev->efuse;
529 efuse->country_code[0] = map->country_code[0];
530 efuse->country_code[1] = map->country_code[1];
534 switch (rtwdev->hci.type) {
539 return -EOPNOTSUPP;
542 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
549 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
551 u32 addr = rtwdev->chip->phycap_addr;
559 ofst = tssi_trim_addr[i] - addr - j;
560 tssi->tssi_trim[i][j] = phycap_map[ofst];
568 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
577 i, j, tssi->tssi_trim[i][j],
578 tssi_trim_addr[i] - j);
584 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
586 u32 addr = rtwdev->chip->phycap_addr;
590 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
594 i, info->thermal_trim[i]);
596 if (info->thermal_trim[i] != 0xff)
597 info->pg_thermal_trim = true;
608 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
611 if (!info->pg_thermal_trim) {
619 val = __thm_setting(info->thermal_trim[i]);
632 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
634 u32 addr = rtwdev->chip->phycap_addr;
638 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
642 i, info->pa_bias_trim[i]);
644 if (info->pa_bias_trim[i] != 0xff)
645 info->pg_pa_bias_trim = true;
651 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
655 if (!info->pg_pa_bias_trim) {
663 pabias_2g = u8_get_bits(info->pa_bias_trim[i], GENMASK(3, 0));
664 pabias_5g = u8_get_bits(info->pa_bias_trim[i], GENMASK(7, 4));
680 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
681 u32 phycap_addr = rtwdev->chip->phycap_addr;
691 data = phycap_map[comp_addrs[path][i] - phycap_addr];
693 &gain->comp[path][i]);
696 gain->comp_valid = valid;
717 /* 2 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 2 bits */
724 /* 4 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 4 bits */
753 rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data);
758 u8 rfe_type = rtwdev->efuse.rfe_type;
787 switch (chan->band_width) {
798 switch (chan->band_width) {
815 if (chan->channel > 14) {
838 u8 ch_element = primary_ch - 1;
855 return 106;
908 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
922 val = gain->lna_gain[gain_band][path][i];
933 val = gain->tia_gain[gain_band][path][i];
944 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
951 if (!efuse_gain->comp_valid)
955 tmp = efuse_gain->comp[path][subband];
961 if (!efuse_gain->offset_valid)
966 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
968 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
972 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
973 offset_cck = -efuse_gain->offset[RF_PATH_A][0];
975 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
979 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
984 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
994 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
998 val = u32_encode_bits(gain->rpl_ofst_20[band][RF_PATH_A], B_P0_RPL1_20_MASK) |
999 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][0], B_P0_RPL1_40_MASK) |
1000 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][1], B_P0_RPL1_41_MASK);
1005 val = u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][2], B_P0_RTL2_42_MASK) |
1006 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][0], B_P0_RTL2_80_MASK) |
1007 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][1], B_P0_RTL2_81_MASK) |
1008 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][10], B_P0_RTL2_8A_MASK);
1012 val = u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][2], B_P0_RTL3_82_MASK) |
1013 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][3], B_P0_RTL3_83_MASK) |
1014 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][4], B_P0_RTL3_84_MASK) |
1015 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][9], B_P0_RTL3_89_MASK);
1024 u8 subband = chan->subband_type;
1025 u8 central_ch = chan->channel;
1039 if (chan->band_type == RTW89_BAND_6G)
1172 u8 center_chan = chan->channel;
1174 switch (chan->band_type) {
1207 freq_diff = (spur_freq - chan->freq) * 1000000;
1237 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1238 nbi->notch1_en.mask, 0);
1239 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1240 nbi->notch2_en.mask, 0);
1244 fc = chan->freq;
1245 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1246 fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1248 chan->channel < chan->primary_channel) ||
1250 chan->channel > chan->primary_channel))
1254 freq_diff = (spur_freq - fc) * 1000000;
1258 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1261 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1269 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1270 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1271 nbi->notch2_idx.mask, nbi_tone_idx);
1272 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1273 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx);
1274 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1275 nbi->notch2_en.mask, 0);
1276 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1277 nbi->notch2_en.mask, 1);
1278 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1279 nbi->notch1_en.mask, 0);
1281 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1282 nbi->notch1_idx.mask, nbi_tone_idx);
1283 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1284 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx);
1285 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1286 nbi->notch1_en.mask, 0);
1287 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1288 nbi->notch1_en.mask, 1);
1289 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1290 nbi->notch2_en.mask, 0);
1296 if (chan->band_type == RTW89_BAND_2G &&
1297 chan->band_width == RTW89_CHANNEL_WIDTH_20 &&
1298 (chan->channel == 1 || chan->channel == 13)) {
1322 u8 pri_ch = chan->pri_ch_idx;
1326 switch (chan->band_width) {
1461 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1472 gain->offset_base[RTW89_PHY_0] =
1474 gain->rssi_base[RTW89_PHY_0] =
1481 u8 band = chan->band_type, chan_idx;
1482 bool cck_en = chan->channel <= 14;
1483 u8 pri_ch_idx = chan->pri_ch_idx;
1486 rtw8851b_ctrl_sco_cck(rtwdev, chan->primary_channel);
1489 rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1494 if (chan->band_type == RTW89_BAND_5G) {
1506 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1556 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1561 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1566 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1567 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1573 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1574 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1629 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1698 u8 ch = chan->channel;
1732 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
1733 u8 band = chan->band_type;
1735 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd];
1736 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd];
1768 if (pw_ofst < -16 || pw_ofst > 15) {
1779 pw_ofst = max_t(s8, pw_ofst - 3, -16);
1816 if (chan->band_type == RTW89_BAND_2G) {
1855 if (chan->band_type == RTW89_BAND_2G) {
1892 rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
1905 if (rtwdev->hal.rx_nss == 1) {
1917 if (rtwdev->is_tssi_mode[rf_path]) {
1934 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
1935 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
1937 if (ver->fcxinit == 7) {
1938 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
1939 md->md_v7.kt_ver = rtwdev->hal.cv;
1940 md->md_v7.bt_solo = 0;
1941 md->md_v7.switch_type = BTC_SWITCH_INTERNAL;
1942 md->md_v7.ant.isolation = 10;
1943 md->md_v7.kt_ver_adie = rtwdev->hal.acv;
1945 if (md->md_v7.rfe_type == 0)
1948 /* rfe_type 3*n+1: 1-Ant(shared),
1949 * 3*n+2: 2-Ant+Div(non-shared),
1950 * 3*n+3: 2-Ant+no-Div(non-shared)
1952 md->md_v7.ant.num = (md->md_v7.rfe_type % 3 == 1) ? 1 : 2;
1953 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */
1954 md->md_v7.ant.single_pos = RF_PATH_A;
1955 md->md_v7.ant.btg_pos = RF_PATH_A;
1956 md->md_v7.ant.stream_cnt = 1;
1958 if (md->md_v7.ant.num == 1) {
1959 md->md_v7.ant.type = BTC_ANT_SHARED;
1960 md->md_v7.bt_pos = BTC_BT_BTG;
1961 md->md_v7.wa_type = 1;
1962 md->md_v7.ant.diversity = 0;
1964 md->md_v7.ant.type = BTC_ANT_DEDICATED;
1965 md->md_v7.bt_pos = BTC_BT_ALONE;
1966 md->md_v7.switch_type = BTC_SWITCH_EXTERNAL;
1967 md->md_v7.wa_type = 0;
1968 if (md->md_v7.rfe_type % 3 == 2)
1969 md->md_v7.ant.diversity = 1;
1971 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
1972 rtwdev->btc.ant_type = md->md_v7.ant.type;
1974 md->md.rfe_type = rtwdev->efuse.rfe_type;
1975 md->md.cv = rtwdev->hal.cv;
1976 md->md.bt_solo = 0;
1977 md->md.switch_type = BTC_SWITCH_INTERNAL;
1978 md->md.ant.isolation = 10;
1979 md->md.kt_ver_adie = rtwdev->hal.acv;
1981 if (md->md.rfe_type == 0)
1984 /* rfe_type 3*n+1: 1-Ant(shared),
1985 * 3*n+2: 2-Ant+Div(non-shared),
1986 * 3*n+3: 2-Ant+no-Div(non-shared)
1988 md->md.ant.num = (md->md.rfe_type % 3 == 1) ? 1 : 2;
1989 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */
1990 md->md.ant.single_pos = RF_PATH_A;
1991 md->md.ant.btg_pos = RF_PATH_A;
1992 md->md.ant.stream_cnt = 1;
1994 if (md->md.ant.num == 1) {
1995 md->md.ant.type = BTC_ANT_SHARED;
1996 md->md.bt_pos = BTC_BT_BTG;
1997 md->md.wa_type = 1;
1998 md->md.ant.diversity = 0;
2000 md->md.ant.type = BTC_ANT_DEDICATED;
2001 md->md.bt_pos = BTC_BT_ALONE;
2002 md->md.switch_type = BTC_SWITCH_EXTERNAL;
2003 md->md.wa_type = 0;
2004 if (md->md.rfe_type % 3 == 2)
2005 md->md.ant.diversity = 1;
2007 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
2008 rtwdev->btc.ant_type = md->md.ant.type;
2016 group--; /* Tx-group=1, Rx-group=2 */
2018 if (rtwdev->btc.ant_type == BTC_ANT_SHARED) /* 1-Ant */
2031 const struct rtw89_chip_info *chip = rtwdev->chip;
2032 struct rtw89_btc *btc = &rtwdev->btc;
2033 union rtw89_btc_module_info *md = &btc->mdinfo;
2034 const struct rtw89_btc_ver *ver = btc->ver;
2040 /* set WL Tx response = Hi-Pri */
2041 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
2042 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
2044 if (ver->fcxinit == 7) {
2045 str_cnt = md->md_v7.ant.stream_cnt;
2046 ant_sing_pos = md->md_v7.ant.single_pos;
2048 str_cnt = md->md.ant.stream_cnt;
2049 ant_sing_pos = md->md.ant.single_pos;
2052 /* for 1-Ant && 1-ss case: only 1-path */
2062 /* set rf gnt-debug off */
2065 /* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */
2068 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */
2071 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */
2074 /* if GNT_WL = 0 && BT = Tx_group -->
2075 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff)
2077 if (btc->ant_type == BTC_ANT_SHARED && btc->btg_pos == path)
2082 /* set DEBUG_LUT_RFMODE_MASK = 0 to stop trx-mask-setup */
2092 btc->cx.wl.status.map.init_ok = true;
2194 val = clamp_t(s8, val, -100, 0) + 100;
2208 struct rtw89_btc *btc = &rtwdev->btc;
2210 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000);
2211 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWA, RFREG_MASK, 0x1);
2212 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110);
2214 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2216 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c);
2218 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208);
2220 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x0);
2230 /* To improve BT ACI in co-rx
2231 * level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
2232 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
2234 struct rtw89_btc *btc = &rtwdev->btc;
2241 btc->dm.wl_lna2 = 0;
2243 case 1: /* for FDD free-run */
2244 btc->dm.wl_lna2 = 0;
2246 case 2: /* for BTG Co-Rx*/
2247 btc->dm.wl_lna2 = 1;
2251 if (btc->dm.wl_lna2 == 0) {
2260 val = rf->data;
2261 /* bit[10] = 1 if non-shared-ant for 8851b */
2262 if (btc->ant_type == BTC_ANT_DEDICATED)
2265 rtw89_write_rf(rtwdev, btc->btg_pos, rf->addr, LNA2_51B_MA, val);
2273 u16 chan = phy_ppdu->chan_idx;
2281 status->freq = ieee80211_channel_to_frequency(ch, band);
2282 status->band = band;
2290 u8 *rx_power = phy_ppdu->rssi;
2292 status->signal = RTW89_RSSI_RAW_TO_DBM(rx_power[RF_PATH_A]);
2294 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2295 status->chains |= BIT(path);
2296 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2298 if (phy_ppdu->valid)