Lines Matching defs:rtwdev
272 static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev)
278 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
280 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
281 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
282 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
283 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
286 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
290 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
291 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
294 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
298 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
299 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
300 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
301 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
303 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
304 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
306 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
310 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
314 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
317 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
321 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
325 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
328 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
331 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
334 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
337 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH);
341 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
342 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
343 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
347 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
348 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
349 rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN,
352 if (rtwdev->hal.cv == CHIP_CAV) {
353 ret = rtw89_read_efuse_ver(rtwdev, &val8);
355 rtwdev->hal.cv = val8;
358 rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
360 if (rtwdev->hal.cv != CHIP_CAV) {
361 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
362 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
365 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
372 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
378 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
384 static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev)
386 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR);
387 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM);
388 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM);
389 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM);
392 static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev)
397 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
401 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
404 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
407 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
410 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
414 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
417 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
421 rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
423 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
424 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
425 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
427 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
430 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
434 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
436 if (rtwdev->hal.cv == CHIP_CAV) {
437 rtw8851b_patch_swr_pfm2pwm(rtwdev);
439 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
440 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
443 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
456 static void rtw8851b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
459 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
470 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
480 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
496 static void rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
499 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
521 static int rtw8851b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
524 struct rtw89_efuse *efuse = &rtwdev->efuse;
531 rtw8851b_efuse_parsing_tssi(rtwdev, map);
532 rtw8851b_efuse_parsing_gain_offset(rtwdev, map);
534 switch (rtwdev->hci.type) {
542 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
547 static void rtw8851b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
549 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
551 u32 addr = rtwdev->chip->phycap_addr;
569 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
575 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
581 static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
584 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
586 u32 addr = rtwdev->chip->phycap_addr;
592 rtw89_debug(rtwdev, RTW89_DBG_RFK,
601 static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev)
608 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
612 rtw89_debug(rtwdev, RTW89_DBG_RFK,
620 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
622 rtw89_debug(rtwdev, RTW89_DBG_RFK,
629 static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
632 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
634 u32 addr = rtwdev->chip->phycap_addr;
640 rtw89_debug(rtwdev, RTW89_DBG_RFK,
649 static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev)
651 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
656 rtw89_debug(rtwdev, RTW89_DBG_RFK,
666 rtw89_debug(rtwdev, RTW89_DBG_RFK,
670 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
671 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
675 static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
680 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
681 u32 phycap_addr = rtwdev->chip->phycap_addr;
699 static int rtw8851b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
701 rtw8851b_phycap_parsing_tssi(rtwdev, phycap_map);
702 rtw8851b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
703 rtw8851b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
704 rtw8851b_phycap_parsing_gain_comp(rtwdev, phycap_map);
709 static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv,
721 rtw89_phy_write32_mask(rtwdev, addr, mask, RF_PATH_A);
722 rtw89_phy_write32_mask(rtwdev, R_RFE_INV0, BIT(gpio_idx), inv);
728 rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel);
731 static void rtw8851b_set_mac_gpio(struct rtw89_dev *rtwdev, u8 func)
749 rtw89_warn(rtwdev, "undefined gpio func %d\n", func);
753 rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data);
756 static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev)
758 u8 rfe_type = rtwdev->efuse.rfe_type;
764 rtw8851b_set_bb_gpio(rtwdev, 16, true, RFE_SEL0_SRC_ANTSEL_0);
765 rtw8851b_set_bb_gpio(rtwdev, 17, false, RFE_SEL0_SRC_ANTSEL_0);
767 rtw8851b_set_mac_gpio(rtwdev, 16);
768 rtw8851b_set_mac_gpio(rtwdev, 17);
772 static void rtw8851b_power_trim(struct rtw89_dev *rtwdev)
774 rtw8851b_thermal_trim(rtwdev);
775 rtw8851b_pa_bias_trim(rtwdev);
778 static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev,
782 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
783 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
784 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
789 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
792 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
800 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
801 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
804 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
805 rtw89_write32(rtwdev, sub_carr, txsc20);
808 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
809 rtw89_write32(rtwdev, sub_carr, 0);
816 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
817 rtw89_write8_set(rtwdev, chk_rate,
820 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
821 rtw89_write8_clr(rtwdev, chk_rate,
836 static void rtw8851b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
840 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
842 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
904 static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev,
908 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
923 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
934 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
938 static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev,
944 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
957 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
970 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
977 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
981 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
986 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
992 void rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
994 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1002 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
1003 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
1009 rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
1010 rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
1016 rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
1017 rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
1020 static void rtw8851b_ctrl_ch(struct rtw89_dev *rtwdev,
1030 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1033 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1037 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
1044 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
1045 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
1046 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
1047 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
1048 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
1049 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
1050 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
1051 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
1053 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
1054 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
1055 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
1056 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
1057 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
1058 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
1059 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
1060 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
1063 rtw8851b_set_gain_error(rtwdev, subband, RF_PATH_A);
1064 rtw8851b_set_gain_offset(rtwdev, subband, phy_idx);
1065 rtw8851b_set_rxsc_rpl_comp(rtwdev, subband);
1068 static void rtw8851b_bw_setting(struct rtw89_dev *rtwdev, u8 bw)
1070 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8);
1071 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2);
1072 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2);
1073 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0x4);
1074 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0xf);
1075 rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_LP, 0xa);
1076 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92);
1080 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1081 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x0);
1082 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x1);
1085 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1086 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x1);
1087 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1090 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1091 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1092 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1095 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1096 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1097 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1100 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0);
1101 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1102 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1105 rtw89_warn(rtwdev, "Fail to set ADC\n");
1109 static void rtw8851b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1114 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1115 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
1116 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1119 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1120 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
1121 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1124 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1125 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1126 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1129 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
1130 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1131 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1135 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1137 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1141 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
1142 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1143 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1147 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1151 rtw8851b_bw_setting(rtwdev, bw);
1154 static void rtw8851b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
1157 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1158 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1160 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1162 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1163 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1165 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1169 static u32 rtw8851b_spur_freq(struct rtw89_dev *rtwdev,
1193 static void rtw8851b_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1200 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1202 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN,
1211 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX,
1213 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
1225 static void rtw8851b_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1235 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1237 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1239 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1270 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1272 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1274 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1276 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1278 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1281 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1283 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1285 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1287 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1289 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1294 static void rtw8851b_set_cfr(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan)
1299 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1301 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1303 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1305 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1308 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1310 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1312 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1314 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1319 static void rtw8851b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1344 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
1345 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1351 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1352 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1353 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
1354 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
1356 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1357 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1358 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
1359 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
1361 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1365 static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1367 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1369 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1370 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1371 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1372 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1375 static void rtw8851b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1379 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1381 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1383 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
1384 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1386 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
1387 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1388 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1391 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1395 static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev,
1398 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1400 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1401 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1402 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1404 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1408 void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1422 rtw89_phy_write32_mask(rtwdev, R_P0_TRSW,
1426 static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev)
1428 rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);
1429 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X);
1430 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2);
1431 rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777);
1432 rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777);
1434 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1435 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1436 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1437 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1439 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1440 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1441 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1442 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1443 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1444 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1445 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1446 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1449 static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1456 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1459 static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev)
1461 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1463 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1465 rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1466 rtw8851b_bb_gpio_init(rtwdev);
1468 rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE);
1469 rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN);
1473 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
1475 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
1478 static void rtw8851b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1486 rtw8851b_ctrl_sco_cck(rtwdev, chan->primary_channel);
1488 rtw8851b_ctrl_ch(rtwdev, chan, phy_idx);
1489 rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1490 rtw8851b_ctrl_cck_en(rtwdev, cck_en);
1491 rtw8851b_set_nbi_tone_idx(rtwdev, chan);
1492 rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx);
1495 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1497 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1499 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1500 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1501 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1503 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1506 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1507 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx);
1508 rtw8851b_5m_mask(rtwdev, chan, phy_idx);
1509 rtw8851b_set_cfr(rtwdev, chan);
1510 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1513 static void rtw8851b_set_channel(struct rtw89_dev *rtwdev,
1518 rtw8851b_set_channel_mac(rtwdev, chan, mac_idx);
1519 rtw8851b_set_channel_bb(rtwdev, chan, phy_idx);
1520 rtw8851b_set_channel_rf(rtwdev, chan, phy_idx);
1523 static void rtw8851b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1527 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0);
1528 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x0);
1530 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1);
1531 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x1);
1535 static void rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1538 rtw8851b_tssi_cont_en(rtwdev, en, RF_PATH_A);
1541 static void rtw8851b_adc_en(struct rtw89_dev *rtwdev, bool en)
1544 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
1546 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
1549 static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1556 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1557 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
1558 rtw8851b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
1559 rtw8851b_adc_en(rtwdev, false);
1561 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1563 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
1564 rtw8851b_adc_en(rtwdev, true);
1565 rtw8851b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
1566 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1567 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1571 static void rtw8851b_rfk_init(struct rtw89_dev *rtwdev)
1573 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1574 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1575 rtw8851b_lck_init(rtwdev);
1577 rtw8851b_dpk_init(rtwdev);
1578 rtw8851b_aack(rtwdev);
1579 rtw8851b_rck(rtwdev);
1580 rtw8851b_dack(rtwdev);
1581 rtw8851b_rx_dck(rtwdev, RTW89_PHY_0);
1584 static void rtw8851b_rfk_channel(struct rtw89_dev *rtwdev)
1588 rtw8851b_rx_dck(rtwdev, phy_idx);
1589 rtw8851b_iqk(rtwdev, phy_idx);
1590 rtw8851b_tssi(rtwdev, phy_idx, true);
1591 rtw8851b_dpk(rtwdev, phy_idx);
1594 static void rtw8851b_rfk_band_changed(struct rtw89_dev *rtwdev,
1597 rtw8851b_tssi_scan(rtwdev, phy_idx);
1600 static void rtw8851b_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1602 rtw8851b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1605 static void rtw8851b_rfk_track(struct rtw89_dev *rtwdev)
1607 rtw8851b_dpk_track(rtwdev);
1608 rtw8851b_lck_track(rtwdev);
1611 static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1630 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1639 static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev,
1651 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1653 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1656 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1657 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1660 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1663 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1664 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1667 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1671 static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1704 rtw89_warn(rtwdev,
1716 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1718 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
1728 static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev,
1732 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
1734 u8 regd = rtw89_regd_get(rtwdev, band);
1739 rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1741 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
1745 static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev,
1749 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1750 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1751 rtw8851b_set_tx_shape(rtwdev, chan, phy_idx);
1752 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1753 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1756 static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1759 rtw8851b_set_txpwr_ref(rtwdev, phy_idx);
1763 void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1769 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1773 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1774 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1776 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1777 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1780 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1781 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
1785 rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1789 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1793 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1797 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1801 rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1807 static void rtw8851b_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
1810 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1812 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8851b_btc_preagc_en_defs_tbl :
1817 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1819 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1822 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1824 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1830 static void rtw8851b_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
1833 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1836 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1838 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1840 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1842 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1844 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1845 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
1846 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x1);
1847 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1849 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
1851 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1853 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1856 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1858 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1861 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1863 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1866 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
1867 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1868 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1869 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1871 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1875 static void rtw8851b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
1878 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1882 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
1883 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
1884 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
1885 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1886 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1887 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1888 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1889 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1892 rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
1896 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1897 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1901 static void rtw8851b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
1903 rtw8851b_bb_ctrl_rx_path(rtwdev, RF_A);
1905 if (rtwdev->hal.rx_nss == 1) {
1906 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1907 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1908 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1909 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1912 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1915 static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1917 if (rtwdev->is_tssi_mode[rf_path]) {
1920 return rtw89_phy_read32_mask(rtwdev, addr, B_TSSI_THER);
1923 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1924 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1925 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1929 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1932 static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev)
1934 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
1935 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
1938 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
1939 md->md_v7.kt_ver = rtwdev->hal.cv;
1943 md->md_v7.kt_ver_adie = rtwdev->hal.acv;
1971 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
1972 rtwdev->btc.ant_type = md->md_v7.ant.type;
1974 md->md.rfe_type = rtwdev->efuse.rfe_type;
1975 md->md.cv = rtwdev->hal.cv;
1979 md->md.kt_ver_adie = rtwdev->hal.acv;
2007 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
2008 rtwdev->btc.ant_type = md->md.ant.type;
2013 void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2018 if (rtwdev->btc.ant_type == BTC_ANT_SHARED) /* 1-Ant */
2021 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2022 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2025 static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev)
2031 const struct rtw89_chip_info *chip = rtwdev->chip;
2032 struct rtw89_btc *btc = &rtwdev->btc;
2038 rtw89_mac_coex_init(rtwdev, &coex_params);
2041 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
2042 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
2063 rtw89_write_rf(rtwdev, path, RR_WLSEL, RFREG_MASK, 0x0);
2066 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17));
2069 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff);
2072 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df);
2078 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f);
2080 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff);
2083 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0);
2087 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
2090 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
2096 void rtw8851b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2119 rtw89_write32_set(rtwdev, reg, bitmap);
2121 rtw89_write32_clr(rtwdev, reg, bitmap);
2146 rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2159 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2192 s8 rtw8851b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2201 void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2206 static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2208 struct rtw89_btc *btc = &rtwdev->btc;
2210 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000);
2211 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWA, RFREG_MASK, 0x1);
2212 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110);
2216 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c);
2218 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208);
2220 rtw89_write_rf(rtwdev, btc->btg_pos, RR_LUTWE, RFREG_MASK, 0x0);
2228 static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2234 struct rtw89_btc *btc = &rtwdev->btc;
2265 rtw89_write_rf(rtwdev, btc->btg_pos, rf->addr, LNA2_51B_MA, val);
2269 static void rtw8851b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2280 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band);
2285 static void rtw8851b_query_ppdu(struct rtw89_dev *rtwdev,
2294 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2299 rtw8851b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2302 static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2306 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2308 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2309 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2310 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2312 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
2317 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
2322 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
2327 static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2333 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2334 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2337 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
2341 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
2346 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
2350 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,