Lines Matching +full:data +full:- +full:addr
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
13 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr)
15 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr)
19 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr)
20 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr)
21 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr)
22 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr)
100 #define LNA0_GAIN (-24)
116 #define CCKPD_TH_MIN_RSSI (-18)
234 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1
315 u32 data;
350 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM];
519 u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr);
546 u32 addr, u8 data)
548 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
550 rtw89_write8(rtwdev, addr + phy->cr_base, data);
554 u32 addr, u16 data)
556 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
558 rtw89_write16(rtwdev, addr + phy->cr_base, data);
562 u32 addr, u32 data)
564 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
566 rtw89_write32(rtwdev, addr + phy->cr_base, data);
570 u32 addr, u32 bits)
572 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
574 rtw89_write32_set(rtwdev, addr + phy->cr_base, bits);
578 u32 addr, u32 bits)
580 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
582 rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits);
586 u32 addr, u32 mask, u32 data)
588 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
590 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data);
593 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr)
595 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
597 return rtw89_read8(rtwdev, addr + phy->cr_base);
600 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr)
602 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
604 return rtw89_read16(rtwdev, addr + phy->cr_base);
607 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr)
609 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
611 return rtw89_read32(rtwdev, addr + phy->cr_base);
615 u32 addr, u32 mask)
617 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
619 return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask);
623 u32 addr, u32 data, enum rtw89_phy_idx phy_idx)
625 if (phy_idx && addr < 0x10000)
626 addr += 0x20000;
628 rtw89_write32(rtwdev, addr + RTW89_BBMCU_ADDR_OFFSET, data);
724 /* desc is valid iff ch is non-zero */
759 .addr = _addr, \
761 .data = _data,}
765 .addr = _addr, \
767 .data = _data,}
771 .addr = _addr, \
776 .addr = _addr, \
781 .data = _data,}
803 u32 addr, u32 mask);
805 u32 addr, u32 mask);
807 u32 addr, u32 mask);
809 u32 addr, u32 mask, u32 data);
811 u32 addr, u32 mask, u32 data);
813 u32 addr, u32 mask, u32 data);
822 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
823 u32 data, enum rtw89_phy_idx phy_idx);
824 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
826 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
828 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
849 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
851 phy->preinit_rf_nctl(rtwdev);
856 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
858 if (phy->bb_wrap_init)
859 phy->bb_wrap_init(rtwdev);
864 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
866 if (phy->ch_info_init)
867 phy->ch_info_init(rtwdev);
875 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
877 phy->set_txpwr_byrate(rtwdev, chan, phy_idx);
885 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
887 phy->set_txpwr_offset(rtwdev, chan, phy_idx);
895 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
897 phy->set_txpwr_limit(rtwdev, chan, phy_idx);
905 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
907 phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx);
912 const struct rtw89_chip_info *chip = rtwdev->chip;
914 return txpwr_rf << (chip->txpwr_factor_bb - chip->txpwr_factor_rf);
919 const struct rtw89_chip_info *chip = rtwdev->chip;
921 return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac);
926 const struct rtw89_chip_info *chip = rtwdev->chip;
928 return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63);
986 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,