Lines Matching refs:phy_idx

479 	ra->band_num = rtwvif_link->phy_idx;
1139 enum rtw89_phy_idx phy_idx)
1143 chip->ops->bb_reset(rtwdev, phy_idx);
1822 u32 data, enum rtw89_phy_idx phy_idx)
1824 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1831 enum rtw89_phy_idx phy_idx)
1833 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1840 enum rtw89_phy_idx phy_idx)
1842 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1849 enum rtw89_phy_idx phy_idx)
1851 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
2710 enum rtw89_phy_idx phy_idx)
2756 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
2767 enum rtw89_phy_idx phy_idx)
2789 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
2795 enum rtw89_phy_idx phy_idx)
2823 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2830 enum rtw89_phy_idx phy_idx)
2858 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
3558 enum rtw89_phy_idx phy_idx,
3565 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx);
3574 enum rtw89_phy_idx phy_idx,
3583 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, chan, tssi_mode);
3592 enum rtw89_phy_idx phy_idx,
3600 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx, chan);
3609 enum rtw89_phy_idx phy_idx,
3617 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx, chan);
3626 enum rtw89_phy_idx phy_idx,
3634 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx, chan);
3643 enum rtw89_phy_idx phy_idx,
3651 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx, chan);
3660 enum rtw89_phy_idx phy_idx,
3668 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx, chan, is_chl_k);
5730 enum rtw89_phy_idx phy_idx)
5739 return rtw89_phy_read32_idx(rtwdev, addr, MASKDWORD, phy_idx);
5744 u32 val, enum rtw89_phy_idx phy_idx)
5756 rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx);
5762 bool enable, enum rtw89_phy_idx phy_idx)
5764 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap, phy_idx);
5771 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val, phy_idx);
5776 enum rtw89_phy_idx phy_idx)
5783 physts->dis_trigger_fail_mask, phy_idx);
5785 physts->dis_trigger_brk_mask, phy_idx);
5788 physts->dis_trigger_fail_mask, phy_idx);
5790 physts->dis_trigger_brk_mask, phy_idx);
5795 enum rtw89_phy_idx phy_idx)
5799 rtw89_physts_enable_fail_report(rtwdev, false, phy_idx);
5805 true, phy_idx);
5811 true, phy_idx);
5814 RTW89_PHYSTS_IE13_DL_MU_DEF, true, phy_idx);
5816 RTW89_PHYSTS_IE13_DL_MU_DEF, true, phy_idx);
5820 RTW89_PHYSTS_IE01_CMN_OFDM, true, phy_idx);
6584 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
6601 phy_idx);
6603 bss_color, phy_idx);
6605 vif->cfg.aid, phy_idx);
7095 enum rtw89_phy_idx phy_idx)
7099 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7103 if (phy_idx == RTW89_PHY_0)
7108 if (phy_idx == RTW89_PHY_0)
7120 if (phy_idx == RTW89_PHY_0)
7129 enum rtw89_phy_idx phy_idx)
7133 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7137 if (phy_idx == RTW89_PHY_0)
7142 if (phy_idx == RTW89_PHY_0)
7148 if (phy_idx == RTW89_PHY_0)
7156 if (phy_idx == RTW89_PHY_0)