Lines Matching +full:out +full:- +full:of +full:- +full:band
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
20 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
22 return phy->phy0_phy1_offset(rtwdev, addr);
28 u32 bit_rate = report->bit_rate;
35 if (report->might_fallback_legacy)
50 return rtwdev->chip->max_amsdu_limit;
66 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss;
69 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss;
81 struct ieee80211_sta_he_cap cap = link_sta->he_cap;
84 switch (link_sta->bandwidth) {
124 struct ieee80211_sta_eht_cap *eht_cap = &link_sta->eht_cap;
127 u8 *he_phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;
129 switch (link_sta->bandwidth) {
131 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320;
133 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
135 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160;
137 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
141 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz;
143 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4);
148 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80;
150 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
204 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
205 enum nl80211_band band;
208 if (!rtwsta_link->use_cfg_mask)
209 return -1;
211 switch (chan->band_type) {
213 band = NL80211_BAND_2GHZ;
214 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy,
218 band = NL80211_BAND_5GHZ;
219 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy,
223 band = NL80211_BAND_6GHZ;
224 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy,
228 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type);
229 return -1;
232 if (link_sta->he_cap.has_he) {
233 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0],
235 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1],
237 } else if (link_sta->vht_cap.vht_supported) {
238 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
240 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
242 } else if (link_sta->ht_cap.ht_supported) {
243 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
245 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
274 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
275 u8 band = chan->band_type;
276 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
277 u8 he_ltf = mask->control[nl_band].he_ltf;
278 u8 he_gi = mask->control[nl_band].he_gi;
282 if (rtwdev->chip->chip_id == RTL8852C &&
283 chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
289 if (!(rtwsta_link->use_cfg_mask && link_sta->he_cap.has_he))
313 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
314 struct rtw89_ra_info *ra = &rtwsta_link->ra;
316 rtwvif_link->chanctx_idx);
318 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi);
333 if (link_sta->eht_cap.has_eht) {
337 if (rtwdev->hal.no_mcs_12_13)
344 } else if (link_sta->he_cap.has_he) {
349 if (link_sta->he_cap.he_cap_elem.phy_cap_info[2] &
352 if (link_sta->he_cap.he_cap_elem.phy_cap_info[1] &
357 } else if (link_sta->vht_cap.vht_supported) {
358 u16 mcs_map = le16_to_cpu(link_sta->vht_cap.vht_mcs.rx_mcs_map);
362 /* MCS9 (non-20MHz), MCS8, MCS7 */
363 if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20)
368 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
370 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
372 } else if (link_sta->ht_cap.ht_supported) {
375 ra_mask |= ((u64)link_sta->ht_cap.mcs.rx_mask[3] << 48) |
376 ((u64)link_sta->ht_cap.mcs.rx_mask[2] << 36) |
377 ((u64)link_sta->ht_cap.mcs.rx_mask[1] << 24) |
378 ((u64)link_sta->ht_cap.mcs.rx_mask[0] << 12);
380 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
382 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
386 switch (chan->band_type) {
388 ra_mask |= link_sta->supp_rates[NL80211_BAND_2GHZ];
389 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xf)
391 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xff0)
395 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_5GHZ] << 4;
399 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_6GHZ] << 4;
403 rtw89_err(rtwdev, "Unknown band type\n");
411 for (i = 0; i < rtwdev->hal.tx_nss; i++)
428 switch (link_sta->bandwidth) {
431 sgi = link_sta->vht_cap.vht_supported &&
432 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160);
436 sgi = link_sta->vht_cap.vht_supported &&
437 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
441 sgi = link_sta->ht_cap.ht_supported &&
442 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
446 sgi = link_sta->ht_cap.ht_supported &&
447 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
451 if (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
453 ra->dcm_cap = 1;
455 if (rate_pattern->enable && !p2p) {
457 ra_mask &= rate_pattern->ra_mask;
458 mode = rate_pattern->ra_mode;
461 ra->bw_cap = bw_mode;
462 ra->er_cap = rtwsta_link->er_cap;
463 ra->mode_ctrl = mode;
464 ra->macid = rtwsta_link->mac_id;
465 ra->stbc_cap = stbc_en;
466 ra->ldpc_cap = ldpc_en;
467 ra->ss_num = min(link_sta->rx_nss, rtwdev->hal.tx_nss) - 1;
468 ra->en_sgi = sgi;
469 ra->ra_mask = ra_mask;
470 ra->fix_giltf_en = fix_giltf_en;
471 ra->fix_giltf = fix_giltf;
476 ra->fixed_csi_rate_en = false;
477 ra->ra_csi_rate_en = true;
478 ra->cr_tbl_sel = false;
479 ra->band_num = rtwvif_link->phy_idx;
480 ra->csi_bw = bw_mode;
481 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32;
482 ra->csi_mcs_ss_idx = 5;
483 ra->csi_mode = csi_mode;
490 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
492 struct rtw89_ra_info *ra = &rtwsta_link->ra;
499 link_sta, vif->p2p, false);
504 ra->upd_mask = 1;
506 ra->upd_bw_nss_mask = 1;
510 ra->macid,
511 ra->bw_cap,
512 ra->ss_num,
513 ra->en_sgi,
514 ra->giltf);
546 if (next->enable)
550 next->rate = rate_base + c;
551 next->ra_mode = ra_mode;
552 next->ra_mask = ra_mask;
553 next->enable = true;
572 rtwvif_link->chanctx_idx);
591 u8 band = chan->band_type;
592 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
593 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
594 u8 tx_nss = rtwdev->hal.tx_nss;
600 mask->control[nl_band].he_mcs[i],
602 goto out;
607 mask->control[nl_band].vht_mcs[i],
609 goto out;
614 mask->control[nl_band].ht_mcs[i],
616 goto out;
622 sband = rtwdev->hw->wiphy->bands[nl_band];
623 if (band == RTW89_BAND_2G) {
627 mask->control[nl_band].legacy,
628 BIT(sband->n_bitrates) - 1, false))
629 goto out;
633 mask->control[nl_band].legacy,
634 BIT(sband->n_bitrates) - 1, false))
635 goto out;
639 goto out;
641 rtwvif_link->rate_pattern = next_pattern;
656 out:
657 rtwvif_link->rate_pattern.enable = false;
682 ieee80211_iterate_stations_atomic(rtwdev->hw,
689 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
691 struct rtw89_ra_info *ra = &rtwsta_link->ra;
692 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi) >> RSSI_FACTOR;
702 link_sta, vif->p2p, csi);
707 ra->init_rate_lv = 1;
709 ra->init_rate_lv = 2;
711 ra->init_rate_lv = 3;
713 ra->init_rate_lv = 0;
714 ra->upd_all = 1;
717 ra->macid,
718 ra->mode_ctrl,
719 ra->bw_cap,
720 ra->ss_num,
721 ra->init_rate_lv);
724 ra->dcm_cap,
725 ra->er_cap,
726 ra->ldpc_cap,
727 ra->stbc_cap,
728 ra->en_sgi,
729 ra->giltf);
738 enum rtw89_bandwidth cbw = chan->band_width;
739 u8 pri_ch = chan->primary_channel;
740 u8 central_ch = chan->channel;
754 txsc_idx = (pri_ch - central_ch) >> 1;
756 txsc_idx = ((central_ch - pri_ch) >> 1) + 1;
763 tmp = (pri_ch - central_ch) >> 1;
765 tmp = ((central_ch - pri_ch) >> 1) + 1;
787 txsc_idx = (10 - (pri_ch - central_ch)) >> 1;
789 txsc_idx = ((central_ch - pri_ch) >> 1) + 5;
807 enum rtw89_bandwidth cbw = chan->band_width;
808 u8 pri_ch = chan->primary_channel;
809 u8 central_ch = chan->channel;
821 txsb_idx = (pri_ch - central_ch + 6) / 4;
827 txsb_idx = (pri_ch - central_ch + 14) / 4;
829 txsb_idx = (pri_ch - central_ch + 12) / 8;
835 txsb_idx = (pri_ch - central_ch + 30) / 4;
837 txsb_idx = (pri_ch - central_ch + 28) / 8;
839 txsb_idx = (pri_ch - central_ch + 24) / 16;
860 const struct rtw89_chip_info *chip = rtwdev->chip;
861 const u32 *base_addr = chip->rf_base_addr;
864 if (rf_path >= rtwdev->chip->rf_path_num) {
917 if (rf_path >= rtwdev->chip->rf_path_num) {
957 goto out;
961 out:
982 if (rf_path >= rtwdev->chip->rf_path_num) {
997 const struct rtw89_chip_info *chip = rtwdev->chip;
998 const u32 *base_addr = chip->rf_base_addr;
1001 if (rf_path >= rtwdev->chip->rf_path_num) {
1061 if (rf_path >= rtwdev->chip->rf_path_num) {
1121 if (rf_path >= rtwdev->chip->rf_path_num) {
1135 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1;
1141 const struct rtw89_chip_info *chip = rtwdev->chip;
1143 chip->ops->bb_reset(rtwdev, phy_idx);
1149 if (rtwdev->dbcc_en)
1160 if (reg->addr == 0xfe) {
1162 } else if (reg->addr == 0xfd) {
1164 } else if (reg->addr == 0xfc) {
1166 } else if (reg->addr == 0xfb) {
1168 } else if (reg->addr == 0xfa) {
1170 } else if (reg->addr == 0xf9) {
1172 } else if (reg->data == BYPASS_CR_DATA) {
1173 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr);
1175 addr = reg->addr;
1178 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr);
1180 rtw89_phy_write32(rtwdev, addr, reg->data);
1204 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1213 gain->lna_gain[gband][path][i] = data & 0xff;
1217 gain->lna_gain[gband][path][i] = data & 0xff;
1221 gain->tia_gain[gband][path][i] = data & 0xff;
1243 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1254 gain->rpl_ofst_20[gband][path] = (s8)data;
1258 gain->rpl_ofst_40[gband][path][0] = (s8)data;
1263 gain->rpl_ofst_40[gband][path][rxsc] = ofst;
1269 gain->rpl_ofst_80[gband][path][0] = (s8)data;
1274 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1280 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1286 gain->rpl_ofst_160[gband][path][0] = (s8)data;
1291 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1297 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1303 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1309 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1325 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1334 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1338 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1352 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1361 gain->lna_op1db[gband][path][i] = data & 0xff;
1365 gain->lna_op1db[gband][path][i] = data & 0xff;
1369 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1373 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1388 const struct rtw89_chip_info *chip = rtwdev->chip;
1389 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
1390 struct rtw89_efuse *efuse = &rtwdev->efuse;
1395 if (arg.path >= chip->rf_path_num)
1405 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data);
1408 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data);
1411 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data);
1414 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
1418 if (efuse->rfe_type < 50)
1424 arg.addr, reg->data, arg.cfg_type);
1435 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE;
1436 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE;
1440 rf_path, info->curr_idx);
1444 info->rtw89_phy_config_rf_h2c[page][idx] =
1445 cpu_to_le32((reg->addr << 20) | reg->data);
1446 info->curr_idx++;
1452 u16 remain = info->curr_idx;
1461 ret = -EINVAL;
1462 goto out;
1465 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) {
1469 goto out;
1471 out:
1472 info->curr_idx = 0;
1482 u32 addr = reg->addr;
1500 if (reg->addr == 0xfe) {
1502 } else if (reg->addr == 0xfd) {
1504 } else if (reg->addr == 0xfc) {
1506 } else if (reg->addr == 0xfb) {
1508 } else if (reg->addr == 0xfa) {
1510 } else if (reg->addr == 0xf9) {
1513 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
1524 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
1526 if (reg->addr < 0x100)
1547 for (i = 0; i < table->n_regs; i++) {
1548 reg = &table->regs[i];
1549 headline = get_phy_headline(reg->addr);
1560 reg = &table->regs[i];
1561 target = get_phy_target(reg->addr);
1571 reg = &table->regs[i];
1572 target = get_phy_target(reg->addr);
1581 reg = &table->regs[i];
1582 rfe_para = get_phy_cond_rfe(reg->addr);
1583 cv_para = get_phy_cond_cv(reg->addr);
1598 reg = &table->regs[i];
1599 rfe_para = get_phy_cond_rfe(reg->addr);
1600 cv_para = get_phy_cond_cv(reg->addr);
1613 return -EINVAL;
1625 enum rtw89_rf_path rf_path = table->rf_path;
1626 u8 rfe = rtwdev->efuse.rfe_type;
1627 u8 cv = rtwdev->hal.cv;
1643 cfg_target = get_phy_target(table->regs[headline_idx].addr);
1644 for (i = headline_size; i < table->n_regs; i++) {
1645 reg = &table->regs[i];
1646 cond = get_phy_cond(reg->addr);
1650 target = get_phy_target(reg->addr);
1656 reg->addr, reg->data);
1688 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1689 const struct rtw89_chip_info *chip = rtwdev->chip;
1693 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table;
1695 if (rtwdev->dbcc_en)
1701 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table;
1704 chip->phy_def->config_bb_gain, NULL);
1720 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1721 const struct rtw89_chip_info *chip = rtwdev->chip;
1730 for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
1731 rf_table = elm_info->rf_radio[path] ?
1732 elm_info->rf_radio[path] : chip->rf_table[path];
1733 rf_reg_info->rf_path = rf_table->rf_path;
1737 config = rf_table->config ? rf_table->config :
1742 rf_reg_info->rf_path);
1749 const struct rtw89_chip_info *chip = rtwdev->chip;
1757 if (chip->chip_id != RTL8851B)
1759 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT)
1777 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1778 const struct rtw89_chip_info *chip = rtwdev->chip;
1783 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table;
1786 if (chip->nctl_post_table)
1787 rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
1824 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1833 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1842 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1851 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1862 if (!rtwdev->dbcc_en)
1875 for (i = 0; i < tbl->size; i++) {
1876 reg3 = &tbl->reg3[i];
1877 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
1895 /* antenna gain in unit of 0.25 dbm */
1896 #define RTW89_ANT_GAIN_2GHZ_MIN -8
1898 #define RTW89_ANT_GAIN_5GHZ_MIN -8
1900 #define RTW89_ANT_GAIN_6GHZ_MIN -8
1909 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
1910 const struct rtw89_chip_info *chip = rtwdev->chip;
1918 if (!chip->support_ant_gain)
1943 ant_gain->regd_enabled |= BIT(regd);
1952 val = RTW89_ANT_GAIN_REF_2GHZ -
1961 val = RTW89_ANT_GAIN_REF_5GHZ -
1972 val = RTW89_ANT_GAIN_REF_6GHZ -
1977 ant_gain->offset[i][j] = val;
2026 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2033 subband_l = span->ant_gain_subband_low;
2034 subband_h = span->ant_gain_subband_high;
2044 return min(ant_gain->offset[path][subband_l],
2045 ant_gain->offset[path][subband_h]);
2048 static s8 rtw89_phy_ant_gain_offset(struct rtw89_dev *rtwdev, u8 band, u32 center_freq)
2050 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2051 const struct rtw89_chip_info *chip = rtwdev->chip;
2052 u8 regd = rtw89_regd_get(rtwdev, band);
2055 if (!chip->support_ant_gain)
2058 if (!(ant_gain->regd_enabled & BIT(regd)))
2070 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2071 u8 regd = rtw89_regd_get(rtwdev, chan->band_type);
2074 if (!(ant_gain->regd_enabled & BIT(regd)))
2077 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2078 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2080 return rtw89_phy_txpwr_rf_to_bb(rtwdev, offset_patha - offset_pathb);
2087 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2088 const struct rtw89_chip_info *chip = rtwdev->chip;
2089 u8 regd = rtw89_regd_get(rtwdev, chan->band_type);
2092 if (!chip->support_ant_gain || !(ant_gain->regd_enabled & BIT(regd))) {
2097 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2098 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2124 switch (desc->rs) {
2126 return &head->cck[desc->idx];
2128 return &head->ofdm[desc->idx];
2130 return &head->mcs[desc->ofdma][desc->nss][desc->idx];
2132 return &head->hedcm[desc->ofdma][desc->nss][desc->idx];
2134 return &head->offset[desc->idx];
2136 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs);
2137 return &head->trap;
2144 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data;
2145 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size;
2153 byr_head = &rtwdev->byr[cfg->band][0];
2154 desc.rs = cfg->rs;
2155 desc.nss = cfg->nss;
2156 data = cfg->data;
2158 for (i = 0; i < cfg->len; i++, data >>= 8) {
2159 desc.idx = cfg->shf + i;
2173 dbm -= tssi_max_deviation;
2178 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band)
2180 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2181 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe;
2184 if (band == RTW89_BAND_6G && tpe->valid)
2185 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint);
2190 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
2196 if (rate_desc->rs == RTW89_RS_CCK)
2197 band = RTW89_BAND_2G;
2199 byr_head = &rtwdev->byr[band][bw];
2209 return (channel_6g - 1) / 2;
2211 return (channel_6g - 3) / 2;
2213 return (channel_6g - 5) / 2;
2215 return (channel_6g - 7) / 2;
2217 return (channel_6g - 9) / 2;
2219 return (channel_6g - 11) / 2;
2221 return (channel_6g - 13) / 2;
2223 return (channel_6g - 15) / 2;
2230 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel)
2232 if (band == RTW89_BAND_6G)
2237 return channel - 1;
2239 return (channel - 36) / 2;
2241 return ((channel - 100) / 2) + 15;
2243 return ((channel - 149) / 2) + 38;
2250 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
2253 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2254 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2255 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2256 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2257 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2258 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2260 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2261 u8 regd = rtw89_regd_get(rtwdev, band);
2262 u8 reg6 = regulatory->reg_6ghz_power;
2266 switch (band) {
2268 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2272 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2275 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2279 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2282 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
2286 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW]
2291 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2295 offset = rtw89_phy_ant_gain_offset(rtwdev, band, freq);
2298 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2304 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \
2309 band, \
2317 u8 band, u8 ntx, u8 ch)
2319 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2321 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2323 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2325 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2332 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2334 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2335 ntx, RTW89_RS_CCK, ch - 2);
2336 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2338 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2340 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2342 ntx, RTW89_RS_MCS, ch - 2);
2343 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2346 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2353 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2359 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2361 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2363 ntx, RTW89_RS_MCS, ch - 6);
2364 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2366 ntx, RTW89_RS_MCS, ch - 2);
2367 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2370 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2373 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2375 ntx, RTW89_RS_MCS, ch - 4);
2376 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2379 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2383 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2384 ntx, RTW89_RS_MCS, ch - 4);
2385 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2389 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2394 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2403 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2407 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2409 ntx, RTW89_RS_MCS, ch - 14);
2410 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2412 ntx, RTW89_RS_MCS, ch - 10);
2413 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2415 ntx, RTW89_RS_MCS, ch - 6);
2416 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2418 ntx, RTW89_RS_MCS, ch - 2);
2419 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band,
2422 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band,
2425 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band,
2428 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band,
2433 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2435 ntx, RTW89_RS_MCS, ch - 12);
2436 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2438 ntx, RTW89_RS_MCS, ch - 4);
2439 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band,
2442 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band,
2447 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2449 ntx, RTW89_RS_MCS, ch - 8);
2450 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band,
2455 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band,
2460 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2461 ntx, RTW89_RS_MCS, ch - 4);
2462 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2466 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2469 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40,
2470 ntx, RTW89_RS_MCS, ch - 8);
2471 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40,
2475 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
2484 u8 band = chan->band_type;
2485 u8 pri_ch = chan->primary_channel;
2486 u8 ch = chan->channel;
2487 u8 bw = chan->band_width;
2493 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch);
2496 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch,
2500 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch,
2504 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch,
2510 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
2513 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2514 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2515 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2516 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2517 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2518 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2520 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2521 u8 regd = rtw89_regd_get(rtwdev, band);
2522 u8 reg6 = regulatory->reg_6ghz_power;
2526 switch (band) {
2528 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2532 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2535 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2539 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2542 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx];
2546 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW]
2551 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2555 offset = rtw89_phy_ant_gain_offset(rtwdev, band, freq);
2558 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2566 u8 band, u8 ntx, u8 ch)
2568 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2571 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2574 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2582 u8 band, u8 ntx, u8 ch)
2584 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2586 ntx, ch - 2);
2587 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2590 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2592 ntx, ch - 2);
2593 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2596 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2598 ntx, ch - 2);
2599 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2607 u8 band, u8 ntx, u8 ch)
2609 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2611 ntx, ch - 6);
2612 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2614 ntx, ch - 2);
2615 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2618 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2621 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2623 ntx, ch - 6);
2624 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2626 ntx, ch - 2);
2627 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2630 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2633 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2635 ntx, ch - 6);
2636 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2638 ntx, ch - 2);
2639 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2642 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2650 u8 band, u8 ntx, u8 ch)
2652 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 };
2661 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2665 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2669 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2682 u8 band = chan->band_type;
2683 u8 ch = chan->channel;
2684 u8 bw = chan->band_width;
2690 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx,
2694 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx,
2698 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx,
2702 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx,
2712 u8 max_nss_num = rtwdev->chip->rf_path_num;
2720 u8 band = chan->band_type;
2721 u8 ch = chan->channel;
2745 band, 0,
2773 u8 band = chan->band_type;
2780 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
2797 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2799 u8 ch = chan->channel;
2800 u8 bw = chan->band_width;
2832 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2834 u8 ch = chan->channel;
2835 u8 bw = chan->band_width;
2872 struct rtw89_dev *rtwdev = ra_data->rtwdev;
2874 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data;
2875 struct rtw89_ra_report *ra_report = &rtwsta_link->ra_report;
2876 const struct rtw89_chip_info *chip = rtwdev->chip;
2877 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE;
2884 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID);
2885 if (mac_id != rtwsta_link->mac_id)
2888 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS);
2889 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW);
2890 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF);
2891 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL);
2894 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7);
2896 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2);
2898 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2);
2908 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate));
2912 ra_report->txrate.legacy = legacy_bitrate;
2915 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS;
2916 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw))
2921 ra_report->txrate.mcs = rate;
2923 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2924 mcs = ra_report->txrate.mcs & 0x07;
2927 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS;
2928 ra_report->txrate.mcs = format_v1 ?
2931 ra_report->txrate.nss = format_v1 ?
2935 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2936 mcs = ra_report->txrate.mcs;
2939 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS;
2940 ra_report->txrate.mcs = format_v1 ?
2943 ra_report->txrate.nss = format_v1 ?
2947 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8;
2949 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6;
2951 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2;
2952 mcs = ra_report->txrate.mcs;
2955 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS;
2956 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1);
2957 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1;
2959 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8;
2961 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6;
2963 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2;
2964 mcs = ra_report->txrate.mcs;
2968 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw);
2969 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate);
2970 ra_report->hw_rate = format_v1 ?
2975 ra_report->might_fallback_legacy = mcs <= 2;
2976 link_sta->agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
2977 rtwsta_link->max_agg_wait = link_sta->agg.max_rc_amsdu_len / 1500 - 1;
3005 ieee80211_iterate_stations_atomic(rtwdev->hw,
3033 goto out;
3037 "[IQK] iqk->is_iqk_init = %x\n", iqk->is_iqk_init);
3039 "[IQK] iqk->is_reload = %x\n", iqk->is_reload);
3041 "[IQK] iqk->is_nbiqk = %x\n", iqk->is_nbiqk);
3043 "[IQK] iqk->txiqk_en = %x\n", iqk->txiqk_en);
3045 "[IQK] iqk->rxiqk_en = %x\n", iqk->rxiqk_en);
3047 "[IQK] iqk->lok_en = %x\n", iqk->lok_en);
3049 "[IQK] iqk->iqk_xym_en = %x\n", iqk->iqk_xym_en);
3051 "[IQK] iqk->iqk_sram_en = %x\n", iqk->iqk_sram_en);
3053 "[IQK] iqk->iqk_fft_en = %x\n", iqk->iqk_fft_en);
3055 "[IQK] iqk->is_fw_iqk = %x\n", iqk->is_fw_iqk);
3057 "[IQK] iqk->is_iqk_enable = %x\n", iqk->is_iqk_enable);
3059 "[IQK] iqk->iqk_cfir_en = %x\n", iqk->iqk_cfir_en);
3061 "[IQK] iqk->thermal_rek_en = %x\n", iqk->thermal_rek_en);
3063 "[IQK] iqk->version = %x\n", iqk->version);
3065 "[IQK] iqk->phy = %x\n", iqk->phy);
3067 "[IQK] iqk->fwk_status = %x\n", iqk->fwk_status);
3072 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_band[%d] = %x\n",
3073 i, iqk->iqk_band[i]);
3074 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_ch[%d] = %x\n",
3075 i, iqk->iqk_ch[i]);
3076 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_bw[%d] = %x\n",
3077 i, iqk->iqk_bw[i]);
3078 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_idac[%d] = %x\n",
3079 i, le32_to_cpu(iqk->lok_idac[i]));
3080 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_vbuf[%d] = %x\n",
3081 i, le32_to_cpu(iqk->lok_vbuf[i]));
3082 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_tx_fail[%d] = %x\n",
3083 i, iqk->iqk_tx_fail[i]);
3084 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_rx_fail[%d] = %x\n",
3085 i, iqk->iqk_rx_fail[i]);
3088 "[IQK] iqk->rftxgain[%d][%d] = %x\n",
3089 i, j, le32_to_cpu(iqk->rftxgain[i][j]));
3092 "[IQK] iqk->tx_xym[%d][%d] = %x\n",
3093 i, j, le32_to_cpu(iqk->tx_xym[i][j]));
3096 "[IQK] iqk->rfrxgain[%d][%d] = %x\n",
3097 i, j, le32_to_cpu(iqk->rfrxgain[i][j]));
3100 "[IQK] iqk->rx_xym[%d][%d] = %x\n",
3101 i, j, le32_to_cpu(iqk->rx_xym[i][j]));
3106 goto out;
3110 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n",
3111 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok);
3114 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q);
3117 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov);
3121 goto out;
3128 dack->fwdack_ver, dack->fwdack_info_ver, 0x2);
3132 dack->addck_timeout, dack->cdack_timeout, dack->dadck_timeout,
3133 dack->adgaink_timeout, dack->msbk_timeout);
3135 "[DACK]DACK fail = 0x%x\n", dack->dack_fail);
3137 "[DACK]S0 WBADCK = [0x%x]\n", dack->wbdck_d[0]);
3139 "[DACK]S1 WBADCK = [0x%x]\n", dack->wbdck_d[1]);
3141 "[DACK]DRCK = [0x%x]\n", dack->rck_d);
3143 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]);
3145 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]);
3147 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]);
3149 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]);
3152 ((u32)dack->addck2_hd[0][0][0] << 8) | dack->addck2_ld[0][0][0],
3153 ((u32)dack->addck2_hd[0][0][1] << 8) | dack->addck2_ld[0][0][1]);
3155 ((u32)dack->addck2_hd[0][1][0] << 8) | dack->addck2_ld[0][1][0],
3156 ((u32)dack->addck2_hd[0][1][1] << 8) | dack->addck2_ld[0][1][1]);
3158 ((u32)dack->addck2_hd[1][0][0] << 8) | dack->addck2_ld[1][0][0],
3159 ((u32)dack->addck2_hd[1][0][1] << 8) | dack->addck2_ld[1][0][1]);
3161 ((u32)dack->addck2_hd[1][1][0] << 8) | dack->addck2_ld[1][1][0],
3162 ((u32)dack->addck2_hd[1][1][1] << 8) | dack->addck2_ld[1][1][1]);
3165 dack->adgaink_d[0][0], dack->adgaink_d[0][1]);
3167 dack->adgaink_d[1][0], dack->adgaink_d[1][1]);
3170 dack->dadck_d[0][0], dack->dadck_d[0][1]);
3172 dack->dadck_d[1][0], dack->dadck_d[1][1]);
3175 ((u32)dack->biask_hd[0][0] << 8) | dack->biask_ld[0][0]);
3177 ((u32)dack->biask_hd[1][0] << 8) | dack->biask_ld[1][0]);
3182 dack->msbk_d[0][0][i]);
3187 dack->msbk_d[0][1][i]);
3192 dack->msbk_d[1][0][i]);
3197 dack->msbk_d[1][1][i]);
3201 goto out;
3205 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n",
3206 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch,
3207 rxdck->timeout);
3211 goto out;
3219 i, j, k, tssi->alignment_power_cw_h[i][j][k]);
3222 i, j, k, tssi->alignment_power_cw_l[i][j][k]);
3225 i, j, k, tssi->alignment_power[i][j][k]);
3229 (tssi->alignment_power_cw_h[i][j][k] << 8) +
3230 tssi->alignment_power_cw_l[i][j][k]);
3235 i, j, tssi->tssi_alimk_state[i][j]);
3238 j, tssi->default_txagc_offset[0][j]);
3244 goto out;
3249 le32_to_cpu(txgapk->r0x8010[0]),
3250 le32_to_cpu(txgapk->r0x8010[1]));
3252 txgapk->chk_id);
3254 le32_to_cpu(txgapk->chk_cnt));
3256 txgapk->ver);
3258 txgapk->rsv1);
3261 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]);
3263 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]);
3265 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]);
3267 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]);
3273 out:
3282 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
3291 if (!elm_info->rfk_log_fmt)
3294 elm = elm_info->rfk_log_fmt->elm[func];
3295 fmt_idx = le32_to_cpu(log->fmt_idx);
3296 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr)
3299 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]);
3303 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset],
3304 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]),
3305 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3]));
3314 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data;
3329 len -= sizeof(*c2h_hdr);
3337 content_len = le16_to_cpu(log_hdr->len);
3343 switch (log_hdr->type) {
3346 log_hdr->content, content_len);
3351 rfk_name, content_len, log_hdr->content);
3355 log_hdr->content, content_len);
3362 len -= chunk_len;
3422 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3424 wait->state = RTW89_RFK_STATE_START;
3425 wait->start_time = ktime_get();
3426 reinit_completion(&wait->completion);
3433 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3437 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) {
3439 goto out;
3442 time_left = wait_for_completion_timeout(&wait->completion,
3446 return -ETIMEDOUT;
3447 } else if (wait->state != RTW89_RFK_STATE_OK) {
3449 rfk_name, wait->state);
3450 return -EFAULT;
3453 out:
3456 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time));
3459 rfk_name, ktime_ms_delta(ktime_get(), (intmax_t)wait->start_time));
3469 (const struct rtw89_c2h_rfk_report *)c2h->data;
3470 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3472 wait->state = report->state;
3473 wait->version = report->version;
3475 complete(&wait->completion);
3479 wait->state, wait->version,
3480 (int)(len - sizeof(report->hdr)), &report->state);
3981 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3982 enum rtw89_band band = chan->band_type;
3983 u8 ch = chan->channel;
3991 if (band == RTW89_BAND_6G)
4003 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
4004 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
4011 val = tssi_info->tssi_mcs[path][gidx];
4029 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st];
4030 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd];
4037 val = tssi_info->tssi_6g_mcs[path][gidx];
4051 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4052 enum rtw89_band band = chan->band_type;
4053 u8 ch = chan->channel;
4061 if (band == RTW89_BAND_6G)
4073 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
4074 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
4081 val = tssi_info->tssi_trim[path][tgidx];
4100 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st];
4101 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd];
4108 val = tssi_info->tssi_trim_6g[path][tgidx];
4123 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4124 u8 ch = chan->channel;
4137 h2c->curr_tssi_trim_de[i] = trim_de;
4143 cck_de = tssi_info->tssi_cck[i][gidx];
4146 h2c->curr_tssi_cck_de[i] = 0x0;
4147 h2c->curr_tssi_cck_de_20m[i] = val;
4148 h2c->curr_tssi_cck_de_40m[i] = val;
4149 h2c->curr_tssi_efuse_cck_de[i] = cck_de;
4157 h2c->curr_tssi_ofdm_de[i] = 0x0;
4158 h2c->curr_tssi_ofdm_de_20m[i] = val;
4159 h2c->curr_tssi_ofdm_de_40m[i] = val;
4160 h2c->curr_tssi_ofdm_de_80m[i] = val;
4161 h2c->curr_tssi_ofdm_de_160m[i] = val;
4162 h2c->curr_tssi_ofdm_de_320m[i] = val;
4163 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de;
4175 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
4176 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4179 u8 subband = chan->subband_type;
4188 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0];
4189 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0];
4190 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0];
4191 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0];
4194 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0];
4195 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0];
4196 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0];
4197 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0];
4200 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1];
4201 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1];
4202 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1];
4203 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1];
4206 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2];
4207 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2];
4208 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2];
4209 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2];
4213 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0];
4214 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0];
4215 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0];
4216 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0];
4220 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1];
4221 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1];
4222 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1];
4223 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1];
4227 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2];
4228 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2];
4229 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2];
4230 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2];
4234 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3];
4235 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3];
4236 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3];
4237 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3];
4245 thermal = tssi_info->thermal[path];
4250 h2c->pg_thermal[path] = 0x38;
4251 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path]));
4255 h2c->pg_thermal[path] = thermal;
4261 thm_up[path][DELTA_SWINGIDX_SIZE - 1];
4264 for (j = 127; j >= 64; j--)
4266 -thm_down[path][i++] :
4267 -thm_down[path][DELTA_SWINGIDX_SIZE - 1];
4270 h2c->ftable[path][i + 0] = thm_ofst[i + 3];
4271 h2c->ftable[path][i + 1] = thm_ofst[i + 2];
4272 h2c->ftable[path][i + 2] = thm_ofst[i + 1];
4273 h2c->ftable[path][i + 3] = thm_ofst[i + 0];
4285 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4289 reg_mask = xtal->sc_xo_mask;
4291 reg_mask = xtal->sc_xi_mask;
4293 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask);
4299 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4303 reg_mask = xtal->sc_xo_mask;
4305 reg_mask = xtal->sc_xi_mask;
4307 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val);
4313 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4314 const struct rtw89_chip_info *chip = rtwdev->chip;
4317 if (!force && cfo->crystal_cap == crystal_cap)
4319 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) {
4332 cfo->crystal_cap = sc_xi_val;
4333 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap);
4338 cfo->x_cap_ofst);
4344 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4347 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK;
4348 cfo->is_adjust = false;
4349 if (cfo->crystal_cap == cfo->def_x_cap)
4351 cap = cfo->crystal_cap;
4352 cap += (cap > cfo->def_x_cap ? -1 : 1);
4355 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap,
4356 cfo->def_x_cap);
4361 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp;
4362 bool is_linked = rtwdev->total_sta_assoc > 0;
4367 if (rtwdev->chip->chip_id == RTL8922A)
4379 sign = curr_cfo > 0 ? 1 : -1;
4382 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
4383 cfo_avg_312 = -cfo_avg_312;
4384 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask,
4390 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4391 const struct rtw89_chip_info *chip = rtwdev->chip;
4392 const struct rtw89_cfo_regs *cfo = phy->cfo;
4394 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1);
4395 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8);
4397 if (chip->chip_gen == RTW89_CHIP_AX) {
4398 if (chip->cfo_hw_comp) {
4411 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4412 struct rtw89_efuse *efuse = &rtwdev->efuse;
4414 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK;
4415 cfo->crystal_cap = cfo->crystal_cap_default;
4416 cfo->def_x_cap = cfo->crystal_cap;
4417 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f);
4418 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1);
4419 cfo->is_adjust = false;
4420 cfo->divergence_lock_en = false;
4421 cfo->x_cap_ofst = 0;
4422 cfo->lock_cnt = 0;
4423 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE;
4424 cfo->apply_compensation = false;
4425 cfo->residual_cfo_acc = 0;
4427 cfo->crystal_cap_default);
4428 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
4430 cfo->cfo_timer_ms = 2000;
4431 cfo->cfo_trig_by_timer_en = false;
4432 cfo->phy_cfo_trk_cnt = 0;
4433 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4434 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE;
4440 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4441 int crystal_cap = cfo->crystal_cap;
4449 if (!cfo->is_adjust) {
4451 cfo->is_adjust = true;
4454 cfo->is_adjust = false;
4456 if (!cfo->is_adjust) {
4460 sign = curr_cfo > 0 ? 1 : -1;
4476 cfo->crystal_cap, cfo->def_x_cap);
4481 const struct rtw89_chip_info *chip = rtwdev->chip;
4482 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4488 if (rtwdev->total_sta_assoc != 1)
4492 if (cfo->cfo_cnt[i] == 0)
4494 cfo_khz_all += cfo->cfo_tail[i];
4495 cfo_cnt_all += cfo->cfo_cnt[i];
4497 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4498 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft,
4511 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4512 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4527 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) {
4530 if (cfo->cfo_cnt[i] == 0)
4532 cfo_khz_all += cfo->cfo_tail[i];
4533 cfo_cnt_all += cfo->cfo_cnt[i];
4540 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) {
4543 if (cfo->cfo_cnt[i] == 0)
4545 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4546 (s32)cfo->cfo_cnt[i]);
4547 cfo_khz_all += cfo->cfo_avg[i];
4550 cfo->cfo_avg[i]);
4552 sta_cnt = rtwdev->total_sta_assoc;
4558 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) {
4560 cfo_tol = cfo->sta_cfo_tolerance;
4563 if (cfo->cfo_cnt[i] != 0) {
4564 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4565 (s32)cfo->cfo_cnt[i]);
4568 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i];
4570 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb);
4571 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub);
4572 cfo_khz_all += cfo->cfo_avg[i];
4576 i, cfo->cfo_avg[i]);
4577 if (sta_cnt >= rtwdev->total_sta_assoc)
4580 tp_all = stats->rx_throughput; /* need tp for each entry */
4595 min_cfo_ub - max_cfo_lb);
4599 "No intersection of cfo tolerance windows\n");
4603 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4611 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4613 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail));
4614 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt));
4615 cfo->packet_count = 0;
4616 cfo->packet_count_pre = 0;
4617 cfo->cfo_avg_pre = 0;
4622 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4625 u8 pre_x_cap = cfo->crystal_cap;
4626 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft;
4628 cfo->dcfo_avg = 0;
4630 rtwdev->total_sta_assoc);
4631 if (rtwdev->total_sta_assoc == 0) {
4635 if (cfo->packet_count == 0) {
4639 if (cfo->packet_count == cfo->packet_count_pre) {
4643 if (rtwdev->total_sta_assoc == 1)
4647 if (cfo->divergence_lock_en) {
4648 cfo->lock_cnt++;
4649 if (cfo->lock_cnt > CFO_PERIOD_CNT) {
4650 cfo->divergence_lock_en = false;
4651 cfo->lock_cnt = 0;
4657 if (cfo->crystal_cap >= cfo->x_cap_ub ||
4658 cfo->crystal_cap <= cfo->x_cap_lb) {
4659 cfo->divergence_lock_en = true;
4665 cfo->cfo_avg_pre = new_cfo;
4666 cfo->dcfo_avg_pre = cfo->dcfo_avg;
4667 x_cap_update = cfo->crystal_cap != pre_x_cap;
4669 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n",
4670 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap,
4671 cfo->x_cap_ofst);
4673 if (cfo->dcfo_avg > 0)
4674 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4676 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4678 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg);
4686 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4688 mutex_lock(&rtwdev->mutex);
4689 if (!cfo->cfo_trig_by_timer_en)
4690 goto out;
4693 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
4694 msecs_to_jiffies(cfo->cfo_timer_ms));
4695 out:
4696 mutex_unlock(&rtwdev->mutex);
4701 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4703 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
4704 msecs_to_jiffies(cfo->cfo_timer_ms));
4709 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4710 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4713 if (stats->rx_tf_periodic > CFO_TF_CNT_TH)
4715 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE &&
4719 switch (cfo->phy_cfo_status) {
4721 if (stats->tx_throughput >= CFO_TP_UPPER) {
4722 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE;
4723 cfo->cfo_trig_by_timer_en = true;
4724 cfo->cfo_timer_ms = CFO_COMP_PERIOD;
4729 if (stats->tx_throughput <= CFO_TP_LOWER)
4730 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4732 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT)
4733 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD;
4735 cfo->phy_cfo_trk_cnt++;
4737 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) {
4738 cfo->phy_cfo_trk_cnt = 0;
4739 cfo->cfo_trig_by_timer_en = false;
4743 if (stats->tx_throughput <= CFO_TP_LOWER) {
4744 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4745 cfo->phy_cfo_trk_cnt = 0;
4746 cfo->cfo_trig_by_timer_en = false;
4748 cfo->phy_cfo_trk_cnt++;
4752 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4753 cfo->phy_cfo_trk_cnt = 0;
4758 stats->tx_throughput, cfo->phy_cfo_status,
4759 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt,
4760 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0]));
4761 if (cfo->cfo_trig_by_timer_en)
4769 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4770 u8 macid = phy_ppdu->mac_id;
4773 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid);
4777 cfo->cfo_tail[macid] += cfo_val;
4778 cfo->cfo_cnt[macid]++;
4779 cfo->packet_count++;
4784 const struct rtw89_chip_info *chip = rtwdev->chip;
4786 rtwvif_link->chanctx_idx);
4787 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4789 if (!chip->ul_tb_waveform_ctrl)
4792 rtwvif_link->def_tri_idx =
4795 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV)
4796 rtwvif_link->dyn_tb_bedge_en = false;
4797 else if (chan->band_type >= RTW89_BAND_5G &&
4798 chan->band_width >= RTW89_CHANNEL_WIDTH_40)
4799 rtwvif_link->dyn_tb_bedge_en = true;
4801 rtwvif_link->dyn_tb_bedge_en = false;
4805 ul_tb_info->def_if_bandedge, rtwvif_link->def_tri_idx);
4808 rtwvif_link->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en);
4839 if (!rtwdev->chip->ul_tb_pwr_diff)
4842 if (rtwvif_link->pwr_diff_en == rtwvif_link->pre_pwr_diff_en) {
4843 rtwvif_link->pwr_diff_en = false;
4847 rtwvif_link->pre_pwr_diff_en = rtwvif_link->pwr_diff_en;
4848 param = &table[rtwvif_link->pwr_diff_en];
4851 param->q_00);
4853 param->q_11);
4855 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en);
4857 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif_link->mac_idx);
4859 param->ultb_1t_norm_160);
4861 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif_link->mac_idx);
4863 param->ultb_2t_norm_160);
4865 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif_link->mac_idx);
4867 param->com1_norm_1sts);
4869 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif_link->mac_idx);
4871 param->com2_resp_1sts_path);
4879 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4882 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
4885 if (!vif->cfg.assoc)
4888 if (rtwdev->chip->ul_tb_waveform_ctrl) {
4889 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH)
4890 ul_tb_data->high_tf_client = true;
4891 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH)
4892 ul_tb_data->low_tf_client = true;
4894 ul_tb_data->valid = true;
4895 ul_tb_data->def_tri_idx = rtwvif_link->def_tri_idx;
4896 ul_tb_data->dyn_tb_bedge_en = rtwvif_link->dyn_tb_bedge_en;
4905 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4907 if (!rtwdev->chip->ul_tb_waveform_ctrl)
4910 if (ul_tb_data->dyn_tb_bedge_en) {
4911 if (ul_tb_data->high_tf_client) {
4915 } else if (ul_tb_data->low_tf_client) {
4917 ul_tb_info->def_if_bandedge);
4920 ul_tb_info->def_if_bandedge);
4924 if (ul_tb_info->dyn_tb_tri_en) {
4925 if (ul_tb_data->high_tf_client) {
4930 } else if (ul_tb_data->low_tf_client) {
4933 ul_tb_data->def_tri_idx);
4936 ul_tb_data->def_tri_idx);
4943 const struct rtw89_chip_info *chip = rtwdev->chip;
4949 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff)
4952 if (rtwdev->total_sta_assoc != 1)
4967 const struct rtw89_chip_info *chip = rtwdev->chip;
4968 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4970 if (!chip->ul_tb_waveform_ctrl)
4973 ul_tb_info->dyn_tb_tri_en = true;
4974 ul_tb_info->def_if_bandedge =
4981 ewma_rssi_init(&antdiv_sts->cck_rssi_avg);
4982 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg);
4983 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg);
4984 antdiv_sts->pkt_cnt_cck = 0;
4985 antdiv_sts->pkt_cnt_ofdm = 0;
4986 antdiv_sts->pkt_cnt_non_legacy = 0;
4987 antdiv_sts->evm = 0;
4994 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) {
4995 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) {
4996 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg);
4997 stats->pkt_cnt_cck++;
4999 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg);
5000 stats->pkt_cnt_ofdm++;
5001 stats->evm += phy_ppdu->ofdm.evm_min;
5004 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg);
5005 stats->pkt_cnt_non_legacy++;
5006 stats->evm += phy_ppdu->ofdm.evm_min;
5012 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck &&
5013 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm)
5014 return ewma_rssi_read(&stats->non_legacy_rssi_avg);
5015 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck &&
5016 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy)
5017 return ewma_rssi_read(&stats->ofdm_rssi_avg);
5019 return ewma_rssi_read(&stats->cck_rssi_avg);
5024 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm);
5030 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5031 struct rtw89_hal *hal = &rtwdev->hal;
5033 if (!hal->ant_diversity || hal->ant_diversity_fixed)
5036 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats);
5038 if (!antdiv->get_stats)
5041 if (hal->antenna_rx == RF_A)
5042 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats);
5043 else if (hal->antenna_rx == RF_B)
5044 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats);
5077 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5079 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
5080 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats);
5081 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats);
5086 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5087 struct rtw89_hal *hal = &rtwdev->hal;
5089 if (!hal->ant_diversity)
5092 antdiv->get_stats = false;
5093 antdiv->rssi_pre = 0;
5100 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5101 struct rtw89_hal *hal = &rtwdev->hal;
5102 u8 th_max = phystat->last_thermal_max;
5103 u8 lv = hal->thermal_prot_lv;
5105 if (!hal->thermal_prot_th ||
5106 (hal->disabled_dm_bitmap & BIT(RTW89_DM_THERMAL_PROTECT)))
5109 if (th_max > hal->thermal_prot_th && lv < RTW89_THERMAL_PROT_LV_MAX)
5111 else if (th_max < hal->thermal_prot_th - 2 && lv > 0)
5112 lv--;
5116 hal->thermal_prot_lv = lv;
5120 rtw89_fw_h2c_tx_duty(rtwdev, hal->thermal_prot_lv);
5125 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5129 for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
5132 ewma_thermal_add(&phystat->avg_thermal[i], th);
5136 ewma_thermal_read(&phystat->avg_thermal[i]));
5141 phystat->last_thermal_max = th_max;
5154 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info;
5157 rssi_curr = ewma_rssi_read(&rtwsta_link->avg_rssi);
5159 if (rssi_curr < ch_info->rssi_min) {
5160 ch_info->rssi_min = rssi_curr;
5161 ch_info->rssi_min_macid = rtwsta_link->mac_id;
5164 if (rtwsta_link->prev_rssi == 0) {
5165 rtwsta_link->prev_rssi = rssi_curr;
5166 } else if (abs((int)rtwsta_link->prev_rssi - (int)rssi_curr) >
5168 rtwsta_link->prev_rssi = rssi_curr;
5169 rssi_data->rssi_changed = true;
5191 rssi_data.ch_info = &rtwdev->ch_info;
5192 rssi_data.ch_info->rssi_min = U8_MAX;
5193 ieee80211_iterate_stations_atomic(rtwdev->hw,
5202 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5205 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
5206 ewma_thermal_init(&phystat->avg_thermal[i]);
5210 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5211 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat));
5213 ewma_rssi_init(&phystat->bcn_rssi);
5215 rtwdev->hal.thermal_prot_lv = 0;
5220 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5226 phystat->last_pkt_stat = phystat->cur_pkt_stat;
5227 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5232 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5234 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5239 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5241 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5246 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5247 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5248 const struct rtw89_ccx_regs *ccx = phy->ccx;
5250 env->ccx_manual_ctrl = false;
5251 env->ccx_ongoing = false;
5252 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5253 env->ccx_period = 0;
5254 env->ccx_unit_idx = RTW89_CCX_32_US;
5256 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1);
5257 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1);
5258 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
5259 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask,
5266 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5270 numer = report * score + (env->ccx_period >> 1);
5271 if (env->ccx_period)
5272 ret = numer / env->ccx_period;
5274 return ret >= score ? score - 1 : ret;
5308 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5311 "lv:(%d)->(0)\n", env->ccx_rac_lv);
5313 env->ccx_ongoing = false;
5314 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5315 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5321 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5322 bool is_update = env->ifs_clm_app != para->ifs_clm_app;
5324 u16 *ifs_th_l = env->ifs_clm_th_l;
5325 u16 *ifs_th_h = env->ifs_clm_th_h;
5332 switch (para->ifs_clm_app) {
5343 ifs_th0_us = para->ifs_clm_manual_th0;
5344 ifs_th_times = para->ifs_clm_manual_th_times;
5351 * low[i] = high[i-1] + 1
5352 * high[i] = high[i-1] * ifs_th_times
5359 ifs_th_l[i] = ifs_th_h[i - 1] + 1;
5360 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times;
5374 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5375 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5376 const struct rtw89_ccx_regs *ccx = phy->ccx;
5379 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask,
5380 env->ifs_clm_th_l[0]);
5381 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask,
5382 env->ifs_clm_th_l[1]);
5383 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask,
5384 env->ifs_clm_th_l[2]);
5385 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask,
5386 env->ifs_clm_th_l[3]);
5388 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask,
5389 env->ifs_clm_th_h[0]);
5390 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask,
5391 env->ifs_clm_th_h[1]);
5392 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask,
5393 env->ifs_clm_th_h[2]);
5394 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask,
5395 env->ifs_clm_th_h[3]);
5400 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]);
5405 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5406 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5407 const struct rtw89_ccx_regs *ccx = phy->ccx;
5410 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5411 env->ifs_clm_mntr_time = 0;
5417 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true);
5418 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true);
5419 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true);
5420 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true);
5421 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true);
5427 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5433 return -EINVAL;
5437 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing,
5438 env->ccx_rac_lv, level);
5440 if (env->ccx_ongoing) {
5441 if (level <= env->ccx_rac_lv)
5442 ret = -EINVAL;
5444 env->ccx_ongoing = false;
5448 env->ccx_rac_lv = level;
5458 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5459 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5460 const struct rtw89_ccx_regs *ccx = phy->ccx;
5462 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0);
5463 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0);
5464 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1);
5465 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
5467 env->ccx_ongoing = true;
5472 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5476 env->ifs_clm_tx_ratio =
5477 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT);
5478 env->ifs_clm_edcca_excl_cca_ratio =
5479 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca,
5481 env->ifs_clm_cck_fa_ratio =
5482 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT);
5483 env->ifs_clm_ofdm_fa_ratio =
5484 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT);
5485 env->ifs_clm_cck_cca_excl_fa_ratio =
5486 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa,
5488 env->ifs_clm_ofdm_cca_excl_fa_ratio =
5489 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa,
5491 env->ifs_clm_cck_fa_permil =
5492 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL);
5493 env->ifs_clm_ofdm_fa_permil =
5494 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL);
5497 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) {
5498 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
5500 env->ifs_clm_ifs_avg[i] =
5502 env->ifs_clm_avg[i]);
5505 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]);
5506 res += env->ifs_clm_his[i] >> 1;
5507 if (env->ifs_clm_his[i])
5508 res /= env->ifs_clm_his[i];
5511 env->ifs_clm_cca_avg[i] = res;
5515 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
5516 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio);
5518 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n",
5519 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
5521 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n",
5522 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil);
5524 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n",
5525 env->ifs_clm_cck_cca_excl_fa_ratio,
5526 env->ifs_clm_ofdm_cca_excl_fa_ratio);
5531 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
5532 env->ifs_clm_cca_avg[i]);
5537 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5538 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5539 const struct rtw89_ccx_regs *ccx = phy->ccx;
5542 if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
5543 ccx->ifs_cnt_done_mask) == 0) {
5549 env->ifs_clm_tx =
5550 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5551 ccx->ifs_clm_tx_cnt_msk);
5552 env->ifs_clm_edcca_excl_cca =
5553 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5554 ccx->ifs_clm_edcca_excl_cca_fa_mask);
5555 env->ifs_clm_cckcca_excl_fa =
5556 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
5557 ccx->ifs_clm_cckcca_excl_fa_mask);
5558 env->ifs_clm_ofdmcca_excl_fa =
5559 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
5560 ccx->ifs_clm_ofdmcca_excl_fa_mask);
5561 env->ifs_clm_cckfa =
5562 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
5563 ccx->ifs_clm_cck_fa_mask);
5564 env->ifs_clm_ofdmfa =
5565 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
5566 ccx->ifs_clm_ofdm_fa_mask);
5568 env->ifs_clm_his[0] =
5569 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5570 ccx->ifs_t1_his_mask);
5571 env->ifs_clm_his[1] =
5572 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5573 ccx->ifs_t2_his_mask);
5574 env->ifs_clm_his[2] =
5575 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5576 ccx->ifs_t3_his_mask);
5577 env->ifs_clm_his[3] =
5578 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5579 ccx->ifs_t4_his_mask);
5581 env->ifs_clm_avg[0] =
5582 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
5583 ccx->ifs_t1_avg_mask);
5584 env->ifs_clm_avg[1] =
5585 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
5586 ccx->ifs_t2_avg_mask);
5587 env->ifs_clm_avg[2] =
5588 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
5589 ccx->ifs_t3_avg_mask);
5590 env->ifs_clm_avg[3] =
5591 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
5592 ccx->ifs_t4_avg_mask);
5594 env->ifs_clm_cca[0] =
5595 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
5596 ccx->ifs_t1_cca_mask);
5597 env->ifs_clm_cca[1] =
5598 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
5599 ccx->ifs_t2_cca_mask);
5600 env->ifs_clm_cca[2] =
5601 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
5602 ccx->ifs_t3_cca_mask);
5603 env->ifs_clm_cca[3] =
5604 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
5605 ccx->ifs_t4_cca_mask);
5607 env->ifs_clm_total_ifs =
5608 rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
5609 ccx->ifs_total_mask);
5611 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
5612 env->ifs_clm_total_ifs);
5615 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca);
5617 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n",
5618 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa);
5620 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n",
5621 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa);
5626 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i],
5627 env->ifs_clm_avg[i], env->ifs_clm_cca[i]);
5637 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5638 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5639 const struct rtw89_ccx_regs *ccx = phy->ccx;
5643 if (para->mntr_time == 0) {
5646 return -EINVAL;
5649 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv))
5650 return -EINVAL;
5652 if (para->mntr_time != env->ifs_clm_mntr_time) {
5653 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
5655 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
5656 ccx->ifs_clm_period_mask, period);
5657 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
5658 ccx->ifs_clm_cnt_unit_mask,
5662 "Update IFS-CLM time ((%d)) -> ((%d))\n",
5663 env->ifs_clm_mntr_time, para->mntr_time);
5665 env->ifs_clm_mntr_time = para->mntr_time;
5666 env->ccx_period = (u16)period;
5667 env->ccx_unit_idx = (u8)unit_idx;
5671 env->ifs_clm_app = para->ifs_clm_app;
5680 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5684 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL;
5685 if (env->ccx_manual_ctrl) {
5693 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM;
5707 env->ccx_watchdog_result, chk_result);
5716 *ie_page -= 1;
5746 const struct rtw89_chip_info *chip = rtwdev->chip;
5752 if (chip->chip_id == RTL8852A)
5778 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5779 const struct rtw89_physts_regs *physts = phy->physts;
5782 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
5783 physts->dis_trigger_fail_mask, phy_idx);
5784 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
5785 physts->dis_trigger_brk_mask, phy_idx);
5787 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
5788 physts->dis_trigger_fail_mask, phy_idx);
5789 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
5790 physts->dis_trigger_brk_mask, phy_idx);
5826 if (rtwdev->dbcc_en)
5832 const struct rtw89_chip_info *chip = rtwdev->chip;
5833 struct rtw89_dig_info *dig = &rtwdev->dig;
5843 gain_arr = dig->lna_gain_g;
5845 cfg = chip->dig_table->cfg_lna_g;
5849 gain_arr = dig->tia_gain_g;
5851 cfg = chip->dig_table->cfg_tia_g;
5855 gain_arr = dig->lna_gain_a;
5857 cfg = chip->dig_table->cfg_lna_a;
5861 gain_arr = dig->tia_gain_a;
5863 cfg = chip->dig_table->cfg_tia_a;
5870 for (i = 0; i < cfg->size; i++) {
5871 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr,
5872 cfg->table[i].mask);
5884 struct rtw89_dig_info *dig = &rtwdev->dig;
5888 if (!rtwdev->hal.support_igi)
5893 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT);
5894 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK,
5897 dig->ib_pkpwr, dig->ib_pbk);
5911 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info;
5912 struct rtw89_dig_info *dig = &rtwdev->dig;
5913 bool is_linked = rtwdev->total_sta_assoc > 0;
5916 dig->igi_rssi = ch_info->rssi_min >> 1;
5919 dig->igi_rssi = rssi_nolink;
5925 struct rtw89_dig_info *dig = &rtwdev->dig;
5927 bool is_linked = rtwdev->total_sta_assoc > 0;
5930 switch (chan->band_type) {
5932 dig->lna_gain = dig->lna_gain_g;
5933 dig->tia_gain = dig->tia_gain_g;
5935 dig->force_gaincode_idx_en = false;
5936 dig->dyn_pd_th_en = true;
5940 dig->lna_gain = dig->lna_gain_a;
5941 dig->tia_gain = dig->tia_gain_a;
5943 dig->force_gaincode_idx_en = true;
5944 dig->dyn_pd_th_en = true;
5947 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th));
5948 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th));
5957 struct rtw89_dig_info *dig = &rtwdev->dig;
5959 dig->cur_gaincode.lna_idx = LNA_IDX_MAX;
5960 dig->cur_gaincode.tia_idx = TIA_IDX_MAX;
5961 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX;
5962 dig->force_gaincode.lna_idx = LNA_IDX_MAX;
5963 dig->force_gaincode.tia_idx = TIA_IDX_MAX;
5964 dig->force_gaincode.rxb_idx = RXB_IDX_MAX;
5966 dig->dyn_igi_max = igi_max_performance_mode;
5967 dig->dyn_igi_min = dynamic_igi_min;
5968 dig->dyn_pd_th_max = dynamic_pd_threshold_max;
5969 dig->pd_low_th_ofst = pd_low_th_offset;
5970 dig->is_linked_pre = false;
5981 struct rtw89_dig_info *dig = &rtwdev->dig;
5984 if (rssi < dig->igi_rssi_th[0])
5986 else if (rssi < dig->igi_rssi_th[1])
5988 else if (rssi < dig->igi_rssi_th[2])
5990 else if (rssi < dig->igi_rssi_th[3])
5992 else if (rssi < dig->igi_rssi_th[4])
6002 struct rtw89_dig_info *dig = &rtwdev->dig;
6005 if (rssi < dig->igi_rssi_th[0])
6018 struct rtw89_dig_info *dig = &rtwdev->dig;
6019 s8 lna_gain = dig->lna_gain[set->lna_idx];
6020 s8 tia_gain = dig->tia_gain[set->tia_idx];
6025 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi;
6037 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi);
6038 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi);
6039 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set);
6043 rssi, set->lna_idx, set->tia_idx, set->rxb_idx);
6050 struct rtw89_dig_info *dig = &rtwdev->dig;
6051 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
6053 u8 igi_offset = dig->fa_rssi_ofst;
6056 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil;
6058 if (fa_ratio < dig->fa_th[0])
6060 else if (fa_ratio < dig->fa_th[1])
6062 else if (fa_ratio < dig->fa_th[2])
6064 else if (fa_ratio < dig->fa_th[3])
6075 dig->fa_rssi_ofst = igi_offset;
6078 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
6079 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]);
6083 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil,
6084 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil,
6090 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6092 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr,
6093 dig_regs->p0_lna_init.mask, lna_idx);
6094 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr,
6095 dig_regs->p1_lna_init.mask, lna_idx);
6100 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6102 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr,
6103 dig_regs->p0_tia_init.mask, tia_idx);
6104 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr,
6105 dig_regs->p1_tia_init.mask, tia_idx);
6110 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6112 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr,
6113 dig_regs->p0_rxb_init.mask, rxb_idx);
6114 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr,
6115 dig_regs->p1_rxb_init.mask, rxb_idx);
6121 if (!rtwdev->hal.support_igi)
6135 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6137 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr,
6138 dig_regs->p0_p20_pagcugc_en.mask, enable);
6139 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr,
6140 dig_regs->p0_s20_pagcugc_en.mask, enable);
6141 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr,
6142 dig_regs->p1_p20_pagcugc_en.mask, enable);
6143 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr,
6144 dig_regs->p1_s20_pagcugc_en.mask, enable);
6151 struct rtw89_dig_info *dig = &rtwdev->dig;
6153 if (!rtwdev->hal.support_igi)
6156 if (dig->force_gaincode_idx_en) {
6157 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
6161 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi,
6162 &dig->cur_gaincode);
6163 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode);
6171 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6172 enum rtw89_bandwidth cbw = chan->band_width;
6173 struct rtw89_dig_info *dig = &rtwdev->dig;
6174 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst;
6179 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
6199 dig->dyn_pd_th_max = dig->igi_rssi;
6201 final_rssi = min_t(u8, rssi, dig->igi_rssi);
6206 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1;
6215 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg,
6216 dig_regs->pd_lower_bound_mask, pd_val);
6217 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg,
6218 dig_regs->pd_spatial_reuse_en, enable);
6220 if (!rtwdev->hal.support_cckpd)
6223 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
6224 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
6230 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_reg,
6231 dig_regs->bmode_cca_rssi_limit_en, enable);
6232 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_lower_bound_reg,
6233 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val);
6238 struct rtw89_dig_info *dig = &rtwdev->dig;
6240 dig->bypass_dig = false;
6242 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
6252 struct rtw89_dig_info *dig = &rtwdev->dig;
6253 bool is_linked = rtwdev->total_sta_assoc > 0;
6256 if (unlikely(dig->bypass_dig)) {
6257 dig->bypass_dig = false;
6263 if (!dig->is_linked_pre && is_linked) {
6266 dig->igi_fa_rssi = dig->igi_rssi;
6267 } else if (dig->is_linked_pre && !is_linked) {
6270 dig->igi_fa_rssi = dig->igi_rssi;
6272 dig->is_linked_pre = is_linked;
6276 igi_min = max_t(int, dig->igi_rssi - IGI_RSSI_MIN, 0);
6277 dig->dyn_igi_max = min(igi_min + IGI_OFFSET_MAX, igi_max_performance_mode);
6278 dig->dyn_igi_min = max(igi_min, ABS_IGI_MIN);
6280 if (dig->dyn_igi_max >= dig->dyn_igi_min) {
6281 dig->igi_fa_rssi += dig->fa_rssi_ofst;
6282 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min,
6283 dig->dyn_igi_max);
6285 dig->igi_fa_rssi = dig->dyn_igi_max;
6290 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min,
6291 dig->igi_fa_rssi);
6295 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en);
6297 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max)
6306 struct rtw89_hal *hal = &rtwdev->hal;
6310 rssi_a = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_A]);
6311 rssi_b = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_B]);
6320 if (hal->antenna_tx == candidate)
6323 hal->antenna_tx = candidate;
6326 if (hal->antenna_tx == RF_A) {
6329 } else if (hal->antenna_tx == RF_B) {
6338 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6339 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
6349 if (sta->tdls)
6356 rtwvif_link = rtwsta_link->rtwvif_link;
6357 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
6368 struct rtw89_hal *hal = &rtwdev->hal;
6371 if (!hal->tx_path_diversity)
6374 ieee80211_iterate_stations_atomic(rtwdev->hw,
6384 struct rtw89_hal *hal = &rtwdev->hal;
6387 if (!hal->ant_diversity || hal->antenna_tx == 0)
6390 if (hal->antenna_tx == RF_B) {
6410 struct rtw89_hal *hal = &rtwdev->hal;
6412 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A;
6413 hal->antenna_tx = hal->antenna_rx;
6418 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6419 struct rtw89_hal *hal = &rtwdev->hal;
6425 antdiv->get_stats = false;
6426 antdiv->training_count = 0;
6428 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats);
6429 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats);
6430 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats);
6431 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats);
6450 hal->antenna_tx = candidate;
6451 hal->antenna_rx = candidate;
6456 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6459 if (antdiv->training_count % 2 == 0) {
6460 if (antdiv->training_count == 0)
6463 antdiv->get_stats = true;
6466 antdiv->get_stats = false;
6473 antdiv->training_count++;
6474 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work,
6482 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6484 mutex_lock(&rtwdev->mutex);
6486 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) {
6493 mutex_unlock(&rtwdev->mutex);
6498 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6499 struct rtw89_hal *hal = &rtwdev->hal;
6502 if (!hal->ant_diversity || hal->ant_diversity_fixed)
6505 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats);
6506 rssi_pre = antdiv->rssi_pre;
6507 antdiv->rssi_pre = rssi;
6508 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
6510 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH)
6513 antdiv->training_count = 0;
6514 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0);
6525 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6526 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
6530 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) {
6542 rtw89_phy_write32_mask(rtwdev, edcca_regs->tx_collision_t2r_st,
6543 edcca_regs->tx_collision_t2r_st_mask, 0x29);
6582 const struct rtw89_chip_info *chip = rtwdev->chip;
6583 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld;
6584 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
6591 if (!bss_conf->he_support || !vif->cfg.assoc) {
6596 bss_color = bss_conf->he_bss_color.color;
6600 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1,
6602 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT,
6604 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID,
6605 vif->cfg.aid, phy_idx);
6610 return desc->ch != 0;
6619 if (desc->ch != chan->channel)
6622 if (desc->has_band && desc->band != chan->band_type)
6625 if (desc->has_bw && desc->bw != chan->band_width)
6640 if (rfk_chan_is_equivalent(&iter_data->desc, chan))
6641 iter_data->found++;
6650 int sel = -1;
6662 if (!iter_data.found && sel == -1)
6666 if (sel == -1) {
6679 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
6685 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
6691 rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
6697 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
6703 udelay(def->data);
6724 const struct rtw89_reg5_def *p = tbl->defs;
6725 const struct rtw89_reg5_def *end = tbl->defs + tbl->size;
6728 _rfk_handler[p->flag](rtwdev, p);
6809 const struct rtw89_chip_info *chip = rtwdev->chip;
6823 data = chip->tssi_dbw_table->data[bandedge_cfg];
6851 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band)
6857 switch (band) {
6871 rtw89_warn(rtwdev, "Unsupported band %d\n", band);
6875 for (idx = last; idx >= first; idx--)
6880 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch);
6886 (central_ch - rtw89_ch_base_table[idx]) >> 1);
6892 u8 *ch, enum nl80211_band *band)
6900 *band = NL80211_BAND_2GHZ;
6905 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ;
6912 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6913 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
6916 edcca_bak->a =
6917 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level,
6918 edcca_regs->edcca_mask);
6919 edcca_bak->p =
6920 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level,
6921 edcca_regs->edcca_p_mask);
6922 edcca_bak->ppdu =
6923 rtw89_phy_read32_mask(rtwdev, edcca_regs->ppdu_level,
6924 edcca_regs->ppdu_mask);
6926 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6927 edcca_regs->edcca_mask, EDCCA_MAX);
6928 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6929 edcca_regs->edcca_p_mask, EDCCA_MAX);
6930 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
6931 edcca_regs->ppdu_mask, EDCCA_MAX);
6933 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6934 edcca_regs->edcca_mask,
6935 edcca_bak->a);
6936 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6937 edcca_regs->edcca_p_mask,
6938 edcca_bak->p);
6939 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
6940 edcca_regs->ppdu_mask,
6941 edcca_bak->ppdu);
6947 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6957 if (rtwdev->chip->chip_id == RTL8922A)
6958 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6959 edcca_regs->rpt_sel_be_mask, 0);
6961 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6962 edcca_regs->rpt_sel_mask, 0);
6963 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6974 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6975 edcca_regs->rpt_sel_mask, 4);
6976 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6980 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_regs->rpt_a,
6983 if (rtwdev->chip->chip_id == RTL8922A) {
6984 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6985 edcca_regs->rpt_sel_be_mask, 4);
6986 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6992 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6993 edcca_regs->rpt_sel_be_mask, 5);
6994 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
7000 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
7001 edcca_regs->rpt_sel_mask, 0);
7002 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
7006 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
7007 edcca_regs->rpt_sel_mask, 1);
7008 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
7012 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
7013 edcca_regs->rpt_sel_mask, 2);
7014 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
7018 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
7019 edcca_regs->rpt_sel_mask, 3);
7020 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
7044 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info;
7045 bool is_linked = rtwdev->total_sta_assoc > 0;
7046 u8 rssi_min = ch_info->rssi_min >> 1;
7052 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER -
7062 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7063 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
7067 if (th == edcca_bak->th_old)
7070 edcca_bak->th_old = th;
7075 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
7076 edcca_regs->edcca_mask, th);
7077 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
7078 edcca_regs->edcca_p_mask, th);
7079 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
7080 edcca_regs->ppdu_mask, th);
7085 struct rtw89_hal *hal = &rtwdev->hal;
7087 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA))
7099 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7101 switch (rtwdev->mlo_dbcc_mode) {
7133 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7135 switch (rtwdev->mlo_dbcc_mode) {