Lines Matching defs:rtwdev
17 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
19 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
21 return phy->phy0_phy1_offset(rtwdev, addr);
24 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
49 return rtwdev->chip->max_amsdu_limit;
155 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,
198 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
226 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type);
263 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev,
297 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,
304 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
338 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, chan, &fix_giltf_en, &fix_giltf);
382 rtw89_err(rtwdev, "Unknown band type\n");
390 for (i = 0; i < rtwdev->hal.tx_nss; i++)
402 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0);
405 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan);
435 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan);
446 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1;
465 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
471 rtw89_phy_ra_sta_update(rtwdev, sta, false);
478 rtw89_debug(rtwdev, RTW89_DBG_RA,
486 rtw89_fw_h2c_ra(rtwdev, ra, false);
523 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
530 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
552 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
553 u8 tx_nss = rtwdev->hal.tx_nss;
581 sband = rtwdev->hw->wiphy->bands[nl_band];
601 rtw89_debug(rtwdev, RTW89_DBG_RA,
617 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n");
622 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data;
624 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED);
627 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev)
629 ieee80211_iterate_stations_atomic(rtwdev->hw,
631 rtwdev);
634 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta)
641 rtw89_phy_ra_sta_update(rtwdev, sta, csi);
652 rtw89_debug(rtwdev, RTW89_DBG_RA,
659 rtw89_debug(rtwdev, RTW89_DBG_RA,
668 rtw89_fw_h2c_ra(rtwdev, ra, csi);
671 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
741 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
788 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev)
790 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) ||
791 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1);
794 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
797 const struct rtw89_chip_info *chip = rtwdev->chip;
801 if (rf_path >= rtwdev->chip->rf_path_num) {
802 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
810 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask);
816 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev,
825 1, 30, false, rtwdev);
827 rtw89_err(rtwdev, "read rf busy swsi\n");
835 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val);
839 30, false, rtwdev, R_SWSI_V1,
842 rtw89_err(rtwdev, "read swsi busy\n");
846 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask);
849 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
854 if (rf_path >= rtwdev->chip->rf_path_num) {
855 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
860 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
862 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask);
866 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev,
875 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1);
878 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY);
880 rtw89_warn(rtwdev, "poll HWSI is busy\n");
884 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr);
885 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1);
890 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE);
892 rtw89_warn(rtwdev, "read HWSI is busy\n");
897 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK);
899 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0);
904 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev,
909 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
914 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
919 if (rf_path >= rtwdev->chip->rf_path_num) {
920 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
925 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
927 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask);
931 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
934 const struct rtw89_chip_info *chip = rtwdev->chip;
938 if (rf_path >= rtwdev->chip->rf_path_num) {
939 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
947 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data);
956 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev,
966 1, 30, false, rtwdev);
968 rtw89_err(rtwdev, "write rf busy swsi\n");
977 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK,
988 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val);
993 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
998 if (rf_path >= rtwdev->chip->rf_path_num) {
999 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1004 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1006 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data);
1011 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1022 rtwdev, addr_is_idle[rf_path], BIT(29));
1024 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__);
1031 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val);
1037 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1045 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
1050 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val);
1053 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1058 if (rf_path >= rtwdev->chip->rf_path_num) {
1059 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1064 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1066 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data);
1070 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev)
1072 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1;
1075 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
1078 const struct rtw89_chip_info *chip = rtwdev->chip;
1080 chip->ops->bb_reset(rtwdev, phy_idx);
1083 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,
1103 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr);
1108 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr);
1110 rtw89_phy_write32(rtwdev, addr, reg->data);
1131 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev,
1134 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1154 rtw89_warn(rtwdev,
1170 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev,
1173 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1244 rtw89_warn(rtwdev,
1252 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev,
1255 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1271 rtw89_warn(rtwdev,
1279 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev,
1282 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1306 rtw89_warn(rtwdev,
1313 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev,
1318 const struct rtw89_chip_info *chip = rtwdev->chip;
1320 struct rtw89_efuse *efuse = &rtwdev->efuse;
1329 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n");
1335 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data);
1338 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data);
1341 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data);
1344 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
1352 rtw89_warn(rtwdev,
1360 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev,
1369 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d",
1379 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev,
1388 rtw89_warn(rtwdev,
1397 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i);
1407 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev,
1418 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100)
1421 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1425 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
1443 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
1444 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1449 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
1454 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
1459 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1464 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,
1546 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
1548 void (*config)(struct rtw89_dev *rtwdev,
1556 u8 rfe = rtwdev->efuse.rfe_type;
1557 u8 cv = rtwdev->hal.cv;
1566 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size,
1569 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv);
1585 rtw89_warn(rtwdev, "failed to load CR %x/%x\n",
1610 config(rtwdev, reg, rf_path, extra_data);
1616 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
1618 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1619 const struct rtw89_chip_info *chip = rtwdev->chip;
1624 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
1625 if (rtwdev->dbcc_en)
1626 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg,
1628 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0);
1632 rtw89_phy_init_reg(rtwdev, bb_gain_table,
1634 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0);
1637 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev)
1639 rtw89_phy_write32(rtwdev, 0x8080, 0x4);
1641 return rtw89_phy_read32(rtwdev, 0x8080);
1644 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
1646 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
1648 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1649 const struct rtw89_chip_info *chip = rtwdev->chip;
1667 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
1668 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
1669 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
1675 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev)
1677 const struct rtw89_chip_info *chip = rtwdev->chip;
1682 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
1683 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
1684 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
1686 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
1688 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
1691 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
1694 1000, false, rtwdev);
1697 rtw89_err(rtwdev, "failed to poll nctl block\n");
1699 rtw89_err(rtwdev, "failed to poll nctl block: ret %d val %#06x\n", ret, val);
1703 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
1705 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1706 const struct rtw89_chip_info *chip = rtwdev->chip;
1709 rtw89_phy_preinit_rf_nctl(rtwdev);
1712 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
1715 rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
1718 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr)
1749 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1752 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1753 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1754 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
1758 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1761 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1762 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1763 return rtw89_phy_read32_mask(rtwdev, addr, mask);
1767 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1770 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
1772 if (!rtwdev->dbcc_en)
1775 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1779 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
1787 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
1808 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
1824 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs);
1829 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
1841 byr_head = &rtwdev->byr[cfg->band][0];
1848 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc);
1855 static s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf)
1857 const struct rtw89_chip_info *chip = rtwdev->chip;
1862 static s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm)
1864 const struct rtw89_chip_info *chip = rtwdev->chip;
1880 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band)
1882 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
1889 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr);
1892 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
1901 byr_head = &rtwdev->byr[band][bw];
1902 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc);
1904 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr);
1907 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
1927 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g);
1932 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel)
1935 return rtw89_channel_6g_to_idx(rtwdev, channel);
1947 rtw89_warn(rtwdev, "unknown channel: %d\n", channel);
1952 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
1955 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
1959 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
1962 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
1963 u8 regd = rtw89_regd_get(rtwdev, band);
1993 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
1997 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt);
1998 sar = rtw89_query_sar(rtwdev, freq);
1999 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2009 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \
2016 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev,
2031 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev,
2052 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev,
2093 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev,
2180 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2194 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch);
2197 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch,
2201 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch,
2205 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch,
2211 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
2214 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2218 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2221 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2222 u8 regd = rtw89_regd_get(rtwdev, band);
2252 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2256 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt_ru);
2257 sar = rtw89_query_sar(rtwdev, freq);
2258 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2264 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev,
2268 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2271 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2274 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2280 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev,
2284 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2287 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2290 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2293 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2296 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2299 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2305 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev,
2309 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2312 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2315 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2318 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2321 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2324 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2327 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2330 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2333 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2336 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2339 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2342 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2348 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev,
2361 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2365 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2369 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2377 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
2390 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx,
2394 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx,
2398 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx,
2402 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx,
2408 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev,
2412 u8 max_nss_num = rtwdev->chip->rf_path_num;
2426 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2444 rtw89_phy_read_txpwr_byrate(rtwdev,
2456 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
2465 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev,
2477 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
2480 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
2489 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
2493 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2497 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2505 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2513 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i);
2523 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2528 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
2532 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2540 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2548 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i);
2558 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2564 struct rtw89_dev *rtwdev;
2571 struct rtw89_dev *rtwdev = ra_data->rtwdev;
2576 const struct rtw89_chip_info *chip = rtwdev->chip;
2603 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate);
2616 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw))
2676 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
2681 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2685 ra_data.rtwdev = rtwdev;
2687 ieee80211_iterate_stations_atomic(rtwdev->hw,
2693 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
2700 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev,
2715 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2718 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2721 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2731 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ver=0x%x 0x%x\n",
2733 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n",
2735 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n",
2737 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n",
2739 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n",
2742 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n",
2744 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n",
2746 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n",
2748 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n",
2751 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
2753 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
2756 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
2758 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
2761 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n",
2763 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n",
2766 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic: %*ph\n",
2768 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc: %*ph\n",
2770 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic: %*ph\n",
2772 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc: %*ph\n",
2780 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2790 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2794 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n",
2796 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n",
2798 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n",
2800 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n",
2803 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n",
2805 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n",
2807 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n",
2809 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n",
2817 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2821 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev,
2825 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
2846 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset],
2853 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
2868 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK))
2888 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func,
2893 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n",
2897 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func,
2910 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2912 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2917 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2919 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2924 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2926 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2931 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2933 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2938 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2940 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2945 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2947 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
2952 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev,
2963 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev)
2965 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
2973 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name,
2976 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
2980 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) {
2988 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name);
2991 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n",
2998 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n",
3001 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %jd ms to complete\n",
3009 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3013 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3020 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3027 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev,
3032 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
3059 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3062 void (*handler)(struct rtw89_dev *rtwdev,
3083 rtw89_info(rtwdev, "c2h class %d not support\n", class);
3087 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class,
3091 handler(rtwdev, skb, len);
3094 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev,
3100 rtw89_phy_rfk_report_prep(rtwdev);
3102 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx);
3106 return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms);
3110 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev,
3117 rtw89_phy_rfk_report_prep(rtwdev);
3119 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, tssi_mode);
3123 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms);
3127 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev,
3133 rtw89_phy_rfk_report_prep(rtwdev);
3135 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx);
3139 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms);
3143 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev,
3149 rtw89_phy_rfk_report_prep(rtwdev);
3151 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx);
3155 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms);
3159 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev,
3165 rtw89_phy_rfk_report_prep(rtwdev);
3167 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx);
3171 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms);
3175 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev,
3181 rtw89_phy_rfk_report_prep(rtwdev);
3183 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx);
3187 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms);
3191 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev,
3197 rtw89_phy_rfk_report_prep(rtwdev);
3199 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx);
3203 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms);
3507 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev,
3512 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3527 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3538 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3544 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3553 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3564 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3570 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3577 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev,
3582 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3597 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3608 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3614 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3624 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3635 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3641 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3649 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev,
3654 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3663 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
3667 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i);
3670 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3682 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3685 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i);
3696 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3701 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev,
3706 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
3707 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3772 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3777 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3806 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3814 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)
3816 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
3824 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask);
3827 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,
3830 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
3838 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val);
3841 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
3844 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
3845 const struct rtw89_chip_info *chip = rtwdev->chip;
3852 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
3853 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
3854 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
3855 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
3857 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO,
3859 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI,
3861 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val);
3862 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val);
3867 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val);
3868 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val);
3869 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n",
3871 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n");
3874 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev)
3876 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
3885 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false);
3886 rtw89_debug(rtwdev, RTW89_DBG_CFO,
3891 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo)
3893 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp;
3894 bool is_linked = rtwdev->total_sta_assoc > 0;
3899 if (rtwdev->chip->chip_id == RTL8922A)
3903 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n",
3907 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo);
3910 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO);
3913 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312);
3914 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
3916 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask,
3920 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)
3922 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
3923 const struct rtw89_chip_info *chip = rtwdev->chip;
3926 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1);
3927 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8);
3931 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2,
3934 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
3935 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2,
3941 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)
3943 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
3944 struct rtw89_efuse *efuse = &rtwdev->efuse;
3958 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n",
3960 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
3961 rtw89_dcfo_comp_init(rtwdev);
3969 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev,
3972 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
3978 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n");
3989 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n");
4003 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false);
4004 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4009 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev)
4011 const struct rtw89_chip_info *chip = rtwdev->chip;
4012 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4018 if (rtwdev->total_sta_assoc != 1)
4020 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n");
4031 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4033 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4039 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev)
4041 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4042 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4056 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n");
4058 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n");
4065 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4071 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n");
4078 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4082 sta_cnt = rtwdev->total_sta_assoc;
4084 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4089 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n");
4104 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4107 if (sta_cnt >= rtwdev->total_sta_assoc)
4113 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n",
4115 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n",
4117 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4120 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n",
4123 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4128 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4135 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo);
4139 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev)
4141 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4150 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev)
4152 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4156 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft;
4159 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n",
4160 rtwdev->total_sta_assoc);
4161 if (rtwdev->total_sta_assoc == 0) {
4162 rtw89_phy_cfo_reset(rtwdev);
4166 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n");
4170 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n");
4173 if (rtwdev->total_sta_assoc == 1)
4174 new_cfo = rtw89_phy_average_cfo_calc(rtwdev);
4176 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev);
4183 rtw89_phy_cfo_reset(rtwdev);
4190 rtw89_phy_cfo_reset(rtwdev);
4194 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo);
4198 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update);
4199 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n",
4208 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg);
4209 rtw89_phy_cfo_statistics_reset(rtwdev);
4214 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4216 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4218 mutex_lock(&rtwdev->mutex);
4221 rtw89_leave_ps_mode(rtwdev);
4222 rtw89_phy_cfo_dm(rtwdev);
4223 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
4226 mutex_unlock(&rtwdev->mutex);
4229 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev)
4231 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4233 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
4237 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev)
4239 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4240 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4255 rtw89_phy_cfo_start_work(rtwdev);
4286 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4290 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0]));
4293 rtw89_phy_cfo_dm(rtwdev);
4296 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
4299 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4303 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid);
4312 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4314 const struct rtw89_chip_info *chip = rtwdev->chip;
4315 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
4317 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4323 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG);
4325 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV)
4333 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4336 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4359 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev,
4369 if (!rtwdev->chip->ul_tb_pwr_diff)
4380 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL,
4382 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL,
4384 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX,
4387 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif->mac_idx);
4388 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160,
4391 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif->mac_idx);
4392 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160,
4395 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif->mac_idx);
4396 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS,
4399 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif->mac_idx);
4400 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH,
4405 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev,
4409 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4418 if (rtwdev->chip->ul_tb_waveform_ctrl) {
4429 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif);
4432 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev,
4435 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4437 if (!rtwdev->chip->ul_tb_waveform_ctrl)
4442 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0);
4443 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4446 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN,
4448 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4456 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
4458 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4461 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
4464 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4471 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev)
4473 const struct rtw89_chip_info *chip = rtwdev->chip;
4480 if (rtwdev->total_sta_assoc != 1)
4483 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4484 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data);
4489 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data);
4492 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev)
4494 const struct rtw89_chip_info *chip = rtwdev->chip;
4495 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4502 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN);
4517 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev,
4521 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) {
4554 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
4557 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
4558 struct rtw89_hal *hal = &rtwdev->hal;
4563 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats);
4569 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats);
4571 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats);
4574 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev)
4576 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN,
4578 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL,
4581 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND,
4583 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT,
4586 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN,
4589 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING,
4592 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX,
4594 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL,
4596 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G,
4598 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G,
4602 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev)
4604 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
4611 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev)
4613 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
4614 struct rtw89_hal *hal = &rtwdev->hal;
4621 rtw89_phy_antdiv_sts_reset(rtwdev);
4622 rtw89_phy_antdiv_reg_init(rtwdev);
4625 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
4627 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
4631 for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
4632 th = rtw89_chip_get_thermal(rtwdev, i);
4636 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
4643 struct rtw89_dev *rtwdev;
4672 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)
4676 rssi_data.rtwdev = rtwdev;
4677 rssi_data.ch_info = &rtwdev->ch_info;
4679 ieee80211_iterate_stations_atomic(rtwdev->hw,
4683 rtw89_btc_ntfy_wl_sta(rtwdev);
4686 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
4688 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
4691 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
4694 rtw89_phy_stat_thermal_update(rtwdev);
4700 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
4702 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
4704 rtw89_phy_stat_thermal_update(rtwdev);
4705 rtw89_phy_stat_rssi_update(rtwdev);
4711 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us)
4713 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4718 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx)
4720 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4725 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev)
4727 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4728 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4737 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1);
4738 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1);
4739 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
4740 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask,
4744 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report,
4747 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4758 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev,
4782 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4787 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev)
4789 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4791 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4799 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,
4802 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4837 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev,
4842 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]);
4847 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4853 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev)
4855 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4856 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4860 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask,
4862 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask,
4864 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask,
4866 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask,
4869 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask,
4871 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask,
4873 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask,
4875 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask,
4879 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4884 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev)
4886 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4887 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4895 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶))
4896 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
4898 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true);
4899 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true);
4900 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true);
4901 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true);
4902 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true);
4905 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
4908 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4912 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4917 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4931 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n",
4937 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev)
4939 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4940 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4943 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0);
4944 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0);
4945 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1);
4946 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
4951 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev)
4953 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
4958 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT);
4960 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca,
4963 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT);
4965 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT);
4967 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa,
4970 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa,
4973 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL);
4975 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL);
4982 rtw89_phy_ccx_idx_to_us(rtwdev,
4986 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]);
4995 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
4998 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5001 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5004 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5008 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5011 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n",
5016 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev)
5018 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5019 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5023 if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
5025 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5031 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5034 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5037 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
5040 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
5043 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
5046 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
5050 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5053 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5056 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5059 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5063 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
5066 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
5069 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
5072 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
5076 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
5079 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
5082 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
5085 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
5089 rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
5092 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
5094 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5097 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5100 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5104 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n");
5106 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5110 rtw89_phy_ifs_clm_get_utility(rtwdev);
5115 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
5118 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5119 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5125 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5130 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv))
5134 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
5136 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
5138 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
5142 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5151 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) {
5153 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
5159 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev)
5161 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5167 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5173 if (rtw89_phy_ifs_clm_get_result(rtwdev))
5176 rtw89_phy_ccx_racing_release(rtwdev);
5181 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0)
5184 rtw89_phy_ccx_trigger(rtwdev);
5186 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5209 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev,
5219 return rtw89_phy_read32(rtwdev, addr);
5222 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev,
5226 const struct rtw89_chip_info *chip = rtwdev->chip;
5236 rtw89_phy_write32(rtwdev, addr, val);
5239 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev,
5244 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap);
5251 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val);
5254 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev,
5258 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5262 rtw89_phy_write32_clr(rtwdev, physts->setting_addr,
5264 rtw89_phy_write32_clr(rtwdev, physts->setting_addr,
5267 rtw89_phy_write32_set(rtwdev, physts->setting_addr,
5269 rtw89_phy_write32_set(rtwdev, physts->setting_addr,
5274 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
5278 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0);
5282 rtw89_physts_enable_ie_bitmap(rtwdev, i,
5288 rtw89_physts_enable_ie_bitmap(rtwdev, i,
5292 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT,
5294 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT,
5298 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT,
5302 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type)
5304 const struct rtw89_chip_info *chip = rtwdev->chip;
5305 struct rtw89_dig_info *dig = &rtwdev->dig;
5343 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr,
5349 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n",
5354 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev)
5356 struct rtw89_dig_info *dig = &rtwdev->dig;
5360 if (!rtwdev->hal.support_igi)
5363 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW,
5366 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK,
5368 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n",
5372 rtw89_phy_dig_read_gain_table(rtwdev, i);
5381 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev)
5383 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info;
5384 struct rtw89_dig_info *dig = &rtwdev->dig;
5385 bool is_linked = rtwdev->total_sta_assoc > 0;
5390 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
5395 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev)
5397 struct rtw89_dig_info *dig = &rtwdev->dig;
5398 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
5399 bool is_linked = rtwdev->total_sta_assoc > 0;
5427 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev)
5429 struct rtw89_dig_info *dig = &rtwdev->dig;
5445 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev)
5447 rtw89_phy_dig_update_gain_para(rtwdev);
5448 rtw89_phy_dig_reset(rtwdev);
5451 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
5453 struct rtw89_dig_info *dig = &rtwdev->dig;
5472 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
5474 struct rtw89_dig_info *dig = &rtwdev->dig;
5487 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
5490 struct rtw89_dig_info *dig = &rtwdev->dig;
5500 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n",
5506 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
5509 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi);
5510 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi);
5511 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set);
5513 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5520 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev)
5522 struct rtw89_dig_info *dig = &rtwdev->dig;
5523 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5549 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5553 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5560 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx)
5562 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
5564 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr,
5566 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr,
5570 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx)
5572 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
5574 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr,
5576 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr,
5580 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx)
5582 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
5584 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr,
5586 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr,
5590 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
5593 if (!rtwdev->hal.support_igi)
5596 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx);
5597 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx);
5598 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx);
5600 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n",
5604 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,
5607 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
5609 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr,
5611 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr,
5613 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr,
5615 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr,
5618 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable);
5621 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev)
5623 struct rtw89_dig_info *dig = &rtwdev->dig;
5625 if (!rtwdev->hal.support_igi)
5629 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
5630 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5633 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi,
5635 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode);
5639 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
5642 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
5643 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
5645 struct rtw89_dig_info *dig = &rtwdev->dig;
5651 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
5679 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5683 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5687 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg,
5689 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg,
5692 if (!rtwdev->hal.support_cckpd)
5698 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5702 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_reg,
5704 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_lower_bound_reg,
5708 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev)
5710 struct rtw89_dig_info *dig = &rtwdev->dig;
5713 rtw89_phy_dig_para_reset(rtwdev);
5714 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
5715 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false);
5716 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
5717 rtw89_phy_dig_update_para(rtwdev);
5721 void rtw89_phy_dig(struct rtw89_dev *rtwdev)
5723 struct rtw89_dig_info *dig = &rtwdev->dig;
5724 bool is_linked = rtwdev->total_sta_assoc > 0;
5732 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n");
5733 rtw89_phy_dig_update_para(rtwdev);
5735 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n");
5736 rtw89_phy_dig_update_para(rtwdev);
5740 rtw89_phy_dig_igi_offset_by_env(rtwdev);
5741 rtw89_phy_dig_update_rssi_info(rtwdev);
5751 rtw89_debug(rtwdev, RTW89_DBG_DIG,
5756 rtw89_phy_dig_config_igi(rtwdev);
5758 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en);
5761 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true);
5763 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
5769 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
5771 struct rtw89_hal *hal = &rtwdev->hal;
5798 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta);
5801 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12);
5802 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11);
5804 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11);
5805 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12);
5809 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev)
5811 struct rtw89_hal *hal = &rtwdev->hal;
5817 ieee80211_iterate_stations_atomic(rtwdev->hw,
5825 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev)
5827 struct rtw89_hal *hal = &rtwdev->hal;
5841 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL,
5843 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI,
5845 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT,
5847 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI,
5851 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev)
5853 struct rtw89_hal *hal = &rtwdev->hal;
5859 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev)
5861 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5862 struct rtw89_hal *hal = &rtwdev->hal;
5889 rtw89_phy_swap_hal_antenna(rtwdev);
5897 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev)
5899 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5904 rtw89_phy_antdiv_sts_reset(rtwdev);
5912 rtw89_phy_swap_hal_antenna(rtwdev);
5913 rtw89_phy_antdiv_set_ant(rtwdev);
5917 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work,
5923 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
5925 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5927 mutex_lock(&rtwdev->mutex);
5930 rtw89_phy_antdiv_training_state(rtwdev);
5932 rtw89_phy_antdiv_decision_state(rtwdev);
5933 rtw89_phy_antdiv_set_ant(rtwdev);
5936 mutex_unlock(&rtwdev->mutex);
5939 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev)
5941 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5942 struct rtw89_hal *hal = &rtwdev->hal;
5957 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0);
5960 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
5962 rtw89_phy_ccx_top_setting_init(rtwdev);
5963 rtw89_phy_ifs_clm_setting_init(rtwdev);
5966 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev)
5968 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
5969 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
5973 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) {
5974 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0);
5975 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2);
5976 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1);
5977 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0);
5978 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0);
5979 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0);
5980 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0);
5981 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1);
5982 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1);
5985 rtw89_phy_write32_mask(rtwdev, edcca_regs->tx_collision_t2r_st,
5989 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
5991 rtw89_phy_stat_init(rtwdev);
5993 rtw89_chip_bb_sethw(rtwdev);
5995 rtw89_phy_env_monitor_init(rtwdev);
5996 rtw89_physts_parsing_init(rtwdev);
5997 rtw89_phy_dig_init(rtwdev);
5998 rtw89_phy_cfo_init(rtwdev);
5999 rtw89_phy_bb_wrap_init(rtwdev);
6000 rtw89_phy_edcca_init(rtwdev);
6001 rtw89_phy_ch_info_init(rtwdev);
6002 rtw89_phy_ul_tb_info_init(rtwdev);
6003 rtw89_phy_antdiv_init(rtwdev);
6004 rtw89_chip_rfe_gpio(rtwdev);
6005 rtw89_phy_antdiv_set_ant(rtwdev);
6007 rtw89_chip_rfk_hw_init(rtwdev);
6008 rtw89_phy_init_rf_nctl(rtwdev);
6009 rtw89_chip_rfk_init(rtwdev);
6010 rtw89_chip_set_txpwr_ctrl(rtwdev);
6011 rtw89_chip_power_trim(rtwdev);
6012 rtw89_chip_cfg_txrx_path(rtwdev);
6015 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif)
6017 const struct rtw89_chip_info *chip = rtwdev->chip;
6027 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1,
6029 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT,
6031 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID,
6073 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
6088 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data);
6094 rtw89_debug(rtwdev, RTW89_DBG_RFK,
6104 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6106 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
6110 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6112 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
6116 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6118 rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
6122 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6124 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
6128 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6134 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = {
6149 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl)
6155 _rfk_handler[p->flag](rtwdev, p);
6176 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev,
6191 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
6192 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val);
6232 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
6236 const struct rtw89_chip_info *chip = rtwdev->chip;
6253 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
6254 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]);
6257 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx);
6258 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg);
6260 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg,
6278 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band)
6298 rtw89_warn(rtwdev, "Unsupported band %d\n", band);
6307 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch);
6318 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
6337 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan)
6339 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6340 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
6344 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level,
6347 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level,
6350 rtw89_phy_read32_mask(rtwdev, edcca_regs->ppdu_level,
6353 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6355 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6357 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
6360 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6363 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6366 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
6372 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev)
6374 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6381 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA))
6384 if (rtwdev->chip->chip_id == RTL8922A)
6385 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6388 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6390 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6401 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6403 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6407 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_regs->rpt_a,
6410 if (rtwdev->chip->chip_id == RTL8922A) {
6411 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6413 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6419 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6421 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6427 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6429 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6433 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6435 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6439 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6441 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6445 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6447 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6452 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6455 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6460 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6464 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6469 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev)
6471 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info;
6472 bool is_linked = rtwdev->total_sta_assoc > 0;
6487 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev)
6489 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6490 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
6493 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev);
6499 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6502 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6504 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6506 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
6510 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev)
6512 struct rtw89_hal *hal = &rtwdev->hal;
6517 rtw89_phy_edcca_thre_calc(rtwdev);
6518 rtw89_phy_edcca_log(rtwdev);
6521 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
6524 rtw89_debug(rtwdev, RTW89_DBG_RFK,
6526 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
6528 switch (rtwdev->mlo_dbcc_mode) {
6555 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
6558 rtw89_debug(rtwdev, RTW89_DBG_RFK,
6560 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
6562 switch (rtwdev->mlo_dbcc_mode) {