Lines Matching +full:txrx +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
8 #include "txrx.h"
11 #define MDIO_PG1_G1 1
16 #define OOBS_SEN_MASK GENMASK(5, 1)
64 #define B_AX_DBI_2LSB GENMASK(1, 0)
89 #define B_AX_CLK_REQ_N BIT(1)
95 #define B_AX_CLK_REQ_SEL_OPT BIT(1)
131 #define B_AX_PCIE_IO_RCY_RTRIG_S1 BIT(1)
158 #define B_AX_GPIO17_INT_EN BIT(1)
163 #define B_AX_GPIO17_INT BIT(1)
199 #define B_AX_RXP1DMA_INT_EN BIT(1)
228 #define B_AX_RXP1DMA_INT BIT(1)
234 #define B_AX_RXMDA_STUCK_IDCT_MSK BIT(1)
240 #define B_AX_RXMDA_STUCK_IDCT BIT(1)
244 #define B_AX_TXDMA_CH11_INT_EN_V1 BIT(1)
295 #define B_BE_PCIE_S1_ACLK_ACT BIT(1)
306 #define B_BE_PCIE_EN_SWENT_L23 BIT(1)
322 #define B_BE_CLK_REQ_N BIT(1)
333 #define B_BE_RTK_PM_SEL_OPT BIT(1)
356 #define B_BE_HS1_IND_INT_EN0 BIT(1)
371 #define B_BE_HS1ISR_IND_INT BIT(1)
396 #define B_BE_PCIE_TX_CH1_IMR0 BIT(1)
421 #define B_BE_PCIE_TX_CH1_ISR BIT(1)
454 #define B_BE_RP0DMA_INT_EN BIT(1)
487 #define B_BE_RP0DMA_INT BIT(1)
512 #define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */
513 #define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */
668 #define B_AX_STOP_RPQ BIT(1)
683 #define B_AX_STOP_CH11 BIT(1)
685 #define B_AX_TX_STOP2_ALL GENMASK(1, 0)
697 #define B_AX_CLR_ACH1_IDX BIT(1)
702 #define B_AX_CLR_RPQ_IDX BIT(1)
704 #define B_AX_RXBD_CLR_ALL GENMASK(1, 0)
707 #define B_AX_CLR_CH11_IDX BIT(1)
709 #define B_AX_TXBD_CLR2_ALL GENMASK(1, 0)
727 #define B_AX_RPQ_BUSY BIT(1)
738 #define B_AX_CH11_BUSY BIT(1)
761 #define B_BE_STOP_CH1 BIT(1)
864 #define AX_RXTIMER_UNIT_128US 1
887 #define B_AX_PCIE_TXBD_LEN0 BIT(1)
891 #define B_AX_CLR_CH11_IDX BIT(1)
896 #define B_AX_LBC_FLAG BIT(1)
900 #define B_AX_CLR_RPQ_IDX BIT(1)
932 #define BE_MIT0_TMR_UNIT_2MS 1
935 #define B_BE_PCIE_MIT0_TX_TMR_MASK GENMASK(1, 0)
965 #define B_BE_PCIE_MIT_TXCH1_EN BIT(1)
979 #define B_BE_SER_L1SUB_IMR BIT(1)
1002 #define B_BE_CLR_CH1_IDX BIT(1)
1010 #define B_BE_CLR_RPQ0_IDX BIT(1)
1037 #define B_BE_CH1_BUSY BIT(1)
1070 #define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0)
1075 #define RTW89_PCIE_BIT_PCI_L11 BIT(1)
1103 PCIE_L0SDLY_2US = 1,
1156 MAC_AX_TX_BURST_32B = 1,
1160 MAC_AX_TX_BURST_V1_128B = 1,
1171 MAC_AX_RX_BURST_32B = 1,
1175 MAC_AX_RX_BURST_V1_128B = 1,
1223 MAC_AX_PCIE_ENABLE = 1,
1376 u32 fs:1, ls:1, tag:13, len:14;
1414 #define TXADDR_INFO_LENTHG_V1_MAX ALIGN_DOWN(BIT(11) - 1, 4)
1543 sizeof(info->status.status_driver_data)); in RTW89_PCI_RX_SKB_CB()
1545 return (struct rtw89_pci_rx_info *)skb->cb; in RTW89_PCI_RX_SKB_CB()
1551 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; in RTW89_PCI_RX_BD()
1552 u8 *head = bd_ring->head; in RTW89_PCI_RX_BD()
1553 u32 desc_size = bd_ring->desc_size; in RTW89_PCI_RX_BD()
1562 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; in rtw89_pci_rxbd_increase()
1564 bd_ring->wp += cnt; in rtw89_pci_rxbd_increase()
1566 if (bd_ring->wp >= bd_ring->len) in rtw89_pci_rxbd_increase()
1567 bd_ring->wp -= bd_ring->len; in rtw89_pci_rxbd_increase()
1574 return (struct rtw89_pci_tx_data *)data->hci_priv; in RTW89_PCI_TX_SKB_CB()
1580 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; in rtw89_pci_get_next_txbd()
1583 head = bd_ring->head; in rtw89_pci_get_next_txbd()
1584 tx_bd = head + bd_ring->wp; in rtw89_pci_get_next_txbd()
1592 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; in rtw89_pci_dequeue_txwd()
1595 txwd = list_first_entry_or_null(&wd_ring->free_pages, in rtw89_pci_dequeue_txwd()
1600 list_del_init(&txwd->list); in rtw89_pci_dequeue_txwd()
1601 txwd->len = 0; in rtw89_pci_dequeue_txwd()
1602 wd_ring->curr_num--; in rtw89_pci_dequeue_txwd()
1611 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; in rtw89_pci_enqueue_txwd()
1613 memset(txwd->vaddr, 0, wd_ring->page_size); in rtw89_pci_enqueue_txwd()
1614 list_add_tail(&txwd->list, &wd_ring->free_pages); in rtw89_pci_enqueue_txwd()
1615 wd_ring->curr_num++; in rtw89_pci_enqueue_txwd()
1674 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_chip_fill_txaddr_info()
1676 return info->fill_txaddr_info(rtwdev, txaddr_info_addr, total_len, in rtw89_chip_fill_txaddr_info()
1683 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; in rtw89_chip_config_intr_mask()
1684 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_chip_config_intr_mask()
1689 rtwpci->low_power = false; in rtw89_chip_config_intr_mask()
1690 rtwpci->under_recovery = false; in rtw89_chip_config_intr_mask()
1693 rtwpci->low_power = false; in rtw89_chip_config_intr_mask()
1696 rtwpci->low_power = true; in rtw89_chip_config_intr_mask()
1699 rtwpci->under_recovery = true; in rtw89_chip_config_intr_mask()
1702 rtwpci->under_recovery = false; in rtw89_chip_config_intr_mask()
1708 rtwpci->low_power, rtwpci->under_recovery); in rtw89_chip_config_intr_mask()
1710 info->config_intr_mask(rtwdev); in rtw89_chip_config_intr_mask()
1716 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_chip_enable_intr()
1718 info->enable_intr(rtwdev, rtwpci); in rtw89_chip_enable_intr()
1724 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_chip_disable_intr()
1726 info->disable_intr(rtwdev, rtwpci); in rtw89_chip_disable_intr()
1734 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_chip_recognize_intrs()
1736 info->recognize_intrs(rtwdev, rtwpci, isrs); in rtw89_chip_recognize_intrs()
1741 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_pci_ops_mac_pre_init()
1742 const struct rtw89_pci_gen_def *gen_def = info->gen_def; in rtw89_pci_ops_mac_pre_init()
1744 return gen_def->mac_pre_init(rtwdev); in rtw89_pci_ops_mac_pre_init()
1749 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_pci_ops_mac_pre_deinit()
1750 const struct rtw89_pci_gen_def *gen_def = info->gen_def; in rtw89_pci_ops_mac_pre_deinit()
1752 if (!gen_def->mac_pre_deinit) in rtw89_pci_ops_mac_pre_deinit()
1755 return gen_def->mac_pre_deinit(rtwdev); in rtw89_pci_ops_mac_pre_deinit()
1760 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_pci_ops_mac_post_init()
1761 const struct rtw89_pci_gen_def *gen_def = info->gen_def; in rtw89_pci_ops_mac_post_init()
1763 return gen_def->mac_post_init(rtwdev); in rtw89_pci_ops_mac_post_init()
1768 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_pci_clr_idx_all()
1769 const struct rtw89_pci_gen_def *gen_def = info->gen_def; in rtw89_pci_clr_idx_all()
1771 gen_def->clr_idx_all(rtwdev); in rtw89_pci_clr_idx_all()
1776 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_pci_reset_bdram()
1777 const struct rtw89_pci_gen_def *gen_def = info->gen_def; in rtw89_pci_reset_bdram()
1779 return gen_def->rst_bdram(rtwdev); in rtw89_pci_reset_bdram()
1784 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_pci_ctrl_txdma_ch()
1785 const struct rtw89_pci_gen_def *gen_def = info->gen_def; in rtw89_pci_ctrl_txdma_ch()
1787 return gen_def->ctrl_txdma_ch(rtwdev, enable); in rtw89_pci_ctrl_txdma_ch()
1792 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_pci_ctrl_txdma_fw_ch()
1793 const struct rtw89_pci_gen_def *gen_def = info->gen_def; in rtw89_pci_ctrl_txdma_fw_ch()
1795 return gen_def->ctrl_txdma_fw_ch(rtwdev, enable); in rtw89_pci_ctrl_txdma_fw_ch()
1800 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_pci_poll_txdma_ch_idle()
1801 const struct rtw89_pci_gen_def *gen_def = info->gen_def; in rtw89_pci_poll_txdma_ch_idle()
1803 return gen_def->poll_txdma_ch_idle(rtwdev); in rtw89_pci_poll_txdma_ch_idle()
1808 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_pci_disable_eq()
1809 const struct rtw89_pci_gen_def *gen_def = info->gen_def; in rtw89_pci_disable_eq()
1811 gen_def->disable_eq(rtwdev); in rtw89_pci_disable_eq()
1816 const struct rtw89_pci_info *info = rtwdev->pci_info; in rtw89_pci_power_wake()
1817 const struct rtw89_pci_gen_def *gen_def = info->gen_def; in rtw89_pci_power_wake()
1819 gen_def->power_wake(rtwdev, pwr_up); in rtw89_pci_power_wake()