Lines Matching +full:0 +full:x1fff
10 #define MDIO_PG0_G1 0
14 #define RAC_CTRL_PPR 0x00
15 #define RAC_ANA03 0x03
17 #define RAC_ANA09 0x09
19 #define RAC_ANA0A 0x0A
21 #define RAC_ANA0B 0x0B
23 #define RAC_ANA0C 0x0C
25 #define RAC_ANA0D 0x0D
28 #define RAC_ANA10 0x10
30 #define ADDR_SEL_VAL 0x3C
31 #define ADDR_SEL_PINOUT_DIS_VAL 0x3C4
33 #define RAC_REG_REV2 0x1B
35 #define PCIE_DPHY_DLY_25US 0x1
36 #define RAC_ANA19 0x19
38 #define RAC_REG_FLD_0 0x1D
40 #define PCIE_AUTOK_4 0x3
41 #define RAC_ANA1E 0x1E
42 #define RAC_ANA1E_G1_VAL 0x66EA
43 #define RAC_ANA1E_G2_VAL 0x6EEA
44 #define RAC_ANA1F 0x1F
47 #define RAC_ANA24 0x24
49 #define RAC_ANA26 0x26
51 #define RAC_ANA2E 0x2E
52 #define RAC_ANA2E_VAL 0xFFFE
53 #define RAC_CTRL_PPR_V1 0x30
57 #define RAC_SET_PPR_V1 0x31
59 #define R_AX_DBI_FLAG 0x1090
64 #define B_AX_DBI_2LSB GENMASK(1, 0)
65 #define R_AX_DBI_WDATA 0x1094
66 #define R_AX_DBI_RDATA 0x1098
68 #define R_AX_MDIO_WDATA 0x10A4
69 #define R_AX_MDIO_RDATA 0x10A6
71 #define R_AX_PCIE_PS_CTRL_V1 0x3008
76 #define B_AX_SEL_REQ_EXIT_L1 BIT(0)
78 #define R_AX_PCIE_MIX_CFG_V1 0x300C
86 #define B_AX_L1SUB_DISABLE BIT(0)
88 #define R_AX_L1_CLK_CTRL 0x3010
91 #define R_AX_PCIE_BG_CLR 0x303C
94 #define R_AX_PCIE_LAT_CTRL 0x3044
96 #define B_AX_CLK_REQ_SEL BIT(0)
98 #define R_AX_PCIE_IO_RCY_M1 0x3100
102 #define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
104 #define R_AX_PCIE_WDT_TIMER_M1 0x3104
105 #define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)
107 #define R_AX_PCIE_IO_RCY_M2 0x310C
111 #define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
113 #define R_AX_PCIE_WDT_TIMER_M2 0x3110
114 #define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)
116 #define R_AX_PCIE_IO_RCY_E0 0x3118
120 #define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
122 #define R_AX_PCIE_WDT_TIMER_E0 0x311C
123 #define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)
125 #define R_AX_PCIE_IO_RCY_S1 0x3124
132 #define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
134 #define R_AX_PCIE_WDT_TIMER_S1 0x3128
135 #define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
137 #define R_RAC_DIRECT_OFFSET_G1 0x3800
139 #define R_RAC_DIRECT_OFFSET_G2 0x3880
143 #define R_RAC_DIRECT_OFFSET_BE_LANE0_G1 0x3800
144 #define R_RAC_DIRECT_OFFSET_BE_LANE1_G1 0x3880
145 #define R_RAC_DIRECT_OFFSET_BE_LANE0_G2 0x3900
146 #define R_RAC_DIRECT_OFFSET_BE_LANE1_G2 0x3980
151 #define R_AX_HIMR0 0x01A0
154 #define R_AX_HISR0 0x01A4
156 #define R_AX_HIMR1 0x01A8
159 #define B_AX_GPIO16_INT_EN BIT(0)
161 #define R_AX_HISR1 0x01AC
164 #define B_AX_GPIO16_INT BIT(0)
166 #define R_AX_MDIO_CFG 0x10A0
170 #define B_AX_MDIO_ADDR_MASK GENMASK(4, 0)
172 #define R_AX_PCIE_HIMR00 0x10B0
173 #define R_AX_HAXI_HIMR00 0x10B0
200 #define B_AX_RXDMA_INT_EN BIT(0)
202 #define R_AX_PCIE_HISR00 0x10B4
203 #define R_AX_HAXI_HISR00 0x10B4
229 #define B_AX_RXDMA_INT BIT(0)
231 #define R_AX_HAXI_IDCT_MSK 0x10B8
235 #define B_AX_TXMDA_STUCK_IDCT_MSK BIT(0)
237 #define R_AX_HAXI_IDCT 0x10BC
241 #define B_AX_TXMDA_STUCK_IDCT BIT(0)
243 #define R_AX_HAXI_HIMR10 0x11E0
245 #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
247 #define R_AX_PCIE_HIMR10 0x13B0
252 #define R_AX_PCIE_HISR10 0x13B4
257 #define R_AX_PCIE_HIMR00_V1 0x30B0
265 #define R_AX_PCIE_HISR00_V1 0x30B4
273 #define R_BE_PCIE_FRZ_CLK 0x3004
296 #define B_BE_PCIE_EN_AUX_CLK BIT(0)
298 #define R_BE_PCIE_PS_CTRL 0x3008
307 #define B_BE_SEL_REQ_EXIT_L1 BIT(0)
309 #define R_BE_PCIE_MIX_CFG 0x300C
318 #define B_BE_L1SUB_ENABLE BIT(0)
320 #define R_BE_L1_CLK_CTRL 0x3010
323 #define B_BE_CLK_PM_EN BIT(0)
325 #define R_BE_PCIE_LAT_CTRL 0x3044
334 #define B_BE_CLK_REQ_SEL BIT(0)
336 #define R_BE_PCIE_HIMR0 0x30B0
357 #define B_BE_HS0_IND_INT_EN0 BIT(0)
359 #define R_BE_PCIE_HISR 0x30B4
372 #define B_BE_HS0ISR_IND_INT BIT(0)
374 #define R_BE_PCIE_DMA_IMR_0_V1 0x30B8
397 #define B_BE_PCIE_TX_CH0_IMR0 BIT(0)
399 #define R_BE_PCIE_DMA_ISR 0x30BC
422 #define B_BE_PCIE_TX_CH0_ISR BIT(0)
424 #define R_BE_HAXI_HIMR00 0xB0B0
455 #define B_BE_RX0DMA_INT_EN BIT(0)
457 #define R_BE_HAXI_HISR00 0xB0B4
486 #define B_BE_RX0DMA_INT BIT(0)
489 #define R_AX_DRV_FW_HSK_0 0x01B0
490 #define R_AX_DRV_FW_HSK_1 0x01B4
491 #define R_AX_DRV_FW_HSK_2 0x01B8
492 #define R_AX_DRV_FW_HSK_3 0x01BC
493 #define R_AX_DRV_FW_HSK_4 0x01C0
494 #define R_AX_DRV_FW_HSK_5 0x01C4
495 #define R_AX_DRV_FW_HSK_6 0x01C8
496 #define R_AX_DRV_FW_HSK_7 0x01CC
498 #define R_AX_RXQ_RXBD_IDX 0x1050
499 #define R_AX_RPQ_RXBD_IDX 0x1054
500 #define R_AX_ACH0_TXBD_IDX 0x1058
501 #define R_AX_ACH1_TXBD_IDX 0x105C
502 #define R_AX_ACH2_TXBD_IDX 0x1060
503 #define R_AX_ACH3_TXBD_IDX 0x1064
504 #define R_AX_ACH4_TXBD_IDX 0x1068
505 #define R_AX_ACH5_TXBD_IDX 0x106C
506 #define R_AX_ACH6_TXBD_IDX 0x1070
507 #define R_AX_ACH7_TXBD_IDX 0x1074
508 #define R_AX_CH8_TXBD_IDX 0x1078 /* Management Queue band 0 */
509 #define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */
510 #define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */
511 #define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */
512 #define R_AX_CH12_TXBD_IDX 0x1080 /* FWCMD Queue */
513 #define R_AX_CH10_TXBD_IDX_V1 0x11D0
514 #define R_AX_CH11_TXBD_IDX_V1 0x11D4
515 #define R_AX_RXQ_RXBD_IDX_V1 0x1218
516 #define R_AX_RPQ_RXBD_IDX_V1 0x121C
518 #define TXBD_HOST_IDX_MASK GENMASK(11, 0)
520 #define R_AX_ACH0_TXBD_DESA_L 0x1110
521 #define R_AX_ACH0_TXBD_DESA_H 0x1114
522 #define R_AX_ACH1_TXBD_DESA_L 0x1118
523 #define R_AX_ACH1_TXBD_DESA_H 0x111C
524 #define R_AX_ACH2_TXBD_DESA_L 0x1120
525 #define R_AX_ACH2_TXBD_DESA_H 0x1124
526 #define R_AX_ACH3_TXBD_DESA_L 0x1128
527 #define R_AX_ACH3_TXBD_DESA_H 0x112C
528 #define R_AX_ACH4_TXBD_DESA_L 0x1130
529 #define R_AX_ACH4_TXBD_DESA_H 0x1134
530 #define R_AX_ACH5_TXBD_DESA_L 0x1138
531 #define R_AX_ACH5_TXBD_DESA_H 0x113C
532 #define R_AX_ACH6_TXBD_DESA_L 0x1140
533 #define R_AX_ACH6_TXBD_DESA_H 0x1144
534 #define R_AX_ACH7_TXBD_DESA_L 0x1148
535 #define R_AX_ACH7_TXBD_DESA_H 0x114C
536 #define R_AX_CH8_TXBD_DESA_L 0x1150
537 #define R_AX_CH8_TXBD_DESA_H 0x1154
538 #define R_AX_CH9_TXBD_DESA_L 0x1158
539 #define R_AX_CH9_TXBD_DESA_H 0x115C
540 #define R_AX_CH10_TXBD_DESA_L 0x1358
541 #define R_AX_CH10_TXBD_DESA_H 0x135C
542 #define R_AX_CH11_TXBD_DESA_L 0x1360
543 #define R_AX_CH11_TXBD_DESA_H 0x1364
544 #define R_AX_CH12_TXBD_DESA_L 0x1160
545 #define R_AX_CH12_TXBD_DESA_H 0x1164
546 #define R_AX_RXQ_RXBD_DESA_L 0x1100
547 #define R_AX_RXQ_RXBD_DESA_H 0x1104
548 #define R_AX_RPQ_RXBD_DESA_L 0x1108
549 #define R_AX_RPQ_RXBD_DESA_H 0x110C
550 #define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
551 #define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
552 #define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
553 #define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
554 #define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
555 #define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
556 #define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
557 #define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
558 #define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
559 #define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
560 #define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
561 #define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
562 #define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
563 #define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
564 #define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
565 #define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
566 #define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
567 #define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
568 #define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
569 #define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
570 #define R_AX_CH8_TXBD_DESA_L_V1 0x1270
571 #define R_AX_CH8_TXBD_DESA_H_V1 0x1274
572 #define R_AX_CH9_TXBD_DESA_L_V1 0x1278
573 #define R_AX_CH9_TXBD_DESA_H_V1 0x127C
574 #define R_AX_CH12_TXBD_DESA_L_V1 0x1280
575 #define R_AX_CH12_TXBD_DESA_H_V1 0x1284
576 #define R_AX_CH10_TXBD_DESA_L_V1 0x1458
577 #define R_AX_CH10_TXBD_DESA_H_V1 0x145C
578 #define R_AX_CH11_TXBD_DESA_L_V1 0x1460
579 #define R_AX_CH11_TXBD_DESA_H_V1 0x1464
580 #define B_AX_DESC_NUM_MSK GENMASK(11, 0)
582 #define R_AX_RXQ_RXBD_NUM 0x1020
583 #define R_AX_RPQ_RXBD_NUM 0x1022
584 #define R_AX_ACH0_TXBD_NUM 0x1024
585 #define R_AX_ACH1_TXBD_NUM 0x1026
586 #define R_AX_ACH2_TXBD_NUM 0x1028
587 #define R_AX_ACH3_TXBD_NUM 0x102A
588 #define R_AX_ACH4_TXBD_NUM 0x102C
589 #define R_AX_ACH5_TXBD_NUM 0x102E
590 #define R_AX_ACH6_TXBD_NUM 0x1030
591 #define R_AX_ACH7_TXBD_NUM 0x1032
592 #define R_AX_CH8_TXBD_NUM 0x1034
593 #define R_AX_CH9_TXBD_NUM 0x1036
594 #define R_AX_CH10_TXBD_NUM 0x1338
595 #define R_AX_CH11_TXBD_NUM 0x133A
596 #define R_AX_CH12_TXBD_NUM 0x1038
597 #define R_AX_RXQ_RXBD_NUM_V1 0x1210
598 #define R_AX_RPQ_RXBD_NUM_V1 0x1212
599 #define R_AX_CH10_TXBD_NUM_V1 0x1438
600 #define R_AX_CH11_TXBD_NUM_V1 0x143A
602 #define R_AX_ACH0_BDRAM_CTRL 0x1200
603 #define R_AX_ACH1_BDRAM_CTRL 0x1204
604 #define R_AX_ACH2_BDRAM_CTRL 0x1208
605 #define R_AX_ACH3_BDRAM_CTRL 0x120C
606 #define R_AX_ACH4_BDRAM_CTRL 0x1210
607 #define R_AX_ACH5_BDRAM_CTRL 0x1214
608 #define R_AX_ACH6_BDRAM_CTRL 0x1218
609 #define R_AX_ACH7_BDRAM_CTRL 0x121C
610 #define R_AX_CH8_BDRAM_CTRL 0x1220
611 #define R_AX_CH9_BDRAM_CTRL 0x1224
612 #define R_AX_CH10_BDRAM_CTRL 0x1320
613 #define R_AX_CH11_BDRAM_CTRL 0x1324
614 #define R_AX_CH12_BDRAM_CTRL 0x1228
615 #define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
616 #define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
617 #define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
618 #define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
619 #define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
620 #define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
621 #define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
622 #define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
623 #define R_AX_CH8_BDRAM_CTRL_V1 0x1320
624 #define R_AX_CH9_BDRAM_CTRL_V1 0x1324
625 #define R_AX_CH12_BDRAM_CTRL_V1 0x1328
626 #define R_AX_CH10_BDRAM_CTRL_V1 0x1420
627 #define R_AX_CH11_BDRAM_CTRL_V1 0x1424
628 #define BDRAM_SIDX_MASK GENMASK(7, 0)
632 #define R_AX_PCIE_INIT_CFG1 0x1000
649 #define R_AX_TXDMA_ADDR_H 0x10F0
650 #define R_AX_RXDMA_ADDR_H 0x10F4
652 #define R_AX_PCIE_DMA_STOP1 0x1010
667 #define B_AX_STOP_RXQ BIT(0)
680 #define R_AX_PCIE_DMA_STOP2 0x1310
682 #define B_AX_STOP_CH10 BIT(0)
683 #define B_AX_TX_STOP2_ALL GENMASK(1, 0)
685 #define R_AX_TXBD_RWPTR_CLR1 0x1014
696 #define B_AX_CLR_ACH0_IDX BIT(0)
697 #define B_AX_TXBD_CLR1_ALL GENMASK(10, 0)
699 #define R_AX_RXBD_RWPTR_CLR 0x1018
701 #define B_AX_CLR_RXQ_IDX BIT(0)
702 #define B_AX_RXBD_CLR_ALL GENMASK(1, 0)
704 #define R_AX_TXBD_RWPTR_CLR2 0x1314
706 #define B_AX_CLR_CH10_IDX BIT(0)
707 #define B_AX_TXBD_CLR2_ALL GENMASK(1, 0)
709 #define R_AX_PCIE_DMA_BUSY1 0x101C
726 #define B_AX_RXQ_BUSY BIT(0)
735 #define R_AX_PCIE_DMA_BUSY2 0x131C
737 #define B_AX_CH10_BUSY BIT(0)
739 #define R_AX_WP_ADDR_H_SEL0_3 0x1334
740 #define R_AX_WP_ADDR_H_SEL4_7 0x1338
741 #define R_AX_WP_ADDR_H_SEL8_11 0x133C
742 #define R_AX_WP_ADDR_H_SEL12_15 0x1340
744 #define R_BE_HAXI_DMA_STOP1 0xB010
760 #define B_BE_STOP_CH0 BIT(0)
769 #define R_BE_CH0_TXBD_NUM_V1 0xB030
770 #define R_BE_CH1_TXBD_NUM_V1 0xB032
771 #define R_BE_CH2_TXBD_NUM_V1 0xB034
772 #define R_BE_CH3_TXBD_NUM_V1 0xB036
773 #define R_BE_CH4_TXBD_NUM_V1 0xB038
774 #define R_BE_CH5_TXBD_NUM_V1 0xB03A
775 #define R_BE_CH6_TXBD_NUM_V1 0xB03C
776 #define R_BE_CH7_TXBD_NUM_V1 0xB03E
777 #define R_BE_CH8_TXBD_NUM_V1 0xB040
778 #define R_BE_CH9_TXBD_NUM_V1 0xB042
779 #define R_BE_CH10_TXBD_NUM_V1 0xB044
780 #define R_BE_CH11_TXBD_NUM_V1 0xB046
781 #define R_BE_CH12_TXBD_NUM_V1 0xB048
782 #define R_BE_CH13_TXBD_NUM_V1 0xB04C
783 #define R_BE_CH14_TXBD_NUM_V1 0xB04E
785 #define R_BE_RXQ0_RXBD_NUM_V1 0xB050
786 #define R_BE_RPQ0_RXBD_NUM_V1 0xB052
788 #define R_BE_CH0_TXBD_IDX_V1 0xB100
789 #define R_BE_CH1_TXBD_IDX_V1 0xB104
790 #define R_BE_CH2_TXBD_IDX_V1 0xB108
791 #define R_BE_CH3_TXBD_IDX_V1 0xB10C
792 #define R_BE_CH4_TXBD_IDX_V1 0xB110
793 #define R_BE_CH5_TXBD_IDX_V1 0xB114
794 #define R_BE_CH6_TXBD_IDX_V1 0xB118
795 #define R_BE_CH7_TXBD_IDX_V1 0xB11C
796 #define R_BE_CH8_TXBD_IDX_V1 0xB120
797 #define R_BE_CH9_TXBD_IDX_V1 0xB124
798 #define R_BE_CH10_TXBD_IDX_V1 0xB128
799 #define R_BE_CH11_TXBD_IDX_V1 0xB12C
800 #define R_BE_CH12_TXBD_IDX_V1 0xB130
801 #define R_BE_CH13_TXBD_IDX_V1 0xB134
802 #define R_BE_CH14_TXBD_IDX_V1 0xB138
804 #define R_BE_RXQ0_RXBD_IDX_V1 0xB160
805 #define R_BE_RPQ0_RXBD_IDX_V1 0xB164
807 #define R_BE_CH0_TXBD_DESA_L_V1 0xB200
808 #define R_BE_CH0_TXBD_DESA_H_V1 0xB204
809 #define R_BE_CH1_TXBD_DESA_L_V1 0xB208
810 #define R_BE_CH1_TXBD_DESA_H_V1 0xB20C
811 #define R_BE_CH2_TXBD_DESA_L_V1 0xB210
812 #define R_BE_CH2_TXBD_DESA_H_V1 0xB214
813 #define R_BE_CH3_TXBD_DESA_L_V1 0xB218
814 #define R_BE_CH3_TXBD_DESA_H_V1 0xB21C
815 #define R_BE_CH4_TXBD_DESA_L_V1 0xB220
816 #define R_BE_CH4_TXBD_DESA_H_V1 0xB224
817 #define R_BE_CH5_TXBD_DESA_L_V1 0xB228
818 #define R_BE_CH5_TXBD_DESA_H_V1 0xB22C
819 #define R_BE_CH6_TXBD_DESA_L_V1 0xB230
820 #define R_BE_CH6_TXBD_DESA_H_V1 0xB234
821 #define R_BE_CH7_TXBD_DESA_L_V1 0xB238
822 #define R_BE_CH7_TXBD_DESA_H_V1 0xB23C
823 #define R_BE_CH8_TXBD_DESA_L_V1 0xB240
824 #define R_BE_CH8_TXBD_DESA_H_V1 0xB244
825 #define R_BE_CH9_TXBD_DESA_L_V1 0xB248
826 #define R_BE_CH9_TXBD_DESA_H_V1 0xB24C
827 #define R_BE_CH10_TXBD_DESA_L_V1 0xB250
828 #define R_BE_CH10_TXBD_DESA_H_V1 0xB254
829 #define R_BE_CH11_TXBD_DESA_L_V1 0xB258
830 #define R_BE_CH11_TXBD_DESA_H_V1 0xB25C
831 #define R_BE_CH12_TXBD_DESA_L_V1 0xB260
832 #define R_BE_CH12_TXBD_DESA_H_V1 0xB264
833 #define R_BE_CH13_TXBD_DESA_L_V1 0xB268
834 #define R_BE_CH13_TXBD_DESA_H_V1 0xB26C
835 #define R_BE_CH14_TXBD_DESA_L_V1 0xB270
836 #define R_BE_CH14_TXBD_DESA_H_V1 0xB274
838 #define R_BE_RXQ0_RXBD_DESA_L_V1 0xB300
839 #define R_BE_RXQ0_RXBD_DESA_H_V1 0xB304
840 #define R_BE_RPQ0_RXBD_DESA_L_V1 0xB308
841 #define R_BE_RPQ0_RXBD_DESA_H_V1 0xB30C
843 #define R_BE_WP_ADDR_H_SEL0_3_V1 0xB420
844 #define R_BE_WP_ADDR_H_SEL4_7_V1 0xB424
845 #define R_BE_WP_ADDR_H_SEL8_11_V1 0xB428
846 #define R_BE_WP_ADDR_H_SEL12_15_V1 0xB42C
849 #define R_AX_PCIE_INIT_CFG2 0x1004
852 #define B_AX_PCIE_RX_APPLEN_MASK GENMASK(13, 0)
854 #define R_AX_PCIE_PS_CTRL 0x1008
857 #define R_AX_INT_MIT_RX 0x10D4
861 #define AX_RXTIMER_UNIT_64US 0
866 #define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0)
868 #define R_AX_DBG_ERR_FLAG_V1 0x1104
870 #define R_AX_INT_MIT_RX_V1 0x1184
875 #define B_AX_MIT_RXTIMER_MATCH_MASK GENMASK(7, 0)
877 #define R_AX_DBG_ERR_FLAG 0x11C4
886 #define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0)
888 #define R_AX_TXBD_RWPTR_CLR2_V1 0x11C4
890 #define B_AX_CLR_CH10_IDX BIT(0)
892 #define R_AX_LBC_WATCHDOG 0x11D8
895 #define B_AX_LBC_EN BIT(0)
897 #define R_AX_RXBD_RWPTR_CLR_V1 0x1200
899 #define B_AX_CLR_RXQ_IDX BIT(0)
901 #define R_AX_HAXI_EXP_CTRL 0x1204
902 #define B_AX_MAX_TAG_NUM_V1_MASK GENMASK(2, 0)
904 #define R_AX_PCIE_EXP_CTRL 0x13F0
909 #define R_AX_PCIE_RX_PREF_ADV 0x13F4
910 #define B_AX_RXDMA_PREF_ADV_EN BIT(0)
912 #define R_AX_PCIE_HRPWM_V1 0x30C0
913 #define R_AX_PCIE_CRPWM 0x30C4
915 #define R_AX_LBC_WATCHDOG_V1 0x30D8
917 #define R_BE_PCIE_HRPWM 0x30C0
918 #define R_BE_PCIE_CRPWM 0x30C4
920 #define R_BE_L1_2_CTRL_HCILDO 0x3110
921 #define B_BE_PCIE_DIS_L1_2_CTRL_HCILDO BIT(0)
923 #define R_BE_PL1_DBG_INFO 0x3120
925 #define B_BE_START_PL1_CNT_MASK GENMASK(7, 0)
927 #define R_BE_PCIE_MIT0_TMR 0x3330
929 #define BE_MIT0_TMR_UNIT_1MS 0
933 #define B_BE_PCIE_MIT0_TX_TMR_MASK GENMASK(1, 0)
935 #define R_BE_PCIE_MIT0_CNT 0x3334
939 #define B_BE_PCIE_TX_MIT0_TMR_CNT_MASK GENMASK(7, 0)
941 #define R_BE_PCIE_MIT_CH_EN 0x3338
964 #define B_BE_PCIE_MIT_TXCH0_EN BIT(0)
966 #define R_BE_SER_PL1_CTRL 0x34A8
970 #define B_BE_PL1_TIMER_CLEAR BIT(0)
972 #define R_BE_REG_PL1_MASK 0x34B0
978 #define B_BE_SER_PMU_IMR BIT(0)
980 #define R_BE_REG_PL1_ISR 0x34B4
982 #define R_BE_RX_APPEND_MODE 0x8920
984 #define B_BE_APPEND_LEN_MASK GENMASK(15, 0)
986 #define R_BE_TXBD_RWPTR_CLR1 0xB014
1001 #define B_BE_CLR_CH0_IDX BIT(0)
1003 #define R_BE_RXBD_RWPTR_CLR1_V1 0xB018
1009 #define B_BE_CLR_RXQ0_IDX BIT(0)
1011 #define R_BE_HAXI_DMA_BUSY1 0xB01C
1036 #define B_BE_CH0_BUSY BIT(0)
1043 #define R_BE_HAXI_EXP_CTRL_V1 0xB020
1047 #define B_BE_MAX_TAG_NUM_MASK GENMASK(3, 0)
1061 #define RTW89_PCIE_CAPABILITY_SPEED 0x7C
1062 #define RTW89_PCIE_SUPPORT_GEN_MASK GENMASK(3, 0)
1063 #define RTW89_PCIE_L1_STS_V1 0x80
1065 #define RTW89_PCIE_GEN1_SPEED 0x01
1066 #define RTW89_PCIE_GEN2_SPEED 0x02
1067 #define RTW89_PCIE_PHY_RATE 0x82
1068 #define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0)
1069 #define RTW89_PCIE_LINK_CHANGE_SPEED 0xA0
1070 #define RTW89_PCIE_L1SS_STS_V1 0x0168
1074 #define RTW89_PCIE_BIT_PCI_L12 BIT(0)
1075 #define RTW89_PCIE_ASPM_CTRL 0x070F
1077 #define RTW89_L0DLY_MASK GENMASK(2, 0)
1078 #define RTW89_PCIE_TIMER_CTRL 0x0718
1080 #define RTW89_PCIE_L1_CTRL 0x0719
1084 #define RTW89_PCIE_CLK_CTRL 0x0725
1085 #define RTW89_PCIE_FTS 0x080C
1087 #define RTW89_PCIE_RST_MSTATE 0x0B48
1088 #define RTW89_PCIE_BIT_CFG_RST_MSTATE BIT(0)
1096 PCIE_PHY_GEN1_UNDEFINE = 0x7F,
1100 PCIE_L0SDLY_1US = 0,
1117 PCIE_CLKDLY_HW_0 = 0,
1118 PCIE_CLKDLY_HW_30US = 0x1,
1119 PCIE_CLKDLY_HW_50US = 0x2,
1120 PCIE_CLKDLY_HW_100US = 0x3,
1121 PCIE_CLKDLY_HW_150US = 0x4,
1122 PCIE_CLKDLY_HW_200US = 0x5,
1126 PCIE_CLKDLY_HW_V1_0 = 0,
1127 PCIE_CLKDLY_HW_V1_16US = 0x1,
1128 PCIE_CLKDLY_HW_V1_32US = 0x2,
1129 PCIE_CLKDLY_HW_V1_64US = 0x3,
1130 PCIE_CLKDLY_HW_V1_80US = 0x4,
1131 PCIE_CLKDLY_HW_V1_96US = 0x5,
1137 MAC_AX_BD_DEF = 0xFE
1143 MAC_AX_RXBD_DEF = 0xFE
1149 MAC_AX_TAG_DEF = 0xFE
1153 MAC_AX_TX_BURST_16B = 0,
1156 MAC_AX_TX_BURST_V1_64B = 0,
1164 MAC_AX_TX_BURST_DEF = 0xFE
1168 MAC_AX_RX_BURST_16B = 0,
1171 MAC_AX_RX_BURST_V1_64B = 0,
1174 MAC_AX_RX_BURST_V1_256B = 0,
1175 MAC_AX_RX_BURST_DEF = 0xFE
1189 MAC_AX_WD_DMA_INTVL_DEF = 0xFE
1201 MAC_AX_TAG_NUM_DEF = 0xFE
1205 MAC_AX_LBC_TMR_8US = 0,
1216 MAC_AX_LBC_TMR_DEF = 0xFE
1220 MAC_AX_PCIE_DISABLE = 0,
1222 MAC_AX_PCIE_DEFAULT = 0xFE,
1223 MAC_AX_PCIE_IGNORE = 0xFF
1230 MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
1397 #define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0))
1409 #define B_PCIADDR_LEN_V1_MASK GENMASK(10, 0)
1420 #define RTW89_TX_DONE 0x0
1421 #define RTW89_TX_RETRY_LIMIT 0x1
1422 #define RTW89_TX_LIFE_TIME 0x2
1423 #define RTW89_TX_MACID_DROP 0x3
1425 #define RTW89_PCI_RPP_MACID GENMASK(7, 0)
1440 #define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0)
1481 #define RTW89_RX_TAG_MAX 0x1fff
1489 u16 tag; /* range from 0x0001 ~ 0x1fff */
1599 txwd->len = 0;
1611 memset(txwd->vaddr, 0, wd_ring->page_size);
1618 return val == 0xffffffff || val == 0xeaeaeaea;
1750 return 0;