Lines Matching refs:phy_offset

30 						  u32 *phy_offset)
43 		*phy_offset = R_RAC_DIRECT_OFFSET_G1;
45 		*phy_offset = R_RAC_DIRECT_OFFSET_G2;
2443 	u32 phy_offset;
2462 	ret = rtw89_pci_get_phy_offset_by_link_speed(rtwdev, &phy_offset);
2466 	rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT, BAC_RX_TEST_EN);
2467 	rtw89_write16(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT, ADDR_SEL_PINOUT_DIS_VAL);
2468 	rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT, B_PCIE_BIT_RD_SEL);
2470 	oobs_val = rtw89_read16_mask(rtwdev, phy_offset + RAC_ANA1F * RAC_MULT,
2485 		phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_G1 :
2488 		rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT,
2496 		phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_G1 :
2499 		rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA0B * RAC_MULT,
2501 		rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT,
2511 	u32 phy_offset;
2516 	phy_offset = R_RAC_DIRECT_OFFSET_G1;
2517 	rtw89_write16(rtwdev, phy_offset + RAC_ANA1E * RAC_MULT, RAC_ANA1E_G1_VAL);
2518 	rtw89_write16(rtwdev, phy_offset + RAC_ANA2E * RAC_MULT, RAC_ANA2E_VAL);
2520 	phy_offset = R_RAC_DIRECT_OFFSET_G2;
2521 	rtw89_write16(rtwdev, phy_offset + RAC_ANA1E * RAC_MULT, RAC_ANA1E_G2_VAL);
2522 	rtw89_write16(rtwdev, phy_offset + RAC_ANA2E * RAC_MULT, RAC_ANA2E_VAL);
3902 	u32 val, phy_offset;
3918 		phy_offset = R_RAC_DIRECT_OFFSET_G1;
3920 		phy_offset = R_RAC_DIRECT_OFFSET_G2;
3921 		val16 = rtw89_read16(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT);
3922 		rtw89_write16_set(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT,
3924 		rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT,
3928 					  phy_offset + RAC_ANA1F * RAC_MULT,
3931 		filter_out_val = rtw89_read16(rtwdev, phy_offset + RAC_ANA24 *
3936 		rtw89_write16(rtwdev, phy_offset + RAC_ANA24 * RAC_MULT,
3938 		rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0A * RAC_MULT,
3946 	rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0C * RAC_MULT,