Lines Matching +full:dma +full:- +full:info
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
32 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
33 struct pci_dev *pdev = rtwpci->pdev;
48 return -EFAULT;
72 const struct rtw89_pci_info *info = rtwdev->pci_info;
75 rp = bd_ring->rp;
76 wp = bd_ring->wp;
77 len = bd_ring->len;
81 cnt = cur_rp >= rp ? cur_rp - rp : len - (rp - cur_rp);
83 if (info->rx_ring_eq_is_full)
86 cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp);
89 bd_ring->rp = cur_rp;
97 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
98 u32 addr_idx = bd_ring->addr.idx;
115 while (cnt--) {
116 skb = skb_dequeue(&rtwpci->h2c_queue);
118 rtw89_err(rtwdev, "failed to pre-release fwcmd\n");
121 skb_queue_tail(&rtwpci->h2c_release_queue, skb);
124 qlen = skb_queue_len(&rtwpci->h2c_release_queue);
126 qlen = qlen > RTW89_PCI_MULTITAG ? qlen - RTW89_PCI_MULTITAG : 0;
128 while (qlen--) {
129 skb = skb_dequeue(&rtwpci->h2c_release_queue);
135 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len,
144 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12];
156 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
157 u32 addr_idx = bd_ring->addr.idx;
170 dma_addr_t dma;
173 dma = rx_info->dma;
174 dma_sync_single_for_cpu(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE,
182 dma_addr_t dma;
185 dma = rx_info->dma;
186 dma_sync_single_for_device(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE,
195 __le32 info;
197 rxbd_info = (struct rtw89_pci_rxbd_info *)skb->data;
198 info = rxbd_info->dword;
200 rx_info->fs = le32_get_bits(info, RTW89_PCI_RXBD_FS);
201 rx_info->ls = le32_get_bits(info, RTW89_PCI_RXBD_LS);
202 rx_info->len = le32_get_bits(info, RTW89_PCI_RXBD_WRITE_SIZE);
203 rx_info->tag = le32_get_bits(info, RTW89_PCI_RXBD_TAG);
211 const struct rtw89_pci_info *info = rtwdev->pci_info;
214 if (!info->check_rx_tag)
218 if (rx_ring->target_rx_tag == 0)
221 target_rx_tag = rx_ring->target_rx_tag;
223 if (rx_info->tag != target_rx_tag) {
225 rx_info->tag, target_rx_tag);
226 return -EAGAIN;
246 if (ret != -EAGAIN)
248 } while (rx_tag_retry--);
251 rx_ring->target_rx_tag = rx_info->tag + 1;
258 const struct rtw89_pci_info *info = rtwdev->pci_info;
259 const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1;
260 const struct rtw89_reg_def *dma_stop2 = &info->dma_stop2;
263 rtw89_write32_clr(rtwdev, dma_stop1->addr, dma_stop1->mask);
264 if (dma_stop2->addr)
265 rtw89_write32_clr(rtwdev, dma_stop2->addr, dma_stop2->mask);
267 rtw89_write32_set(rtwdev, dma_stop1->addr, dma_stop1->mask);
268 if (dma_stop2->addr)
269 rtw89_write32_set(rtwdev, dma_stop2->addr, dma_stop2->mask);
275 const struct rtw89_pci_info *info = rtwdev->pci_info;
276 const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1;
279 rtw89_write32_clr(rtwdev, dma_stop1->addr, B_AX_STOP_CH12);
281 rtw89_write32_set(rtwdev, dma_stop1->addr, B_AX_STOP_CH12);
291 u32 copy_len = rx_info->len - offset;
296 rx_info->len, desc_info->pkt_size, offset, fs, ls);
298 skb->data, rx_info->len);
299 /* length of a single segment skb is desc_info->pkt_size */
301 copy_len = desc_info->pkt_size;
308 skb_put_data(new, skb->data + offset, copy_len);
316 const struct rtw89_pci_info *info = rtwdev->pci_info;
317 u32 wp = bd_ring->wp;
319 if (!info->rx_ring_eq_is_full)
322 if (++wp >= bd_ring->len)
331 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
333 struct rtw89_rx_desc_info *desc_info = &rx_ring->diliver_desc;
334 struct sk_buff *new = rx_ring->diliver_skb;
344 skb = rx_ring->buf[skb_idx];
348 rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n",
349 bd_ring->wp, ret);
354 fs = rx_info->fs;
355 ls = rx_info->ls;
363 if (desc_info->ready) {
364 rtw89_warn(rtwdev, "desc info should not be ready before first segment start\n");
368 rtw89_chip_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size);
370 new = rtw89_alloc_skb_for_rx(rtwdev, desc_info->pkt_size);
374 rx_ring->diliver_skb = new;
377 offset = desc_info->offset + desc_info->rxd_len;
390 if (!desc_info->ready) {
396 rx_ring->diliver_skb = NULL;
397 desc_info->ready = false;
408 rx_ring->diliver_skb = NULL;
409 desc_info->ready = false;
418 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
421 while (cnt && rtwdev->napi_budget_countdown > 0) {
431 cnt -= rx_cnt;
434 rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp);
441 int countdown = rtwdev->napi_budget_countdown;
444 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ];
455 if (rtwdev->napi_budget_countdown <= 0)
458 return budget - countdown;
466 struct ieee80211_tx_info *info;
470 info = IEEE80211_SKB_CB(skb);
471 ieee80211_tx_info_clear_status(info);
473 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
474 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
476 info->flags |= IEEE80211_TX_STAT_ACK;
477 tx_ring->tx_acked++;
479 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS)
484 tx_ring->tx_retry_lmt++;
487 tx_ring->tx_life_time++;
490 tx_ring->tx_mac_id_drop++;
498 ieee80211_tx_status_ni(rtwdev->hw, skb);
507 while (cnt--) {
508 txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list);
514 list_del_init(&txwd->list);
517 if (skb_queue_len(&txwd->queue) == 0)
525 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
529 for (i = 0; i < wd_ring->page_num; i++) {
530 txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list);
534 list_del_init(&txwd->list);
543 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
546 u8 txch = tx_ring->txch;
548 if (!list_empty(&txwd->list)) {
553 if (!rtwpci->low_power && !list_empty(&txwd->list))
558 skb_queue_walk_safe(&txwd->queue, skb, tmp) {
559 skb_unlink(skb, &txwd->queue);
562 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len,
568 if (list_empty(&txwd->list))
575 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
582 seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ);
583 qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL);
584 tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS);
592 tx_ring = &rtwpci->tx_rings[txch];
593 wd_ring = &tx_ring->wd_ring;
594 txwd = &wd_ring->pages[seq];
602 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
606 for (i = 0; i < wd_ring->page_num; i++) {
607 txwd = &wd_ring->pages[i];
609 if (!list_empty(&txwd->list))
620 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
633 skb = rx_ring->buf[skb_idx];
637 rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n",
638 bd_ring->wp, ret);
643 if (!rx_info->fs || !rx_info->ls) {
648 rtw89_chip_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size);
652 for (; offset + rpp_size <= rx_info->len; offset += rpp_size) {
653 rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset);
672 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
685 cnt -= release_cnt;
688 rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp);
698 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ];
700 spin_lock_bh(&rtwpci->trx_lock);
709 spin_unlock_bh(&rtwpci->trx_lock);
713 rtwdev->napi_budget_countdown -= work_done;
728 rx_ring = &rtwpci->rx_rings[i];
729 bd_ring = &rx_ring->bd_ring;
731 reg_idx = rtw89_read32(rtwdev, bd_ring->addr.idx);
734 hw_idx_next = (hw_idx + 1) % bd_ring->len;
741 i, reg_idx, bd_ring->len);
749 isrs->halt_c2h_isrs = rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs;
750 isrs->isrs[0] = rtw89_read32(rtwdev, R_AX_PCIE_HISR00) & rtwpci->intrs[0];
751 isrs->isrs[1] = rtw89_read32(rtwdev, R_AX_PCIE_HISR10) & rtwpci->intrs[1];
753 rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs);
754 rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isrs->isrs[0]);
755 rtw89_write32(rtwdev, R_AX_PCIE_HISR10, isrs->isrs[1]);
763 isrs->ind_isrs = rtw89_read32(rtwdev, R_AX_PCIE_HISR00_V1) & rtwpci->ind_intrs;
764 isrs->halt_c2h_isrs = isrs->ind_isrs & B_AX_HS0ISR_IND_INT_EN ?
765 rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs : 0;
766 isrs->isrs[0] = isrs->ind_isrs & B_AX_HCI_AXIDMA_INT_EN ?
767 rtw89_read32(rtwdev, R_AX_HAXI_HISR00) & rtwpci->intrs[0] : 0;
768 isrs->isrs[1] = isrs->ind_isrs & B_AX_HS1ISR_IND_INT_EN ?
769 rtw89_read32(rtwdev, R_AX_HISR1) & rtwpci->intrs[1] : 0;
771 if (isrs->halt_c2h_isrs)
772 rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs);
773 if (isrs->isrs[0])
774 rtw89_write32(rtwdev, R_AX_HAXI_HISR00, isrs->isrs[0]);
775 if (isrs->isrs[1])
776 rtw89_write32(rtwdev, R_AX_HISR1, isrs->isrs[1]);
784 isrs->ind_isrs = rtw89_read32(rtwdev, R_BE_PCIE_HISR) & rtwpci->ind_intrs;
785 isrs->halt_c2h_isrs = isrs->ind_isrs & B_BE_HS0ISR_IND_INT ?
786 rtw89_read32(rtwdev, R_BE_HISR0) & rtwpci->halt_c2h_intrs : 0;
787 isrs->isrs[0] = isrs->ind_isrs & B_BE_HCI_AXIDMA_INT ?
788 rtw89_read32(rtwdev, R_BE_HAXI_HISR00) & rtwpci->intrs[0] : 0;
789 isrs->isrs[1] = rtw89_read32(rtwdev, R_BE_PCIE_DMA_ISR) & rtwpci->intrs[1];
791 if (isrs->halt_c2h_isrs)
792 rtw89_write32(rtwdev, R_BE_HISR0, isrs->halt_c2h_isrs);
793 if (isrs->isrs[0])
794 rtw89_write32(rtwdev, R_BE_HAXI_HISR00, isrs->isrs[0]);
795 if (isrs->isrs[1])
796 rtw89_write32(rtwdev, R_BE_PCIE_DMA_ISR, isrs->isrs[1]);
797 rtw89_write32(rtwdev, R_BE_PCIE_HISR, isrs->ind_isrs);
803 rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs);
804 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, rtwpci->intrs[0]);
805 rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, rtwpci->intrs[1]);
819 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00_V1, rtwpci->ind_intrs);
820 rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs);
821 rtw89_write32(rtwdev, R_AX_HAXI_HIMR00, rtwpci->intrs[0]);
822 rtw89_write32(rtwdev, R_AX_HIMR1, rtwpci->intrs[1]);
834 rtw89_write32(rtwdev, R_BE_HIMR0, rtwpci->halt_c2h_intrs);
835 rtw89_write32(rtwdev, R_BE_HAXI_HIMR00, rtwpci->intrs[0]);
836 rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, rtwpci->intrs[1]);
837 rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, rtwpci->ind_intrs);
850 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
853 spin_lock_irqsave(&rtwpci->irq_lock, flags);
857 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
862 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
865 spin_lock_irqsave(&rtwpci->irq_lock, flags);
869 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
874 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
878 rtwdev->napi_budget_countdown = budget;
887 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
888 const struct rtw89_pci_info *info = rtwdev->pci_info;
889 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
893 spin_lock_irqsave(&rtwpci->irq_lock, flags);
895 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
897 if (unlikely(isrs.isrs[0] & gen_def->isr_rdu))
900 if (unlikely(isrs.halt_c2h_isrs & gen_def->isr_halt_c2h))
903 if (unlikely(isrs.halt_c2h_isrs & gen_def->isr_wdt_timeout))
906 if (unlikely(rtwpci->under_recovery))
909 if (unlikely(rtwpci->low_power)) {
914 if (likely(rtwpci->running)) {
916 napi_schedule(&rtwdev->napi);
923 spin_lock_irqsave(&rtwpci->irq_lock, flags);
924 if (likely(rtwpci->running))
926 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
933 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
937 spin_lock_irqsave(&rtwpci->irq_lock, flags);
942 if (unlikely(!rtwpci->running)) {
949 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
963 #define DEF_TXCHADDRS_TYPE1(info, txch, v...) \
972 #define DEF_TXCHADDRS(info, txch, v...) \
991 DEF_TXCHADDRS(info, ACH0),
992 DEF_TXCHADDRS(info, ACH1),
993 DEF_TXCHADDRS(info, ACH2),
994 DEF_TXCHADDRS(info, ACH3),
995 DEF_TXCHADDRS(info, ACH4),
996 DEF_TXCHADDRS(info, ACH5),
997 DEF_TXCHADDRS(info, ACH6),
998 DEF_TXCHADDRS(info, ACH7),
999 DEF_TXCHADDRS(info, CH8),
1000 DEF_TXCHADDRS(info, CH9),
1001 DEF_TXCHADDRS_TYPE1(info, CH10),
1002 DEF_TXCHADDRS_TYPE1(info, CH11),
1003 DEF_TXCHADDRS(info, CH12),
1014 DEF_TXCHADDRS(info, ACH0, _V1),
1015 DEF_TXCHADDRS(info, ACH1, _V1),
1016 DEF_TXCHADDRS(info, ACH2, _V1),
1017 DEF_TXCHADDRS(info, ACH3, _V1),
1018 DEF_TXCHADDRS(info, ACH4, _V1),
1019 DEF_TXCHADDRS(info, ACH5, _V1),
1020 DEF_TXCHADDRS(info, ACH6, _V1),
1021 DEF_TXCHADDRS(info, ACH7, _V1),
1022 DEF_TXCHADDRS(info, CH8, _V1),
1023 DEF_TXCHADDRS(info, CH9, _V1),
1024 DEF_TXCHADDRS_TYPE1(info, CH10, _V1),
1025 DEF_TXCHADDRS_TYPE1(info, CH11, _V1),
1026 DEF_TXCHADDRS(info, CH12, _V1),
1066 const struct rtw89_pci_info *info = rtwdev->pci_info;
1069 return -EINVAL;
1071 *addr = &info->dma_addr_set->tx[txch];
1080 const struct rtw89_pci_info *info = rtwdev->pci_info;
1083 return -EINVAL;
1085 *addr = &info->dma_addr_set->rx[rxch];
1092 struct rtw89_pci_dma_ring *bd_ring = &ring->bd_ring;
1095 if (bd_ring->rp > bd_ring->wp)
1096 return bd_ring->rp - bd_ring->wp - 1;
1098 return bd_ring->len - (bd_ring->wp - bd_ring->rp) - 1;
1104 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1105 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12];
1108 spin_lock_bh(&rtwpci->trx_lock);
1111 spin_unlock_bh(&rtwpci->trx_lock);
1120 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1121 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
1122 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1125 spin_lock_bh(&rtwpci->trx_lock);
1128 cnt = min(cnt, wd_ring->curr_num);
1129 spin_unlock_bh(&rtwpci->trx_lock);
1137 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1138 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
1139 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1140 const struct rtw89_chip_info *chip = rtwdev->chip;
1146 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ];
1148 spin_lock_bh(&rtwpci->trx_lock);
1150 wd_cnt = wd_ring->curr_num;
1165 wd_cnt = wd_ring->curr_num;
1172 if (rtwpci->low_power || chip->small_fifo_size)
1183 spin_unlock_bh(&rtwpci->trx_lock);
1191 if (rtwdev->hci.paused)
1202 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1203 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1206 spin_lock_bh(&rtwpci->trx_lock);
1208 addr = bd_ring->addr.idx;
1209 host_idx = bd_ring->wp;
1212 spin_unlock_bh(&rtwpci->trx_lock);
1218 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1221 len = bd_ring->len;
1222 host_idx = bd_ring->wp + n_txbd;
1223 host_idx = host_idx < len ? host_idx : host_idx - len;
1225 bd_ring->wp = host_idx;
1230 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1231 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
1233 if (rtwdev->hci.paused) {
1234 set_bit(txch, rtwpci->kick_map);
1243 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1248 if (!test_and_clear_bit(txch, rtwpci->kick_map))
1251 tx_ring = &rtwpci->tx_rings[txch];
1258 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1259 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
1260 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1270 cur_idx = rtw89_read32(rtwdev, bd_ring->addr.idx);
1272 if (cur_rp == bd_ring->wp)
1285 const struct rtw89_pci_info *info = rtwdev->pci_info;
1292 if (info->tx_dma_ch_mask & BIT(i))
1303 __rtw89_pci_ops_flush_txchs(rtwdev, BIT(RTW89_TXCH_NUM) - 1, drop);
1308 dma_addr_t dma, u8 *add_info_nr)
1313 txaddr_info->length = cpu_to_le16(total_len);
1315 option |= le16_encode_bits(upper_32_bits(dma), RTW89_PCI_ADDR_HIGH_MASK);
1316 txaddr_info->option = option;
1317 txaddr_info->dma = cpu_to_le32(dma);
1327 dma_addr_t dma, u8 *add_info_nr)
1338 remain -= len;
1343 length_option |= u16_encode_bits(upper_32_bits(dma),
1345 txaddr_info->length_opt = cpu_to_le16(length_option);
1346 txaddr_info->dma_low_lsb = cpu_to_le16(FIELD_GET(GENMASK(15, 0), dma));
1347 txaddr_info->dma_low_msb = cpu_to_le16(FIELD_GET(GENMASK(31, 16), dma));
1349 dma += len;
1367 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1368 const struct rtw89_chip_info *chip = rtwdev->chip;
1369 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1372 struct pci_dev *pdev = rtwpci->pdev;
1373 struct sk_buff *skb = tx_req->skb;
1376 bool en_wd_info = desc_info->en_wd_info;
1380 dma_addr_t dma;
1383 dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE);
1384 if (dma_mapping_error(&pdev->dev, dma)) {
1385 rtw89_err(rtwdev, "failed to map skb dma data\n");
1386 ret = -EBUSY;
1390 tx_data->dma = dma;
1391 rcu_assign_pointer(skb_data->wait, NULL);
1394 txwd_len = chip->txwd_body_size;
1395 txwd_len += en_wd_info ? chip->txwd_info_size : 0;
1398 txwp_info = txwd->vaddr + txwd_len;
1400 txwp_info = (struct rtw89_pci_tx_wp_info *)((u8 *)txwd->vaddr + txwd_len);
1402 txwp_info->seq0 = cpu_to_le16(txwd->seq | RTW89_PCI_TXWP_VALID);
1403 txwp_info->seq1 = 0;
1404 txwp_info->seq2 = 0;
1405 txwp_info->seq3 = 0;
1407 tx_ring->tx_cnt++;
1409 txaddr_info_addr = txwd->vaddr + txwd_len + txwp_len;
1411 txaddr_info_addr = (u8 *)txwd->vaddr + txwd_len + txwp_len;
1414 rtw89_chip_fill_txaddr_info(rtwdev, txaddr_info_addr, skb->len,
1415 dma, &desc_info->addr_info_nr);
1417 txwd->len = txwd_len + txwp_len + txaddr_info_len;
1419 rtw89_chip_fill_txdesc(rtwdev, desc_info, txwd->vaddr);
1421 skb_queue_tail(&txwd->queue, skb);
1434 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1435 const struct rtw89_chip_info *chip = rtwdev->chip;
1436 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1438 int txdesc_size = chip->h2c_desc_size;
1439 struct pci_dev *pdev = rtwpci->pdev;
1440 struct sk_buff *skb = tx_req->skb;
1442 dma_addr_t dma;
1449 dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE);
1450 if (dma_mapping_error(&pdev->dev, dma)) {
1451 rtw89_err(rtwdev, "failed to map fwcmd dma data\n");
1452 return -EBUSY;
1455 tx_data->dma = dma;
1457 opt |= le16_encode_bits(upper_32_bits(dma), RTW89_PCI_TXBD_OPT_DMA_HI);
1458 txbd->opt = opt;
1459 txbd->length = cpu_to_le16(skb->len);
1460 txbd->dma = cpu_to_le32(tx_data->dma);
1461 skb_queue_tail(&rtwpci->h2c_queue, skb);
1481 if (tx_ring->txch == RTW89_TXCH_CH12)
1487 ret = -ENOSPC;
1493 rtw89_err(rtwdev, "failed to submit TXWD %d\n", txwd->seq);
1497 list_add_tail(&txwd->list, &tx_ring->busy_pages);
1500 opt |= le16_encode_bits(upper_32_bits(txwd->paddr), RTW89_PCI_TXBD_OPT_DMA_HI);
1501 txbd->opt = opt;
1502 txbd->length = cpu_to_le16(txwd->len);
1503 txbd->dma = cpu_to_le32(txwd->paddr);
1518 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1524 /* check the tx type and dma channel for fw cmd queue */
1526 tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD) &&
1528 tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD)) {
1529 rtw89_err(rtwdev, "only fw cmd uses dma channel 12\n");
1530 return -EINVAL;
1533 tx_ring = &rtwpci->tx_rings[txch];
1534 spin_lock_bh(&rtwpci->trx_lock);
1539 ret = -ENOSPC;
1550 spin_unlock_bh(&rtwpci->trx_lock);
1554 spin_unlock_bh(&rtwpci->trx_lock);
1560 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1563 ret = rtw89_pci_tx_write(rtwdev, tx_req, desc_info->ch_dma);
1565 rtw89_err(rtwdev, "failed to TX Queue %d\n", desc_info->ch_dma);
1602 const struct rtw89_pci_info *info = rtwdev->pci_info;
1603 u32 addr = info->wp_sel_addr;
1607 if (!info->wp_sel_addr)
1621 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1622 const struct rtw89_pci_info *info = rtwdev->pci_info;
1623 const struct rtw89_pci_bd_ram *bd_ram_table = *info->bd_ram_table;
1636 if (info->tx_dma_ch_mask & BIT(i))
1639 tx_ring = &rtwpci->tx_rings[i];
1640 bd_ring = &tx_ring->bd_ring;
1642 addr_num = bd_ring->addr.num;
1643 addr_bdram = bd_ring->addr.bdram;
1644 addr_desa_l = bd_ring->addr.desa_l;
1645 bd_ring->wp = 0;
1646 bd_ring->rp = 0;
1648 rtw89_write16(rtwdev, addr_num, bd_ring->len);
1650 val32 = FIELD_PREP(BDRAM_SIDX_MASK, bd_ram->start_idx) |
1651 FIELD_PREP(BDRAM_MAX_MASK, bd_ram->max_num) |
1652 FIELD_PREP(BDRAM_MIN_MASK, bd_ram->min_num);
1656 rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma);
1657 rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma));
1661 rx_ring = &rtwpci->rx_rings[i];
1662 bd_ring = &rx_ring->bd_ring;
1663 addr_num = bd_ring->addr.num;
1664 addr_idx = bd_ring->addr.idx;
1665 addr_desa_l = bd_ring->addr.desa_l;
1666 if (info->rx_ring_eq_is_full)
1667 bd_ring->wp = bd_ring->len - 1;
1669 bd_ring->wp = 0;
1670 bd_ring->rp = 0;
1671 rx_ring->diliver_skb = NULL;
1672 rx_ring->diliver_desc.ready = false;
1673 rx_ring->target_rx_tag = 0;
1675 rtw89_write16(rtwdev, addr_num, bd_ring->len);
1676 rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma);
1677 rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma));
1679 if (info->rx_ring_eq_is_full)
1680 rtw89_write16(rtwdev, addr_idx, bd_ring->wp);
1695 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1696 const struct rtw89_pci_info *info = rtwdev->pci_info;
1701 spin_lock_bh(&rtwpci->trx_lock);
1703 if (info->tx_dma_ch_mask & BIT(txch))
1707 skb_queue_len(&rtwpci->h2c_queue), true);
1710 rtw89_pci_release_tx_ring(rtwdev, &rtwpci->tx_rings[txch]);
1712 spin_unlock_bh(&rtwpci->trx_lock);
1717 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1720 spin_lock_irqsave(&rtwpci->irq_lock, flags);
1721 rtwpci->running = true;
1723 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
1728 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1731 spin_lock_irqsave(&rtwpci->irq_lock, flags);
1732 rtwpci->running = false;
1734 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
1747 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1748 struct pci_dev *pdev = rtwpci->pdev;
1751 synchronize_irq(pdev->irq);
1757 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1758 struct pci_dev *pdev = rtwpci->pdev;
1762 synchronize_irq(pdev->irq);
1763 if (test_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
1764 napi_synchronize(&rtwdev->napi);
1774 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1775 const struct rtw89_pci_info *info = rtwdev->pci_info;
1776 const struct rtw89_pci_bd_idx_addr *bd_idx_addr = info->bd_idx_addr_low_power;
1777 const struct rtw89_pci_ch_dma_addr_set *dma_addr_set = info->dma_addr_set;
1786 tx_ring = &rtwpci->tx_rings[i];
1787 tx_ring->bd_ring.addr.idx = low_power ?
1788 bd_idx_addr->tx_bd_addrs[i] :
1789 dma_addr_set->tx[i].idx;
1793 rx_ring = &rtwpci->rx_rings[i];
1794 rx_ring->bd_ring.addr.idx = low_power ?
1795 bd_idx_addr->rx_bd_addrs[i] :
1796 dma_addr_set->rx[i].idx;
1804 WARN(!rtwdev->hci.paused, "HCI isn't paused\n");
1815 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1817 u32 val = readl(rtwpci->mmap + addr);
1821 val = bus_read_4((struct resource *)rtwpci->mmap, addr);
1822 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R32 (%#010x) -> %#010x\n", addr, val);
1835 val = readl(rtwpci->mmap + addr);
1837 val = bus_read_4((struct resource *)rtwpci->mmap, addr);
1838 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R32 (%#010x) -> %#010x\n", addr, val);
1847 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1852 return readb(rtwpci->mmap + addr);
1857 val = bus_read_1((struct resource *)rtwpci->mmap, addr);
1858 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R08 (%#010x) -> %#04x\n", addr, val);
1871 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1876 return readw(rtwpci->mmap + addr);
1881 val = bus_read_2((struct resource *)rtwpci->mmap, addr);
1882 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R16 (%#010x) -> %#06x\n", addr, val);
1895 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1899 return readl(rtwpci->mmap + addr);
1904 val = bus_read_4((struct resource *)rtwpci->mmap, addr);
1905 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R32 (%#010x) -> %#010x\n", addr, val);
1915 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1918 writeb(data, rtwpci->mmap + addr);
1920 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "W08 (%#010x) <- %#04x\n", addr, data);
1921 return (bus_write_1((struct resource *)rtwpci->mmap, addr, data));
1927 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1930 writew(data, rtwpci->mmap + addr);
1932 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "W16 (%#010x) <- %#06x\n", addr, data);
1933 return (bus_write_2((struct resource *)rtwpci->mmap, addr, data));
1939 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1942 writel(data, rtwpci->mmap + addr);
1944 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "W32 (%#010x) <- %#010x\n", addr, data);
1945 return (bus_write_4((struct resource *)rtwpci->mmap, addr, data));
1951 const struct rtw89_pci_info *info = rtwdev->pci_info;
1954 rtw89_write32_set(rtwdev, info->init_cfg_reg,
1955 info->rxhci_en_bit | info->txhci_en_bit);
1957 rtw89_write32_clr(rtwdev, info->init_cfg_reg,
1958 info->rxhci_en_bit | info->txhci_en_bit);
1963 const struct rtw89_pci_info *info = rtwdev->pci_info;
1964 const struct rtw89_reg_def *reg = &info->dma_io_stop;
1967 rtw89_write32_clr(rtwdev, reg->addr, reg->mask);
1969 rtw89_write32_set(rtwdev, reg->addr, reg->mask);
2000 return -EINVAL;
2141 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
2142 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2143 struct pci_dev *pdev = rtwpci->pdev;
2159 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
2160 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2161 struct pci_dev *pdev = rtwpci->pdev;
2238 return -EINVAL;
2282 return -EOPNOTSUPP;
2333 mgn_set = tar * INTF_INTGRA_HOSTREF_V1 / INTF_INTGRA_MINREF_V1 - tar;
2411 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2441 if (rtwdev->chip->chip_id != RTL8852C)
2483 if (!test_bit(RTW89_QUIRK_PCI_BER, rtwdev->quirks))
2497 if (rtwdev->chip->chip_id != RTL8852A)
2505 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2517 if (rtwdev->chip->chip_id != RTL8852A)
2535 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2545 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2552 } else if (rtwdev->chip->chip_id == RTL8852C) {
2577 if (rtwdev->chip->chip_id != RTL8852C)
2586 if (!(rtwdev->chip->chip_id == RTL8852C && rtwdev->hal.cv == CHIP_CAV))
2594 if (!(rtwdev->chip->chip_id == RTL8852C && rtwdev->hal.cv == CHIP_CAV))
2606 if (rtwdev->chip->chip_id != RTL8852C)
2614 if (rtwdev->chip->chip_id != RTL8852C)
2622 if (rtwdev->chip->chip_id == RTL8852C)
2631 const struct rtw89_pci_info *info = rtwdev->pci_info;
2634 if (rtwdev->chip->chip_id == RTL8852C)
2638 if (info->lbc_en == MAC_AX_PCIE_ENABLE) {
2639 lbc = u32_replace_bits(lbc, info->lbc_tmr, B_AX_LBC_TIMER);
2650 const struct rtw89_pci_info *info = rtwdev->pci_info;
2653 if (rtwdev->chip->chip_id != RTL8852C)
2656 if (info->io_rcy_en == MAC_AX_PCIE_ENABLE) {
2658 info->io_rcy_tmr);
2677 if (rtwdev->chip->chip_id == RTL8852C)
2683 if (rtwdev->chip->chip_id == RTL8852A)
2690 if (rtwdev->chip->chip_id == RTL8852C)
2699 const struct rtw89_pci_info *info = rtwdev->pci_info;
2700 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2704 u32 rxbd_rwptr_clr = info->rxbd_rwptr_clr_reg;
2705 u32 txbd_rwptr_clr2 = info->txbd_rwptr_clr2_reg;
2710 /* clear DMA indexes */
2721 const struct rtw89_pci_info *info = rtwdev->pci_info;
2723 u32 dma_busy1 = info->dma_busy1.addr;
2724 u32 dma_busy2 = info->dma_busy2_reg;
2726 check = info->dma_busy1.mask;
2748 const struct rtw89_pci_info *info = rtwdev->pci_info;
2750 u32 dma_busy3 = info->dma_busy3_reg;
2783 const struct rtw89_pci_info *info = rtwdev->pci_info;
2784 enum mac_ax_bd_trunc_mode txbd_trunc_mode = info->txbd_trunc_mode;
2785 enum mac_ax_bd_trunc_mode rxbd_trunc_mode = info->rxbd_trunc_mode;
2786 enum mac_ax_rxbd_mode rxbd_mode = info->rxbd_mode;
2787 enum mac_ax_tag_mode tag_mode = info->tag_mode;
2788 enum mac_ax_wd_dma_intvl wd_dma_idle_intvl = info->wd_dma_idle_intvl;
2789 enum mac_ax_wd_dma_intvl wd_dma_act_intvl = info->wd_dma_act_intvl;
2790 enum mac_ax_tx_burst tx_burst = info->tx_burst;
2791 enum mac_ax_rx_burst rx_burst = info->rx_burst;
2792 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2793 u8 cv = rtwdev->hal.cv;
2813 rtw89_write32_clr(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit);
2815 rtw89_write32_set(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit);
2842 rtw89_write32_mask(rtwdev, info->exp_ctrl_reg, info->max_tag_num_mask,
2843 info->multi_tag_num);
2872 const struct rtw89_pci_info *info = rtwdev->pci_info;
2874 if (rtwdev->chip->chip_id == RTL8852A) {
2878 info->ltr_set(rtwdev, false);
2887 const struct rtw89_pci_info *info = rtwdev->pci_info;
2928 rtw89_write32_set(rtwdev, info->dma_stop1.addr, B_AX_STOP_WPDMA);
2930 /* stop DMA activities */
2935 rtw89_err(rtwdev, "[ERR] poll pcie dma all idle\n");
2955 /* start DMA activities */
2970 return -EINVAL;
2973 return -EINVAL;
2976 return -EINVAL;
2979 return -EINVAL;
3003 return -EINVAL;
3006 return -EINVAL;
3009 return -EINVAL;
3012 return -EINVAL;
3015 return -EINVAL;
3045 const struct rtw89_pci_info *info = rtwdev->pci_info;
3046 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3049 ret = info->ltr_set(rtwdev, true);
3059 /* ADDR info 8-byte mode */
3065 /* enable DMA for all queues */
3069 rtw89_write32_clr(rtwdev, info->dma_stop1.addr,
3078 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3088 pci_set_drvdata(pdev, rtwdev->hw);
3090 rtwpci->pdev = pdev;
3103 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3104 const struct rtw89_chip_info *chip = rtwdev->chip;
3106 if (!rtwpci->enable_dac)
3109 switch (chip->chip_id) {
3125 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3136 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
3138 rtwpci->enable_dac = true;
3141 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3144 "failed to set dma and consistent mask to 32/36-bit\n");
3153 rtwpci->mmap = pci_iomap(pdev, bar_id, resource_len);
3154 if (!rtwpci->mmap) {
3156 ret = -EIO;
3171 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3173 if (rtwpci->mmap) {
3174 pci_iounmap(pdev, rtwpci->mmap);
3183 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
3184 u8 *head = wd_ring->head;
3185 dma_addr_t dma = wd_ring->dma;
3186 u32 page_size = wd_ring->page_size;
3187 u32 page_num = wd_ring->page_num;
3190 dma_free_coherent(&pdev->dev, ring_sz, head, dma);
3191 wd_ring->head = NULL;
3200 dma_addr_t dma;
3202 head = tx_ring->bd_ring.head;
3203 dma = tx_ring->bd_ring.dma;
3204 ring_sz = tx_ring->bd_ring.desc_size * tx_ring->bd_ring.len;
3205 dma_free_coherent(&pdev->dev, ring_sz, head, dma);
3207 tx_ring->bd_ring.head = NULL;
3213 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3214 const struct rtw89_pci_info *info = rtwdev->pci_info;
3219 if (info->tx_dma_ch_mask & BIT(i))
3221 tx_ring = &rtwpci->tx_rings[i];
3233 dma_addr_t dma;
3236 int ring_sz = rx_ring->bd_ring.desc_size * rx_ring->bd_ring.len;
3239 buf_sz = rx_ring->buf_sz;
3240 for (i = 0; i < rx_ring->bd_ring.len; i++) {
3241 skb = rx_ring->buf[i];
3246 dma = rx_info->dma;
3247 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE);
3249 rx_ring->buf[i] = NULL;
3252 head = rx_ring->bd_ring.head;
3253 dma = rx_ring->bd_ring.dma;
3254 dma_free_coherent(&pdev->dev, ring_sz, head, dma);
3256 rx_ring->bd_ring.head = NULL;
3262 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3267 rx_ring = &rtwpci->rx_rings[i];
3285 dma_addr_t dma;
3288 return -EINVAL;
3290 dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE);
3291 if (dma_mapping_error(&pdev->dev, dma))
3292 return -EBUSY;
3298 rx_bd->buf_size = cpu_to_le16(buf_sz);
3299 rx_bd->dma = cpu_to_le32(dma);
3300 rx_bd->opt = le16_encode_bits(upper_32_bits(dma), RTW89_PCI_RXBD_OPT_DMA_HI);
3301 rx_info->dma = dma;
3311 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
3313 dma_addr_t dma;
3327 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL);
3329 return -ENOMEM;
3331 INIT_LIST_HEAD(&wd_ring->free_pages);
3332 wd_ring->head = head;
3333 wd_ring->dma = dma;
3334 wd_ring->page_size = page_size;
3335 wd_ring->page_num = page_num;
3339 txwd = &wd_ring->pages[i];
3340 cur_paddr = dma + page_offset;
3343 skb_queue_head_init(&txwd->queue);
3344 INIT_LIST_HEAD(&txwd->list);
3345 txwd->paddr = cur_paddr;
3346 txwd->vaddr = cur_vaddr;
3347 txwd->len = page_size;
3348 txwd->seq = i;
3366 dma_addr_t dma;
3381 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL);
3383 ret = -ENOMEM;
3387 INIT_LIST_HEAD(&tx_ring->busy_pages);
3388 tx_ring->bd_ring.head = head;
3389 tx_ring->bd_ring.dma = dma;
3390 tx_ring->bd_ring.len = len;
3391 tx_ring->bd_ring.desc_size = desc_size;
3392 tx_ring->bd_ring.addr = *txch_addr;
3393 tx_ring->bd_ring.wp = 0;
3394 tx_ring->bd_ring.rp = 0;
3395 tx_ring->txch = txch;
3408 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3409 const struct rtw89_pci_info *info = rtwdev->pci_info;
3417 if (info->tx_dma_ch_mask & BIT(i))
3419 tx_ring = &rtwpci->tx_rings[i];
3439 tx_ring = &rtwpci->tx_rings[i];
3451 const struct rtw89_pci_info *info = rtwdev->pci_info;
3455 dma_addr_t dma;
3467 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL);
3469 ret = -ENOMEM;
3473 rx_ring->bd_ring.head = head;
3474 rx_ring->bd_ring.dma = dma;
3475 rx_ring->bd_ring.len = len;
3476 rx_ring->bd_ring.desc_size = desc_size;
3477 rx_ring->bd_ring.addr = *rxch_addr;
3478 if (info->rx_ring_eq_is_full)
3479 rx_ring->bd_ring.wp = len - 1;
3481 rx_ring->bd_ring.wp = 0;
3482 rx_ring->bd_ring.rp = 0;
3483 rx_ring->buf_sz = buf_sz;
3484 rx_ring->diliver_skb = NULL;
3485 rx_ring->diliver_desc.ready = false;
3486 rx_ring->target_rx_tag = 0;
3491 ret = -ENOMEM;
3495 memset(skb->data, 0, buf_sz);
3496 rx_ring->buf[i] = skb;
3506 rx_ring->buf[i] = NULL;
3516 skb = rx_ring->buf[i];
3519 dma = *((dma_addr_t *)skb->cb);
3520 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE);
3522 rx_ring->buf[i] = NULL;
3525 head = rx_ring->bd_ring.head;
3526 dma = rx_ring->bd_ring.dma;
3527 dma_free_coherent(&pdev->dev, ring_sz, head, dma);
3529 rx_ring->bd_ring.head = NULL;
3537 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3545 rx_ring = &rtwpci->rx_rings[i];
3561 rx_ring = &rtwpci->rx_rings[i];
3575 rtw89_err(rtwdev, "failed to alloc dma tx rings\n");
3581 rtw89_err(rtwdev, "failed to alloc dma rx rings\n");
3596 skb_queue_head_init(&rtwpci->h2c_queue);
3597 skb_queue_head_init(&rtwpci->h2c_release_queue);
3603 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3620 spin_lock_init(&rtwpci->irq_lock);
3621 spin_lock_init(&rtwpci->trx_lock);
3634 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3639 skb_queue_len(&rtwpci->h2c_queue), true);
3644 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3645 const struct rtw89_chip_info *chip = rtwdev->chip;
3648 if (chip->chip_id == RTL8851B)
3651 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | 0;
3653 if (rtwpci->under_recovery) {
3654 rtwpci->intrs[0] = hs0isr_ind_int_en;
3655 rtwpci->intrs[1] = 0;
3657 rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN |
3666 rtwpci->intrs[1] = B_AX_HC10ISR_IND_INT_EN;
3673 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3675 rtwpci->ind_intrs = B_AX_HS0ISR_IND_INT_EN;
3676 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN;
3677 rtwpci->intrs[0] = 0;
3678 rtwpci->intrs[1] = 0;
3683 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3685 rtwpci->ind_intrs = B_AX_HCI_AXIDMA_INT_EN |
3688 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN;
3689 rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN |
3696 rtwpci->intrs[1] = B_AX_GPIO18_INT_EN;
3701 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3703 rtwpci->ind_intrs = B_AX_HS1ISR_IND_INT_EN |
3705 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN;
3706 rtwpci->intrs[0] = 0;
3707 rtwpci->intrs[1] = B_AX_GPIO18_INT_EN;
3712 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3714 if (rtwpci->under_recovery)
3716 else if (rtwpci->low_power)
3725 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3727 rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0;
3728 rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN;
3729 rtwpci->intrs[0] = 0;
3730 rtwpci->intrs[1] = 0;
3735 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3737 rtwpci->ind_intrs = B_BE_HCI_AXIDMA_INT_EN0 |
3739 rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN;
3740 rtwpci->intrs[0] = B_BE_RDU_CH1_INT_IMR_V1 |
3742 rtwpci->intrs[1] = B_BE_PCIE_RX_RX0P2_IMR0_V1 |
3748 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3750 rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0 |
3752 rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN;
3753 rtwpci->intrs[0] = 0;
3754 rtwpci->intrs[1] = B_BE_PCIE_RX_RX0P2_IMR0_V1 |
3760 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3762 if (rtwpci->under_recovery)
3764 else if (rtwpci->low_power)
3784 ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq,
3806 devm_free_irq(rtwdev->dev, pdev->irq, rtwdev);
3817 if (bit_num - bit_idx > 1)
3827 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3828 struct pci_dev *pdev = rtwpci->pdev;
3833 if (rtwdev->chip->chip_id != RTL8852C)
3872 return -EOPNOTSUPP;
3882 const struct rtw89_pci_info *info = rtwdev->pci_info;
3883 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
3888 gen_def->clkreq_set(rtwdev, enable);
3893 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3927 const struct rtw89_pci_info *info = rtwdev->pci_info;
3928 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
3933 gen_def->aspm_set(rtwdev, enable);
3938 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3977 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
3978 const struct rtw89_pci_info *info = rtwdev->pci_info;
3979 struct rtw89_traffic_stats *stats = &rtwdev->stats;
3980 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
3981 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
3984 if (rtwdev->scanning ||
3997 rtw89_write32(rtwdev, info->mit_addr, val);
4002 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
4003 struct pci_dev *pdev = rtwpci->pdev;
4016 * settings (ex. CLKREQ# not Bi-Direction), it could lead to device
4038 const struct rtw89_pci_info *info = rtwdev->pci_info;
4039 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
4044 gen_def->l1ss_set(rtwdev, enable);
4049 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
4081 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
4082 struct pci_dev *pdev = rtwpci->pdev;
4110 return -EINVAL;
4120 if (rtwdev->chip->chip_id == RTL8852C)
4149 if (rtwdev->chip->chip_id == RTL8852C)
4167 const struct rtw89_pci_info *info = rtwdev->pci_info;
4168 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
4173 ret = gen_def->lv1rst_stop_dma(rtwdev);
4175 rtw89_err(rtwdev, "lv1 rcvy pci stop dma fail\n");
4180 ret = gen_def->lv1rst_start_dma(rtwdev);
4182 rtw89_err(rtwdev, "lv1 rcvy pci start dma fail\n");
4186 return -EINVAL;
4194 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
4197 if (rtwdev->chip->chip_id == RTL8852C) {
4215 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
4216 const struct rtw89_pci_info *info = rtwdev->pci_info;
4217 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
4221 rtwdev->napi_budget_countdown = budget;
4223 rtw89_write32(rtwdev, gen_def->isr_clear_rpq.addr, gen_def->isr_clear_rpq.data);
4224 work_done = rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown);
4228 rtw89_write32(rtwdev, gen_def->isr_clear_rxq.addr, gen_def->isr_clear_rxq.data);
4229 work_done += rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown);
4231 spin_lock_irqsave(&rtwpci->irq_lock, flags);
4232 if (likely(rtwpci->running))
4234 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
4243 struct rtw89_dev *rtwdev = hw->priv;
4244 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
4264 if (rtwdev->chip->chip_id == RTL8852C)
4277 struct rtw89_dev *rtwdev = hw->priv;
4278 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
4381 const struct rtw89_driver_info *info;
4385 info = (const struct rtw89_driver_info *)id->driver_data;
4387 rtwdev = rtw89_alloc_ieee80211_hw(&pdev->dev,
4389 info->chip);
4391 dev_err(&pdev->dev, "failed to allocate hw\n");
4392 return -ENOMEM;
4395 pci_info = info->bus.pci;
4397 rtwdev->pci_info = info->bus.pci;
4398 rtwdev->hci.ops = &rtw89_pci_ops;
4399 rtwdev->hci.type = RTW89_HCI_TYPE_PCIE;
4400 rtwdev->hci.rpwm_addr = pci_info->rpwm_addr;
4401 rtwdev->hci.cpwm_addr = pci_info->cpwm_addr;
4403 rtw89_check_quirks(rtwdev, info->quirks);
4405 SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev);
4454 set_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags);
4480 rtwdev = hw->priv;