Lines Matching +full:dma +full:- +full:byte +full:- +full:en
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
32 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
33 struct pci_dev *pdev = rtwpci->pdev;
48 return -EFAULT;
72 const struct rtw89_pci_info *info = rtwdev->pci_info;
75 rp = bd_ring->rp;
76 wp = bd_ring->wp;
77 len = bd_ring->len;
81 cnt = cur_rp >= rp ? cur_rp - rp : len - (rp - cur_rp);
83 if (info->rx_ring_eq_is_full)
86 cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp);
89 bd_ring->rp = cur_rp;
97 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
98 u32 addr_idx = bd_ring->addr.idx;
115 while (cnt--) {
116 skb = skb_dequeue(&rtwpci->h2c_queue);
118 rtw89_err(rtwdev, "failed to pre-release fwcmd\n");
121 skb_queue_tail(&rtwpci->h2c_release_queue, skb);
124 qlen = skb_queue_len(&rtwpci->h2c_release_queue);
126 qlen = qlen > RTW89_PCI_MULTITAG ? qlen - RTW89_PCI_MULTITAG : 0;
128 while (qlen--) {
129 skb = skb_dequeue(&rtwpci->h2c_release_queue);
135 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len,
144 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12];
156 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
157 u32 addr_idx = bd_ring->addr.idx;
170 dma_addr_t dma;
173 dma = rx_info->dma;
174 dma_sync_single_for_cpu(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE,
182 dma_addr_t dma;
185 dma = rx_info->dma;
186 dma_sync_single_for_device(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE,
197 rxbd_info = (struct rtw89_pci_rxbd_info *)skb->data;
198 info = rxbd_info->dword;
200 rx_info->fs = le32_get_bits(info, RTW89_PCI_RXBD_FS);
201 rx_info->ls = le32_get_bits(info, RTW89_PCI_RXBD_LS);
202 rx_info->len = le32_get_bits(info, RTW89_PCI_RXBD_WRITE_SIZE);
203 rx_info->tag = le32_get_bits(info, RTW89_PCI_RXBD_TAG);
211 const struct rtw89_pci_info *info = rtwdev->pci_info;
214 if (!info->check_rx_tag)
218 if (rx_ring->target_rx_tag == 0)
221 target_rx_tag = rx_ring->target_rx_tag;
223 if (rx_info->tag != target_rx_tag) {
225 rx_info->tag, target_rx_tag);
226 return -EAGAIN;
246 if (ret != -EAGAIN)
248 } while (rx_tag_retry--);
251 rx_ring->target_rx_tag = rx_info->tag + 1;
258 const struct rtw89_pci_info *info = rtwdev->pci_info;
259 const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1;
260 const struct rtw89_reg_def *dma_stop2 = &info->dma_stop2;
263 rtw89_write32_clr(rtwdev, dma_stop1->addr, dma_stop1->mask);
264 if (dma_stop2->addr)
265 rtw89_write32_clr(rtwdev, dma_stop2->addr, dma_stop2->mask);
267 rtw89_write32_set(rtwdev, dma_stop1->addr, dma_stop1->mask);
268 if (dma_stop2->addr)
269 rtw89_write32_set(rtwdev, dma_stop2->addr, dma_stop2->mask);
275 const struct rtw89_pci_info *info = rtwdev->pci_info;
276 const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1;
279 rtw89_write32_clr(rtwdev, dma_stop1->addr, B_AX_STOP_CH12);
281 rtw89_write32_set(rtwdev, dma_stop1->addr, B_AX_STOP_CH12);
291 u32 copy_len = rx_info->len - offset;
296 rx_info->len, desc_info->pkt_size, offset, fs, ls);
298 skb->data, rx_info->len);
299 /* length of a single segment skb is desc_info->pkt_size */
301 copy_len = desc_info->pkt_size;
308 skb_put_data(new, skb->data + offset, copy_len);
316 const struct rtw89_pci_info *info = rtwdev->pci_info;
317 u32 wp = bd_ring->wp;
319 if (!info->rx_ring_eq_is_full)
322 if (++wp >= bd_ring->len)
331 struct rtw89_rx_desc_info *desc_info = &rx_ring->diliver_desc;
332 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
333 const struct rtw89_pci_info *info = rtwdev->pci_info;
334 struct sk_buff *new = rx_ring->diliver_skb;
345 skb = rx_ring->buf[skb_idx];
350 bd_ring->wp, ret);
355 fs = info->no_rxbd_fs ? !new : rx_info->fs;
356 ls = rx_info->ls;
360 "unexpected fs/ls=%d/%d tag=%u len=%u new->len=%u\n",
361 fs, ls, rx_info->tag, rx_info->len, new ? new->len : 0);
369 if (desc_info->ready) {
374 rtw89_chip_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size);
376 new = rtw89_alloc_skb_for_rx(rtwdev, desc_info->pkt_size);
380 rx_ring->diliver_skb = new;
383 offset = desc_info->offset + desc_info->rxd_len;
396 if (!desc_info->ready) {
402 rx_ring->diliver_skb = NULL;
403 desc_info->ready = false;
414 rx_ring->diliver_skb = NULL;
415 desc_info->ready = false;
424 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
427 while (cnt && rtwdev->napi_budget_countdown > 0) {
437 cnt -= rx_cnt;
440 rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp);
447 int countdown = rtwdev->napi_budget_countdown;
450 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ];
461 if (rtwdev->napi_budget_countdown <= 0)
464 return budget - countdown;
479 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
480 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
482 info->flags |= IEEE80211_TX_STAT_ACK;
483 tx_ring->tx_acked++;
485 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS)
490 tx_ring->tx_retry_lmt++;
493 tx_ring->tx_life_time++;
496 tx_ring->tx_mac_id_drop++;
504 ieee80211_tx_status_ni(rtwdev->hw, skb);
513 while (cnt--) {
514 txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list);
520 list_del_init(&txwd->list);
523 if (skb_queue_len(&txwd->queue) == 0)
531 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
535 for (i = 0; i < wd_ring->page_num; i++) {
536 txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list);
540 list_del_init(&txwd->list);
549 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
552 u8 txch = tx_ring->txch;
554 if (!list_empty(&txwd->list)) {
559 if (!rtwpci->low_power && !list_empty(&txwd->list))
564 skb_queue_walk_safe(&txwd->queue, skb, tmp) {
565 skb_unlink(skb, &txwd->queue);
568 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len,
574 if (list_empty(&txwd->list))
581 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
588 seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ);
589 qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL);
590 tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS);
598 tx_ring = &rtwpci->tx_rings[txch];
599 wd_ring = &tx_ring->wd_ring;
600 txwd = &wd_ring->pages[seq];
608 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
612 for (i = 0; i < wd_ring->page_num; i++) {
613 txwd = &wd_ring->pages[i];
615 if (!list_empty(&txwd->list))
626 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
639 skb = rx_ring->buf[skb_idx];
644 bd_ring->wp, ret);
649 if (!rx_info->fs || !rx_info->ls) {
654 rtw89_chip_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size);
658 for (; offset + rpp_size <= rx_info->len; offset += rpp_size) {
659 rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset);
678 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
691 cnt -= release_cnt;
694 rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp);
704 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ];
706 spin_lock_bh(&rtwpci->trx_lock);
715 spin_unlock_bh(&rtwpci->trx_lock);
719 rtwdev->napi_budget_countdown -= work_done;
734 rx_ring = &rtwpci->rx_rings[i];
735 bd_ring = &rx_ring->bd_ring;
737 reg_idx = rtw89_read32(rtwdev, bd_ring->addr.idx);
740 hw_idx_next = (hw_idx + 1) % bd_ring->len;
747 i, reg_idx, bd_ring->len);
755 isrs->halt_c2h_isrs = rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs;
756 isrs->isrs[0] = rtw89_read32(rtwdev, R_AX_PCIE_HISR00) & rtwpci->intrs[0];
757 isrs->isrs[1] = rtw89_read32(rtwdev, R_AX_PCIE_HISR10) & rtwpci->intrs[1];
759 rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs);
760 rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isrs->isrs[0]);
761 rtw89_write32(rtwdev, R_AX_PCIE_HISR10, isrs->isrs[1]);
769 isrs->ind_isrs = rtw89_read32(rtwdev, R_AX_PCIE_HISR00_V1) & rtwpci->ind_intrs;
770 isrs->halt_c2h_isrs = isrs->ind_isrs & B_AX_HS0ISR_IND_INT_EN ?
771 rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs : 0;
772 isrs->isrs[0] = isrs->ind_isrs & B_AX_HCI_AXIDMA_INT_EN ?
773 rtw89_read32(rtwdev, R_AX_HAXI_HISR00) & rtwpci->intrs[0] : 0;
774 isrs->isrs[1] = isrs->ind_isrs & B_AX_HS1ISR_IND_INT_EN ?
775 rtw89_read32(rtwdev, R_AX_HISR1) & rtwpci->intrs[1] : 0;
777 if (isrs->halt_c2h_isrs)
778 rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs);
779 if (isrs->isrs[0])
780 rtw89_write32(rtwdev, R_AX_HAXI_HISR00, isrs->isrs[0]);
781 if (isrs->isrs[1])
782 rtw89_write32(rtwdev, R_AX_HISR1, isrs->isrs[1]);
790 isrs->ind_isrs = rtw89_read32(rtwdev, R_BE_PCIE_HISR) & rtwpci->ind_intrs;
791 isrs->halt_c2h_isrs = isrs->ind_isrs & B_BE_HS0ISR_IND_INT ?
792 rtw89_read32(rtwdev, R_BE_HISR0) & rtwpci->halt_c2h_intrs : 0;
793 isrs->isrs[0] = isrs->ind_isrs & B_BE_HCI_AXIDMA_INT ?
794 rtw89_read32(rtwdev, R_BE_HAXI_HISR00) & rtwpci->intrs[0] : 0;
795 isrs->isrs[1] = rtw89_read32(rtwdev, R_BE_PCIE_DMA_ISR) & rtwpci->intrs[1];
797 if (isrs->halt_c2h_isrs)
798 rtw89_write32(rtwdev, R_BE_HISR0, isrs->halt_c2h_isrs);
799 if (isrs->isrs[0])
800 rtw89_write32(rtwdev, R_BE_HAXI_HISR00, isrs->isrs[0]);
801 if (isrs->isrs[1])
802 rtw89_write32(rtwdev, R_BE_PCIE_DMA_ISR, isrs->isrs[1]);
803 rtw89_write32(rtwdev, R_BE_PCIE_HISR, isrs->ind_isrs);
809 rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs);
810 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, rtwpci->intrs[0]);
811 rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, rtwpci->intrs[1]);
825 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00_V1, rtwpci->ind_intrs);
826 rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs);
827 rtw89_write32(rtwdev, R_AX_HAXI_HIMR00, rtwpci->intrs[0]);
828 rtw89_write32(rtwdev, R_AX_HIMR1, rtwpci->intrs[1]);
840 rtw89_write32(rtwdev, R_BE_HIMR0, rtwpci->halt_c2h_intrs);
841 rtw89_write32(rtwdev, R_BE_HAXI_HIMR00, rtwpci->intrs[0]);
842 rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, rtwpci->intrs[1]);
843 rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, rtwpci->ind_intrs);
856 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
859 spin_lock_irqsave(&rtwpci->irq_lock, flags);
863 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
868 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
871 spin_lock_irqsave(&rtwpci->irq_lock, flags);
875 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
880 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
884 rtwdev->napi_budget_countdown = budget;
893 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
894 const struct rtw89_pci_info *info = rtwdev->pci_info;
895 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
899 spin_lock_irqsave(&rtwpci->irq_lock, flags);
901 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
903 if (unlikely(isrs.isrs[0] & gen_def->isr_rdu))
906 if (unlikely(isrs.halt_c2h_isrs & gen_def->isr_halt_c2h))
909 if (unlikely(isrs.halt_c2h_isrs & gen_def->isr_wdt_timeout))
912 if (unlikely(rtwpci->under_recovery))
915 if (unlikely(rtwpci->low_power)) {
920 if (likely(rtwpci->running)) {
922 napi_schedule(&rtwdev->napi);
929 spin_lock_irqsave(&rtwpci->irq_lock, flags);
930 if (likely(rtwpci->running))
932 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
939 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
943 spin_lock_irqsave(&rtwpci->irq_lock, flags);
948 if (unlikely(!rtwpci->running)) {
955 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
1072 const struct rtw89_pci_info *info = rtwdev->pci_info;
1075 return -EINVAL;
1077 *addr = &info->dma_addr_set->tx[txch];
1086 const struct rtw89_pci_info *info = rtwdev->pci_info;
1089 return -EINVAL;
1091 *addr = &info->dma_addr_set->rx[rxch];
1098 struct rtw89_pci_dma_ring *bd_ring = &ring->bd_ring;
1101 if (bd_ring->rp > bd_ring->wp)
1102 return bd_ring->rp - bd_ring->wp - 1;
1104 return bd_ring->len - (bd_ring->wp - bd_ring->rp) - 1;
1110 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1111 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12];
1114 spin_lock_bh(&rtwpci->trx_lock);
1117 spin_unlock_bh(&rtwpci->trx_lock);
1126 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1127 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
1128 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1131 spin_lock_bh(&rtwpci->trx_lock);
1134 cnt = min(cnt, wd_ring->curr_num);
1135 spin_unlock_bh(&rtwpci->trx_lock);
1143 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1144 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
1145 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1146 const struct rtw89_chip_info *chip = rtwdev->chip;
1152 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ];
1154 spin_lock_bh(&rtwpci->trx_lock);
1156 wd_cnt = wd_ring->curr_num;
1171 wd_cnt = wd_ring->curr_num;
1178 if (rtwpci->low_power || chip->small_fifo_size)
1189 spin_unlock_bh(&rtwpci->trx_lock);
1197 if (rtwdev->hci.paused)
1208 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1209 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1212 spin_lock_bh(&rtwpci->trx_lock);
1214 addr = bd_ring->addr.idx;
1215 host_idx = bd_ring->wp;
1218 spin_unlock_bh(&rtwpci->trx_lock);
1224 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1227 len = bd_ring->len;
1228 host_idx = bd_ring->wp + n_txbd;
1229 host_idx = host_idx < len ? host_idx : host_idx - len;
1231 bd_ring->wp = host_idx;
1236 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1237 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
1239 if (rtwdev->hci.paused) {
1240 set_bit(txch, rtwpci->kick_map);
1249 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1254 if (!test_and_clear_bit(txch, rtwpci->kick_map))
1257 tx_ring = &rtwpci->tx_rings[txch];
1264 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1265 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
1266 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1276 cur_idx = rtw89_read32(rtwdev, bd_ring->addr.idx);
1278 if (cur_rp == bd_ring->wp)
1291 const struct rtw89_pci_info *info = rtwdev->pci_info;
1298 if (info->tx_dma_ch_mask & BIT(i))
1309 __rtw89_pci_ops_flush_txchs(rtwdev, BIT(RTW89_TXCH_NUM) - 1, drop);
1314 dma_addr_t dma, u8 *add_info_nr)
1319 txaddr_info->length = cpu_to_le16(total_len);
1321 option |= le16_encode_bits(upper_32_bits(dma), RTW89_PCI_ADDR_HIGH_MASK);
1322 txaddr_info->option = option;
1323 txaddr_info->dma = cpu_to_le32(dma);
1333 dma_addr_t dma, u8 *add_info_nr)
1344 remain -= len;
1349 length_option |= u16_encode_bits(upper_32_bits(dma),
1351 txaddr_info->length_opt = cpu_to_le16(length_option);
1352 txaddr_info->dma_low_lsb = cpu_to_le16(FIELD_GET(GENMASK(15, 0), dma));
1353 txaddr_info->dma_low_msb = cpu_to_le16(FIELD_GET(GENMASK(31, 16), dma));
1355 dma += len;
1373 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1374 const struct rtw89_chip_info *chip = rtwdev->chip;
1375 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1378 struct pci_dev *pdev = rtwpci->pdev;
1379 struct sk_buff *skb = tx_req->skb;
1382 bool en_wd_info = desc_info->en_wd_info;
1386 dma_addr_t dma;
1389 dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE);
1390 if (dma_mapping_error(&pdev->dev, dma)) {
1391 rtw89_err(rtwdev, "failed to map skb dma data\n");
1392 ret = -EBUSY;
1396 tx_data->dma = dma;
1397 rcu_assign_pointer(skb_data->wait, NULL);
1400 txwd_len = chip->txwd_body_size;
1401 txwd_len += en_wd_info ? chip->txwd_info_size : 0;
1404 txwp_info = txwd->vaddr + txwd_len;
1406 txwp_info = (struct rtw89_pci_tx_wp_info *)((u8 *)txwd->vaddr + txwd_len);
1408 txwp_info->seq0 = cpu_to_le16(txwd->seq | RTW89_PCI_TXWP_VALID);
1409 txwp_info->seq1 = 0;
1410 txwp_info->seq2 = 0;
1411 txwp_info->seq3 = 0;
1413 tx_ring->tx_cnt++;
1415 txaddr_info_addr = txwd->vaddr + txwd_len + txwp_len;
1417 txaddr_info_addr = (u8 *)txwd->vaddr + txwd_len + txwp_len;
1420 rtw89_chip_fill_txaddr_info(rtwdev, txaddr_info_addr, skb->len,
1421 dma, &desc_info->addr_info_nr);
1423 txwd->len = txwd_len + txwp_len + txaddr_info_len;
1425 rtw89_chip_fill_txdesc(rtwdev, desc_info, txwd->vaddr);
1427 skb_queue_tail(&txwd->queue, skb);
1440 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1441 const struct rtw89_chip_info *chip = rtwdev->chip;
1442 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1444 int txdesc_size = chip->h2c_desc_size;
1445 struct pci_dev *pdev = rtwpci->pdev;
1446 struct sk_buff *skb = tx_req->skb;
1448 dma_addr_t dma;
1455 dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE);
1456 if (dma_mapping_error(&pdev->dev, dma)) {
1457 rtw89_err(rtwdev, "failed to map fwcmd dma data\n");
1458 return -EBUSY;
1461 tx_data->dma = dma;
1463 opt |= le16_encode_bits(upper_32_bits(dma), RTW89_PCI_TXBD_OPT_DMA_HI);
1464 txbd->opt = opt;
1465 txbd->length = cpu_to_le16(skb->len);
1466 txbd->dma = cpu_to_le32(tx_data->dma);
1467 skb_queue_tail(&rtwpci->h2c_queue, skb);
1487 if (tx_ring->txch == RTW89_TXCH_CH12)
1493 ret = -ENOSPC;
1499 rtw89_err(rtwdev, "failed to submit TXWD %d\n", txwd->seq);
1503 list_add_tail(&txwd->list, &tx_ring->busy_pages);
1506 opt |= le16_encode_bits(upper_32_bits(txwd->paddr), RTW89_PCI_TXBD_OPT_DMA_HI);
1507 txbd->opt = opt;
1508 txbd->length = cpu_to_le16(txwd->len);
1509 txbd->dma = cpu_to_le32(txwd->paddr);
1524 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1530 /* check the tx type and dma channel for fw cmd queue */
1532 tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD) &&
1534 tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD)) {
1535 rtw89_err(rtwdev, "only fw cmd uses dma channel 12\n");
1536 return -EINVAL;
1539 tx_ring = &rtwpci->tx_rings[txch];
1540 spin_lock_bh(&rtwpci->trx_lock);
1545 ret = -ENOSPC;
1556 spin_unlock_bh(&rtwpci->trx_lock);
1560 spin_unlock_bh(&rtwpci->trx_lock);
1566 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1569 ret = rtw89_pci_tx_write(rtwdev, tx_req, desc_info->ch_dma);
1571 rtw89_err(rtwdev, "failed to TX Queue %d\n", desc_info->ch_dma);
1608 const struct rtw89_pci_info *info = rtwdev->pci_info;
1609 u32 addr = info->wp_sel_addr;
1613 if (!info->wp_sel_addr)
1627 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1628 const struct rtw89_pci_info *info = rtwdev->pci_info;
1629 const struct rtw89_pci_bd_ram *bd_ram_table = *info->bd_ram_table;
1642 if (info->tx_dma_ch_mask & BIT(i))
1645 tx_ring = &rtwpci->tx_rings[i];
1646 bd_ring = &tx_ring->bd_ring;
1648 addr_num = bd_ring->addr.num;
1649 addr_bdram = bd_ring->addr.bdram;
1650 addr_desa_l = bd_ring->addr.desa_l;
1651 bd_ring->wp = 0;
1652 bd_ring->rp = 0;
1654 rtw89_write16(rtwdev, addr_num, bd_ring->len);
1656 val32 = FIELD_PREP(BDRAM_SIDX_MASK, bd_ram->start_idx) |
1657 FIELD_PREP(BDRAM_MAX_MASK, bd_ram->max_num) |
1658 FIELD_PREP(BDRAM_MIN_MASK, bd_ram->min_num);
1662 rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma);
1663 rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma));
1667 rx_ring = &rtwpci->rx_rings[i];
1668 bd_ring = &rx_ring->bd_ring;
1669 addr_num = bd_ring->addr.num;
1670 addr_idx = bd_ring->addr.idx;
1671 addr_desa_l = bd_ring->addr.desa_l;
1672 if (info->rx_ring_eq_is_full)
1673 bd_ring->wp = bd_ring->len - 1;
1675 bd_ring->wp = 0;
1676 bd_ring->rp = 0;
1677 rx_ring->diliver_skb = NULL;
1678 rx_ring->diliver_desc.ready = false;
1679 rx_ring->target_rx_tag = 0;
1681 rtw89_write16(rtwdev, addr_num, bd_ring->len);
1682 rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma);
1683 rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma));
1685 if (info->rx_ring_eq_is_full)
1686 rtw89_write16(rtwdev, addr_idx, bd_ring->wp);
1701 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1702 const struct rtw89_pci_info *info = rtwdev->pci_info;
1707 spin_lock_bh(&rtwpci->trx_lock);
1709 if (info->tx_dma_ch_mask & BIT(txch))
1713 skb_queue_len(&rtwpci->h2c_queue), true);
1716 rtw89_pci_release_tx_ring(rtwdev, &rtwpci->tx_rings[txch]);
1718 spin_unlock_bh(&rtwpci->trx_lock);
1723 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1726 spin_lock_irqsave(&rtwpci->irq_lock, flags);
1727 rtwpci->running = true;
1729 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
1734 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1737 spin_lock_irqsave(&rtwpci->irq_lock, flags);
1738 rtwpci->running = false;
1740 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
1753 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1754 struct pci_dev *pdev = rtwpci->pdev;
1757 synchronize_irq(pdev->irq);
1763 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1764 struct pci_dev *pdev = rtwpci->pdev;
1768 synchronize_irq(pdev->irq);
1769 if (test_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
1770 napi_synchronize(&rtwdev->napi);
1780 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1781 const struct rtw89_pci_info *info = rtwdev->pci_info;
1782 const struct rtw89_pci_bd_idx_addr *bd_idx_addr = info->bd_idx_addr_low_power;
1783 const struct rtw89_pci_ch_dma_addr_set *dma_addr_set = info->dma_addr_set;
1792 tx_ring = &rtwpci->tx_rings[i];
1793 tx_ring->bd_ring.addr.idx = low_power ?
1794 bd_idx_addr->tx_bd_addrs[i] :
1795 dma_addr_set->tx[i].idx;
1799 rx_ring = &rtwpci->rx_rings[i];
1800 rx_ring->bd_ring.addr.idx = low_power ?
1801 bd_idx_addr->rx_bd_addrs[i] :
1802 dma_addr_set->rx[i].idx;
1810 WARN(!rtwdev->hci.paused, "HCI isn't paused\n");
1821 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1823 u32 val = readl(rtwpci->mmap + addr);
1827 val = bus_read_4((struct resource *)rtwpci->mmap, addr);
1828 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R32 (%#010x) -> %#010x\n", addr, val);
1841 val = readl(rtwpci->mmap + addr);
1843 val = bus_read_4((struct resource *)rtwpci->mmap, addr);
1844 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R32 (%#010x) -> %#010x\n", addr, val);
1853 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1858 return readb(rtwpci->mmap + addr);
1863 val = bus_read_1((struct resource *)rtwpci->mmap, addr);
1864 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R08 (%#010x) -> %#04x\n", addr, val);
1877 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1882 return readw(rtwpci->mmap + addr);
1887 val = bus_read_2((struct resource *)rtwpci->mmap, addr);
1888 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R16 (%#010x) -> %#06x\n", addr, val);
1901 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1905 return readl(rtwpci->mmap + addr);
1910 val = bus_read_4((struct resource *)rtwpci->mmap, addr);
1911 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "R32 (%#010x) -> %#010x\n", addr, val);
1921 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1924 writeb(data, rtwpci->mmap + addr);
1926 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "W08 (%#010x) <- %#04x\n", addr, data);
1927 return (bus_write_1((struct resource *)rtwpci->mmap, addr, data));
1933 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1936 writew(data, rtwpci->mmap + addr);
1938 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "W16 (%#010x) <- %#06x\n", addr, data);
1939 return (bus_write_2((struct resource *)rtwpci->mmap, addr, data));
1945 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1948 writel(data, rtwpci->mmap + addr);
1950 rtw89_debug(rtwdev, RTW89_DBG_IO_RW, "W32 (%#010x) <- %#010x\n", addr, data);
1951 return (bus_write_4((struct resource *)rtwpci->mmap, addr, data));
1957 const struct rtw89_pci_info *info = rtwdev->pci_info;
1960 rtw89_write32_set(rtwdev, info->init_cfg_reg,
1961 info->rxhci_en_bit | info->txhci_en_bit);
1963 rtw89_write32_clr(rtwdev, info->init_cfg_reg,
1964 info->rxhci_en_bit | info->txhci_en_bit);
1969 const struct rtw89_pci_info *info = rtwdev->pci_info;
1970 const struct rtw89_reg_def *reg = &info->dma_io_stop;
1973 rtw89_write32_clr(rtwdev, reg->addr, reg->mask);
1975 rtw89_write32_set(rtwdev, reg->addr, reg->mask);
2006 return -EINVAL;
2147 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
2148 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2149 struct pci_dev *pdev = rtwpci->pdev;
2165 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
2166 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2167 struct pci_dev *pdev = rtwpci->pdev;
2244 return -EINVAL;
2288 return -EOPNOTSUPP;
2339 mgn_set = tar * INTF_INTGRA_HOSTREF_V1 / INTF_INTGRA_MINREF_V1 - tar;
2417 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2449 if (rtwdev->chip->chip_id != RTL8852C)
2513 if (!test_bit(RTW89_QUIRK_PCI_BER, rtwdev->quirks))
2527 if (rtwdev->chip->chip_id != RTL8852A)
2535 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2547 if (rtwdev->chip->chip_id != RTL8852A)
2565 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2575 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2582 } else if (rtwdev->chip->chip_id == RTL8852C) {
2607 if (rtwdev->chip->chip_id != RTL8852C)
2616 if (!(rtwdev->chip->chip_id == RTL8852C && rtwdev->hal.cv == CHIP_CAV))
2624 if (!(rtwdev->chip->chip_id == RTL8852C && rtwdev->hal.cv == CHIP_CAV))
2636 if (rtwdev->chip->chip_id != RTL8852C)
2644 if (rtwdev->chip->chip_id != RTL8852C)
2652 if (rtwdev->chip->chip_id == RTL8852C)
2661 const struct rtw89_pci_info *info = rtwdev->pci_info;
2664 if (rtwdev->chip->chip_id == RTL8852C)
2668 if (info->lbc_en == MAC_AX_PCIE_ENABLE) {
2669 lbc = u32_replace_bits(lbc, info->lbc_tmr, B_AX_LBC_TIMER);
2680 const struct rtw89_pci_info *info = rtwdev->pci_info;
2683 if (rtwdev->chip->chip_id != RTL8852C)
2686 if (info->io_rcy_en == MAC_AX_PCIE_ENABLE) {
2688 info->io_rcy_tmr);
2707 if (rtwdev->chip->chip_id == RTL8852C)
2713 if (rtwdev->chip->chip_id == RTL8852A)
2720 if (rtwdev->chip->chip_id == RTL8852C)
2729 const struct rtw89_pci_info *info = rtwdev->pci_info;
2730 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2734 u32 rxbd_rwptr_clr = info->rxbd_rwptr_clr_reg;
2735 u32 txbd_rwptr_clr2 = info->txbd_rwptr_clr2_reg;
2740 /* clear DMA indexes */
2751 const struct rtw89_pci_info *info = rtwdev->pci_info;
2752 u32 dma_busy1 = info->dma_busy1.addr;
2753 u32 dma_busy2 = info->dma_busy2_reg;
2757 check = info->dma_busy1.mask;
2779 const struct rtw89_pci_info *info = rtwdev->pci_info;
2780 u32 dma_busy3 = info->dma_busy3_reg;
2815 const struct rtw89_pci_info *info = rtwdev->pci_info;
2816 enum mac_ax_bd_trunc_mode txbd_trunc_mode = info->txbd_trunc_mode;
2817 enum mac_ax_bd_trunc_mode rxbd_trunc_mode = info->rxbd_trunc_mode;
2818 enum mac_ax_rxbd_mode rxbd_mode = info->rxbd_mode;
2819 enum mac_ax_tag_mode tag_mode = info->tag_mode;
2820 enum mac_ax_wd_dma_intvl wd_dma_idle_intvl = info->wd_dma_idle_intvl;
2821 enum mac_ax_wd_dma_intvl wd_dma_act_intvl = info->wd_dma_act_intvl;
2822 enum mac_ax_tx_burst tx_burst = info->tx_burst;
2823 enum mac_ax_rx_burst rx_burst = info->rx_burst;
2824 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2825 u8 cv = rtwdev->hal.cv;
2845 rtw89_write32_clr(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit);
2847 rtw89_write32_set(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit);
2874 rtw89_write32_mask(rtwdev, info->exp_ctrl_reg, info->max_tag_num_mask,
2875 info->multi_tag_num);
2904 const struct rtw89_pci_info *info = rtwdev->pci_info;
2908 if (rtwdev->chip->chip_id == RTL8852A) {
2912 info->ltr_set(rtwdev, false);
2921 const struct rtw89_pci_info *info = rtwdev->pci_info;
2962 rtw89_write32_set(rtwdev, info->dma_stop1.addr, B_AX_STOP_WPDMA);
2964 /* stop DMA activities */
2969 rtw89_err(rtwdev, "[ERR] poll pcie dma all idle\n");
2989 /* start DMA activities */
3002 int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en)
3006 if (!en)
3011 return -EINVAL;
3014 return -EINVAL;
3017 return -EINVAL;
3020 return -EINVAL;
3037 int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en)
3044 return -EINVAL;
3047 return -EINVAL;
3050 return -EINVAL;
3053 return -EINVAL;
3056 return -EINVAL;
3058 if (!en) {
3069 if (en)
3086 const struct rtw89_pci_info *info = rtwdev->pci_info;
3087 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3090 ret = info->ltr_set(rtwdev, true);
3100 /* ADDR info 8-byte mode */
3106 /* enable DMA for all queues */
3110 rtw89_write32_clr(rtwdev, info->dma_stop1.addr,
3119 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3129 pci_set_drvdata(pdev, rtwdev->hw);
3131 rtwpci->pdev = pdev;
3144 const struct rtw89_chip_info *chip = rtwdev->chip;
3146 switch (chip->chip_id) {
3159 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3160 struct pci_dev *bridge = pci_upstream_bridge(rtwpci->pdev);
3168 switch (bridge->vendor) {
3172 if (bridge->device == 0x2806)
3182 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3184 if (!rtwpci->enable_dac)
3196 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3210 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
3212 rtwpci->enable_dac = true;
3215 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3218 "failed to set dma and consistent mask to 32/36-bit\n");
3228 rtwpci->mmap = pci_iomap(pdev, bar_id, resource_len);
3229 if (!rtwpci->mmap) {
3231 ret = -EIO;
3246 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3248 if (rtwpci->mmap) {
3249 pci_iounmap(pdev, rtwpci->mmap);
3258 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
3259 u8 *head = wd_ring->head;
3260 dma_addr_t dma = wd_ring->dma;
3261 u32 page_size = wd_ring->page_size;
3262 u32 page_num = wd_ring->page_num;
3265 dma_free_coherent(&pdev->dev, ring_sz, head, dma);
3266 wd_ring->head = NULL;
3275 dma_addr_t dma;
3277 head = tx_ring->bd_ring.head;
3278 dma = tx_ring->bd_ring.dma;
3279 ring_sz = tx_ring->bd_ring.desc_size * tx_ring->bd_ring.len;
3280 dma_free_coherent(&pdev->dev, ring_sz, head, dma);
3282 tx_ring->bd_ring.head = NULL;
3288 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3289 const struct rtw89_pci_info *info = rtwdev->pci_info;
3294 if (info->tx_dma_ch_mask & BIT(i))
3296 tx_ring = &rtwpci->tx_rings[i];
3308 dma_addr_t dma;
3311 int ring_sz = rx_ring->bd_ring.desc_size * rx_ring->bd_ring.len;
3314 buf_sz = rx_ring->buf_sz;
3315 for (i = 0; i < rx_ring->bd_ring.len; i++) {
3316 skb = rx_ring->buf[i];
3321 dma = rx_info->dma;
3322 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE);
3324 rx_ring->buf[i] = NULL;
3327 head = rx_ring->bd_ring.head;
3328 dma = rx_ring->bd_ring.dma;
3329 dma_free_coherent(&pdev->dev, ring_sz, head, dma);
3331 rx_ring->bd_ring.head = NULL;
3337 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3342 rx_ring = &rtwpci->rx_rings[i];
3360 dma_addr_t dma;
3363 return -EINVAL;
3365 dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE);
3366 if (dma_mapping_error(&pdev->dev, dma))
3367 return -EBUSY;
3373 rx_bd->buf_size = cpu_to_le16(buf_sz);
3374 rx_bd->dma = cpu_to_le32(dma);
3375 rx_bd->opt = le16_encode_bits(upper_32_bits(dma), RTW89_PCI_RXBD_OPT_DMA_HI);
3376 rx_info->dma = dma;
3386 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
3388 dma_addr_t dma;
3402 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL);
3404 return -ENOMEM;
3406 INIT_LIST_HEAD(&wd_ring->free_pages);
3407 wd_ring->head = head;
3408 wd_ring->dma = dma;
3409 wd_ring->page_size = page_size;
3410 wd_ring->page_num = page_num;
3414 txwd = &wd_ring->pages[i];
3415 cur_paddr = dma + page_offset;
3418 skb_queue_head_init(&txwd->queue);
3419 INIT_LIST_HEAD(&txwd->list);
3420 txwd->paddr = cur_paddr;
3421 txwd->vaddr = cur_vaddr;
3422 txwd->len = page_size;
3423 txwd->seq = i;
3441 dma_addr_t dma;
3456 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL);
3458 ret = -ENOMEM;
3462 INIT_LIST_HEAD(&tx_ring->busy_pages);
3463 tx_ring->bd_ring.head = head;
3464 tx_ring->bd_ring.dma = dma;
3465 tx_ring->bd_ring.len = len;
3466 tx_ring->bd_ring.desc_size = desc_size;
3467 tx_ring->bd_ring.addr = *txch_addr;
3468 tx_ring->bd_ring.wp = 0;
3469 tx_ring->bd_ring.rp = 0;
3470 tx_ring->txch = txch;
3483 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3484 const struct rtw89_pci_info *info = rtwdev->pci_info;
3492 if (info->tx_dma_ch_mask & BIT(i))
3494 tx_ring = &rtwpci->tx_rings[i];
3514 tx_ring = &rtwpci->tx_rings[i];
3526 const struct rtw89_pci_info *info = rtwdev->pci_info;
3530 dma_addr_t dma;
3542 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL);
3544 ret = -ENOMEM;
3548 rx_ring->bd_ring.head = head;
3549 rx_ring->bd_ring.dma = dma;
3550 rx_ring->bd_ring.len = len;
3551 rx_ring->bd_ring.desc_size = desc_size;
3552 rx_ring->bd_ring.addr = *rxch_addr;
3553 if (info->rx_ring_eq_is_full)
3554 rx_ring->bd_ring.wp = len - 1;
3556 rx_ring->bd_ring.wp = 0;
3557 rx_ring->bd_ring.rp = 0;
3558 rx_ring->buf_sz = buf_sz;
3559 rx_ring->diliver_skb = NULL;
3560 rx_ring->diliver_desc.ready = false;
3561 rx_ring->target_rx_tag = 0;
3566 ret = -ENOMEM;
3570 memset(skb->data, 0, buf_sz);
3571 rx_ring->buf[i] = skb;
3581 rx_ring->buf[i] = NULL;
3591 skb = rx_ring->buf[i];
3594 dma = *((dma_addr_t *)skb->cb);
3595 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE);
3597 rx_ring->buf[i] = NULL;
3600 head = rx_ring->bd_ring.head;
3601 dma = rx_ring->bd_ring.dma;
3602 dma_free_coherent(&pdev->dev, ring_sz, head, dma);
3604 rx_ring->bd_ring.head = NULL;
3612 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3620 rx_ring = &rtwpci->rx_rings[i];
3636 rx_ring = &rtwpci->rx_rings[i];
3650 rtw89_err(rtwdev, "failed to alloc dma tx rings\n");
3656 rtw89_err(rtwdev, "failed to alloc dma rx rings\n");
3671 skb_queue_head_init(&rtwpci->h2c_queue);
3672 skb_queue_head_init(&rtwpci->h2c_release_queue);
3678 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3695 spin_lock_init(&rtwpci->irq_lock);
3696 spin_lock_init(&rtwpci->trx_lock);
3709 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3714 skb_queue_len(&rtwpci->h2c_queue), true);
3719 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3720 const struct rtw89_chip_info *chip = rtwdev->chip;
3723 if (chip->chip_id == RTL8851B)
3726 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | 0;
3728 if (rtwpci->under_recovery) {
3729 rtwpci->intrs[0] = hs0isr_ind_int_en;
3730 rtwpci->intrs[1] = 0;
3732 rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN |
3741 rtwpci->intrs[1] = B_AX_HC10ISR_IND_INT_EN;
3748 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3750 rtwpci->ind_intrs = B_AX_HS0ISR_IND_INT_EN;
3751 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN;
3752 rtwpci->intrs[0] = 0;
3753 rtwpci->intrs[1] = 0;
3758 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3760 rtwpci->ind_intrs = B_AX_HCI_AXIDMA_INT_EN |
3763 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN;
3764 rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN |
3771 rtwpci->intrs[1] = B_AX_GPIO18_INT_EN;
3776 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3778 rtwpci->ind_intrs = B_AX_HS1ISR_IND_INT_EN |
3780 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN;
3781 rtwpci->intrs[0] = 0;
3782 rtwpci->intrs[1] = B_AX_GPIO18_INT_EN;
3787 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3789 if (rtwpci->under_recovery)
3791 else if (rtwpci->low_power)
3800 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3802 rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0;
3803 rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN;
3804 rtwpci->intrs[0] = 0;
3805 rtwpci->intrs[1] = 0;
3810 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3812 rtwpci->ind_intrs = B_BE_HCI_AXIDMA_INT_EN0 |
3814 rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN;
3815 rtwpci->intrs[0] = B_BE_RDU_CH1_INT_IMR_V1 |
3817 rtwpci->intrs[1] = B_BE_PCIE_RX_RX0P2_IMR0_V1 |
3823 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3825 rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0 |
3827 rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN;
3828 rtwpci->intrs[0] = 0;
3829 rtwpci->intrs[1] = B_BE_PCIE_RX_RX0P2_IMR0_V1 |
3835 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3837 if (rtwpci->under_recovery)
3839 else if (rtwpci->low_power)
3859 ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq,
3881 devm_free_irq(rtwdev->dev, pdev->irq, rtwdev);
3899 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3900 struct pci_dev *pdev = rtwpci->pdev;
3905 if (rtwdev->chip->chip_id != RTL8852C)
3944 return -EOPNOTSUPP;
3954 const struct rtw89_pci_info *info = rtwdev->pci_info;
3955 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
3960 gen_def->clkreq_set(rtwdev, enable);
3965 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3999 const struct rtw89_pci_info *info = rtwdev->pci_info;
4000 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
4005 gen_def->aspm_set(rtwdev, enable);
4010 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
4049 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
4050 const struct rtw89_pci_info *info = rtwdev->pci_info;
4051 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4052 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
4053 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
4056 if (rtwdev->scanning ||
4069 rtw89_write32(rtwdev, info->mit_addr, val);
4074 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
4075 struct pci_dev *pdev = rtwpci->pdev;
4088 * settings (ex. CLKREQ# not Bi-Direction), it could lead to device
4110 const struct rtw89_pci_info *info = rtwdev->pci_info;
4111 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
4116 gen_def->l1ss_set(rtwdev, enable);
4121 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
4153 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
4154 struct pci_dev *pdev = rtwpci->pdev;
4172 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
4173 struct pci_dev *pdev = rtwpci->pdev;
4191 return -EINVAL;
4201 if (rtwdev->chip->chip_id == RTL8852C)
4230 if (rtwdev->chip->chip_id == RTL8852C)
4248 const struct rtw89_pci_info *info = rtwdev->pci_info;
4249 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
4254 ret = gen_def->lv1rst_stop_dma(rtwdev);
4256 rtw89_err(rtwdev, "lv1 rcvy pci stop dma fail\n");
4261 ret = gen_def->lv1rst_start_dma(rtwdev);
4263 rtw89_err(rtwdev, "lv1 rcvy pci start dma fail\n");
4267 return -EINVAL;
4275 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
4278 if (rtwdev->chip->chip_id == RTL8852C) {
4296 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
4297 const struct rtw89_pci_info *info = rtwdev->pci_info;
4298 const struct rtw89_pci_gen_def *gen_def = info->gen_def;
4302 rtwdev->napi_budget_countdown = budget;
4304 rtw89_write32(rtwdev, gen_def->isr_clear_rpq.addr, gen_def->isr_clear_rpq.data);
4305 work_done = rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown);
4309 rtw89_write32(rtwdev, gen_def->isr_clear_rxq.addr, gen_def->isr_clear_rxq.data);
4310 work_done += rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown);
4312 spin_lock_irqsave(&rtwpci->irq_lock, flags);
4313 if (likely(rtwpci->running))
4315 spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
4332 if (ssid_quirks->vendor == 0 && ssid_quirks->device == 0)
4335 if (ssid_quirks->vendor != pdev->vendor ||
4336 ssid_quirks->device != pdev->device ||
4337 ssid_quirks->subsystem_vendor != pdev->subsystem_vendor ||
4338 ssid_quirks->subsystem_device != pdev->subsystem_device)
4341 bitmap_or(rtwdev->quirks, rtwdev->quirks, &ssid_quirks->bitmap,
4343 rtwdev->custid = ssid_quirks->custid;
4348 (int)sizeof(rtwdev->quirks), rtwdev->quirks, rtwdev->custid);
4354 struct rtw89_dev *rtwdev = hw->priv;
4355 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
4375 if (rtwdev->chip->chip_id == RTL8852C)
4400 struct rtw89_dev *rtwdev = hw->priv;
4401 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
4508 info = (const struct rtw89_driver_info *)id->driver_data;
4510 rtwdev = rtw89_alloc_ieee80211_hw(&pdev->dev,
4512 info->chip, info->variant);
4514 dev_err(&pdev->dev, "failed to allocate hw\n");
4515 return -ENOMEM;
4518 pci_info = info->bus.pci;
4520 rtwdev->pci_info = info->bus.pci;
4521 rtwdev->hci.ops = &rtw89_pci_ops;
4522 rtwdev->hci.type = RTW89_HCI_TYPE_PCIE;
4523 rtwdev->hci.rpwm_addr = pci_info->rpwm_addr;
4524 rtwdev->hci.cpwm_addr = pci_info->cpwm_addr;
4526 rtw89_check_quirks(rtwdev, info->quirks);
4527 rtw89_check_pci_ssid_quirks(rtwdev, pdev, pci_info->ssid_quirks);
4529 SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev);
4575 set_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags);
4601 rtwdev = hw->priv;