Lines Matching +full:reg +full:- +full:init
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #include "reg.h"
68 test_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags)) in rtw89_mac_check_mac_en_be()
71 test_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags)) in rtw89_mac_check_mac_en_be()
74 test_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags)) in rtw89_mac_check_mac_en_be()
77 return -EFAULT; in rtw89_mac_check_mac_en_be()
82 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; in is_qta_poh()
87 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_get_mix_info_be()
88 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; in hfc_get_mix_info_be()
89 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; in hfc_get_mix_info_be()
90 struct rtw89_hfc_pub_info *info = ¶m->pub_info; in hfc_get_mix_info_be()
94 info->g0_used = u32_get_bits(val, B_BE_G0_USE_PG_MASK); in hfc_get_mix_info_be()
95 info->g1_used = u32_get_bits(val, B_BE_G1_USE_PG_MASK); in hfc_get_mix_info_be()
98 info->g0_aval = u32_get_bits(val, B_BE_G0_AVAL_PG_MASK); in hfc_get_mix_info_be()
99 info->g1_aval = u32_get_bits(val, B_BE_G1_AVAL_PG_MASK); in hfc_get_mix_info_be()
100 info->pub_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO2), in hfc_get_mix_info_be()
102 info->wp_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_WP_PAGE_INFO1), in hfc_get_mix_info_be()
106 param->en = !!(val & B_BE_HCI_FC_EN); in hfc_get_mix_info_be()
107 param->h2c_en = !!(val & B_BE_HCI_FC_CH12_EN); in hfc_get_mix_info_be()
108 param->mode = u32_get_bits(val, B_BE_HCI_FC_MODE_MASK); in hfc_get_mix_info_be()
109 prec_cfg->ch011_full_cond = u32_get_bits(val, B_BE_HCI_FC_WD_FULL_COND_MASK); in hfc_get_mix_info_be()
110 prec_cfg->h2c_full_cond = u32_get_bits(val, B_BE_HCI_FC_CH12_FULL_COND_MASK); in hfc_get_mix_info_be()
111 prec_cfg->wp_ch07_full_cond = in hfc_get_mix_info_be()
113 prec_cfg->wp_ch811_full_cond = in hfc_get_mix_info_be()
117 prec_cfg->ch011_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH011_V1_MASK); in hfc_get_mix_info_be()
118 prec_cfg->h2c_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH12_V1_MASK); in hfc_get_mix_info_be()
121 pub_cfg->pub_max = u32_get_bits(val, B_BE_PUBPG_ALL_MASK); in hfc_get_mix_info_be()
124 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK); in hfc_get_mix_info_be()
125 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK); in hfc_get_mix_info_be()
128 pub_cfg->wp_thrd = u32_get_bits(val, B_BE_WP_THRD_MASK); in hfc_get_mix_info_be()
131 pub_cfg->grp0 = u32_get_bits(val, B_BE_PUBPG_G0_MASK); in hfc_get_mix_info_be()
132 pub_cfg->grp1 = u32_get_bits(val, B_BE_PUBPG_G1_MASK); in hfc_get_mix_info_be()
137 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_h2c_cfg_be()
138 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; in hfc_h2c_cfg_be()
141 val = u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK); in hfc_h2c_cfg_be()
147 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_mix_cfg_be()
148 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; in hfc_mix_cfg_be()
149 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; in hfc_mix_cfg_be()
152 val = u32_encode_bits(prec_cfg->ch011_prec, B_BE_PREC_PAGE_CH011_V1_MASK) | in hfc_mix_cfg_be()
153 u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK); in hfc_mix_cfg_be()
156 val = u32_encode_bits(pub_cfg->pub_max, B_BE_PUBPG_ALL_MASK); in hfc_mix_cfg_be()
159 val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) | in hfc_mix_cfg_be()
160 u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK); in hfc_mix_cfg_be()
164 param->mode, B_BE_HCI_FC_MODE_MASK); in hfc_mix_cfg_be()
165 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, in hfc_mix_cfg_be()
167 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, in hfc_mix_cfg_be()
169 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, in hfc_mix_cfg_be()
171 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, in hfc_mix_cfg_be()
178 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_func_en_be()
182 param->en = en; in hfc_func_en_be()
183 param->h2c_en = h2c_en; in hfc_func_en_be()
216 wde_size_cfg = cfg->wde_size; in dle_mix_cfg_be()
217 ple_size_cfg = cfg->ple_size; in dle_mix_cfg_be()
221 switch (wde_size_cfg->pge_size) { in dle_mix_cfg_be()
233 return -EINVAL; in dle_mix_cfg_be()
236 bound = wde_size_cfg->srt_ofst / DLE_BOUND_UNIT; in dle_mix_cfg_be()
238 val = u32_replace_bits(val, wde_size_cfg->lnk_pge_num, in dle_mix_cfg_be()
244 switch (ple_size_cfg->pge_size) { in dle_mix_cfg_be()
248 return -EINVAL; in dle_mix_cfg_be()
259 bound = ple_size_cfg->srt_ofst / DLE_BOUND_UNIT; in dle_mix_cfg_be()
261 val = u32_replace_bits(val, ple_size_cfg->lnk_pge_num, in dle_mix_cfg_be()
270 u32 reg, mask; in chk_dle_rdy_be() local
274 reg = R_AX_WDE_INI_STATUS; in chk_dle_rdy_be()
277 reg = R_AX_PLE_INI_STATUS; in chk_dle_rdy_be()
282 2000, false, rtwdev, reg); in chk_dle_rdy_be()
295 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
303 ext_wde_min_qt_wcpu : min_cfg->wcpu; in wde_quota_cfg_be()
304 u16 max_qt_wcpu = max(max_cfg->wcpu, min_qt_wcpu); in wde_quota_cfg_be()
347 switch (rtwdev->hci.type) { in rtw89_mac_dmac_func_pre_en_be()
431 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); in rtw89_mac_disable_cpu_be()
585 u32 reg; in cmac_func_en_be() local
588 return -EINVAL; in cmac_func_en_be()
598 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx); in cmac_func_en_be()
599 rtw89_write32_set(rtwdev, reg, B_BE_CK_EN_SET); in cmac_func_en_be()
601 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx); in cmac_func_en_be()
602 rtw89_write32_set(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET); in cmac_func_en_be()
604 set_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); in cmac_func_en_be()
606 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx); in cmac_func_en_be()
607 rtw89_write32_clr(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET); in cmac_func_en_be()
609 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx); in cmac_func_en_be()
610 rtw89_write32_clr(rtwdev, reg, B_BE_CK_EN_SET); in cmac_func_en_be()
616 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); in cmac_func_en_be()
660 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); in sta_sch_init_be()
759 rtw89_err(rtwdev, "[MLO]%s: MLO init polling timeout\n", __func__); in mlo_init_be()
771 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); in dmac_init_be()
773 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); in dmac_init_be()
777 ret = rtw89_mac_preload_init(rtwdev, mac_idx, rtwdev->mac.qta_mode); in dmac_init_be()
779 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); in dmac_init_be()
785 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); in dmac_init_be()
791 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); in dmac_init_be()
797 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); in dmac_init_be()
803 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); in dmac_init_be()
809 rtw89_err(rtwdev, "[ERR]TX pkt ctrl init %d\n", ret); in dmac_init_be()
815 rtw89_err(rtwdev, "[ERR]MLO init %d\n", ret); in dmac_init_be()
825 u32 reg; in scheduler_init_be() local
832 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_CTN_CHK_CCA_NAV, mac_idx); in scheduler_init_be()
837 rtw89_write32(rtwdev, reg, val32); in scheduler_init_be()
839 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_SIFS_CHK_CCA_NAV, mac_idx); in scheduler_init_be()
842 rtw89_write32(rtwdev, reg, val32); in scheduler_init_be()
844 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_CHK_CCA_NAV, mac_idx); in scheduler_init_be()
846 rtw89_write32(rtwdev, reg, val32); in scheduler_init_be()
848 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CCA_CFG_0, mac_idx); in scheduler_init_be()
849 rtw89_write32_clr(rtwdev, reg, B_BE_NO_GNT_WL_EN); in scheduler_init_be()
852 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PREBKF_CFG_0, mac_idx); in scheduler_init_be()
853 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_MASK, in scheduler_init_be()
856 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_CFG_0, mac_idx); in scheduler_init_be()
857 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_NONAC_MASK, in scheduler_init_be()
861 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_EDCA_BCNQ_PARAM, mac_idx); in scheduler_init_be()
862 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_CW_MASK, 0x32); in scheduler_init_be()
863 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_AIFS_MASK, BCN_IFS_25US); in scheduler_init_be()
872 u32 reg; in addr_cam_init_be() local
879 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx); in addr_cam_init_be()
880 val32 = rtw89_read32(rtwdev, reg); in addr_cam_init_be()
885 rtw89_write32(rtwdev, reg, val32); in addr_cam_init_be()
887 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx); in addr_cam_init_be()
889 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); in addr_cam_init_be()
901 u32 reg; in rtw89_mac_typ_fltr_opt_be() local
914 return -EINVAL; in rtw89_mac_typ_fltr_opt_be()
919 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MGNT_FLTR, mac_idx); in rtw89_mac_typ_fltr_opt_be()
922 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTRL_FLTR, mac_idx); in rtw89_mac_typ_fltr_opt_be()
925 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DATA_FLTR, mac_idx); in rtw89_mac_typ_fltr_opt_be()
929 return -EINVAL; in rtw89_mac_typ_fltr_opt_be()
931 rtw89_write32(rtwdev, reg, val); in rtw89_mac_typ_fltr_opt_be()
938 u32 reg; in rx_fltr_init_be() local
945 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx); in rx_fltr_init_be()
949 rtw89_write32(rtwdev, reg, val); in rx_fltr_init_be()
950 u32p_replace_bits(&rtwdev->hal.rx_fltr, 15, B_BE_UID_FILTER_MASK); in rx_fltr_init_be()
952 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx); in rx_fltr_init_be()
956 rtw89_write16(rtwdev, reg, val); in rx_fltr_init_be()
969 u32 reg; in nav_ctrl_init_be() local
971 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_NAV_CTL, mac_idx); in nav_ctrl_init_be()
973 val32 = rtw89_read32(rtwdev, reg); in nav_ctrl_init_be()
978 rtw89_write32(rtwdev, reg, val32); in nav_ctrl_init_be()
985 u32 reg; in spatial_reuse_init_be() local
992 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_SR_CTRL, mac_idx); in spatial_reuse_init_be()
993 rtw89_write8_clr(rtwdev, reg, B_BE_SR_EN | B_BE_SR_CTRL_PLCP_EN); in spatial_reuse_init_be()
995 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BSSID_SRC_CTRL, mac_idx); in spatial_reuse_init_be()
996 rtw89_write8_set(rtwdev, reg, B_BE_PLCP_SRC_EN); in spatial_reuse_init_be()
1003 u32 reg; in tmac_init_be() local
1005 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_PPDU_CTRL, mac_idx); in tmac_init_be()
1006 rtw89_write32_clr(rtwdev, reg, B_BE_QOSNULL_UPD_MUEDCA_EN); in tmac_init_be()
1008 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMTX_TCR_BE_4, mac_idx); in tmac_init_be()
1009 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK, 0x12); in tmac_init_be()
1010 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK, 0xe); in tmac_init_be()
1017 const struct rtw89_chip_info *chip = rtwdev->chip; in trxptcl_init_be()
1018 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; in trxptcl_init_be()
1019 struct rtw89_hal *hal = &rtwdev->hal; in trxptcl_init_be()
1021 u32 reg; in trxptcl_init_be() local
1028 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MAC_LOOPBACK, mac_idx); in trxptcl_init_be()
1029 val32 = rtw89_read32(rtwdev, reg); in trxptcl_init_be()
1033 rtw89_write32(rtwdev, reg, val32); in trxptcl_init_be()
1035 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx); in trxptcl_init_be()
1036 val32 = rtw89_read32(rtwdev, reg); in trxptcl_init_be()
1041 rtw89_write32(rtwdev, reg, val32); in trxptcl_init_be()
1043 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY, mac_idx); in trxptcl_init_be()
1044 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA); in trxptcl_init_be()
1046 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE, mac_idx); in trxptcl_init_be()
1047 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_HE_CHK_EDCCA); in trxptcl_init_be()
1049 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC, mac_idx); in trxptcl_init_be()
1050 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA); in trxptcl_init_be()
1052 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RXTRIG_TEST_USER_2, mac_idx); in trxptcl_init_be()
1053 rtw89_write32_set(rtwdev, reg, B_BE_RXTRIG_FCSCHK_EN); in trxptcl_init_be()
1055 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_1, mac_idx); in trxptcl_init_be()
1056 val32 = rtw89_read32(rtwdev, reg); in trxptcl_init_be()
1059 rtw89_write32(rtwdev, reg, val32); in trxptcl_init_be()
1060 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); in trxptcl_init_be()
1062 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx); in trxptcl_init_be()
1063 val32 = rtw89_read32(rtwdev, reg); in trxptcl_init_be()
1065 rtw89_write32(rtwdev, reg, val32); in trxptcl_init_be()
1067 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR0, mac_idx); in trxptcl_init_be()
1068 val32 = rtw89_read32(rtwdev, reg); in trxptcl_init_be()
1071 rtw89_write32(rtwdev, reg, val32); in trxptcl_init_be()
1073 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) { in trxptcl_init_be()
1074 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx); in trxptcl_init_be()
1075 rtw89_write32_mask(rtwdev, reg, B_BE_RSC_MASK, 1); in trxptcl_init_be()
1106 u32 reg; in rmac_init_be() local
1119 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DLK_PROTECT_CTL, mac_idx); in rmac_init_be()
1120 val16 = rtw89_read16(rtwdev, reg); in rmac_init_be()
1124 rtw89_write16(rtwdev, reg, val16); in rmac_init_be()
1127 rx_min_qta = rtwdev->mac.dle_info.c0_rx_qta; in rmac_init_be()
1129 rx_min_qta = rtwdev->mac.dle_info.c1_rx_qta; in rmac_init_be()
1131 rx_max_len = rx_max_pg * rtwdev->mac.dle_info.ple_pg_size; in rmac_init_be()
1135 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx); in rmac_init_be()
1136 rtw89_write32_mask(rtwdev, reg, B_BE_RX_MPDU_MAX_LEN_MASK, rx_max_len); in rmac_init_be()
1138 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx); in rmac_init_be()
1139 rtw89_write8_clr(rtwdev, reg, B_BE_VHT_SU_SIGB_CRC_CHK); in rmac_init_be()
1141 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx); in rmac_init_be()
1142 rtw89_write16_set(rtwdev, reg, B_BE_BUSY_CHKSN); in rmac_init_be()
1144 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_PLCP_EXT_OPTION_1, mac_idx); in rmac_init_be()
1145 rtw89_write16_set(rtwdev, reg, B_BE_PLCP_SU_PSDU_LEN_SRC); in rmac_init_be()
1154 u32 reg; in resp_pktctl_init_be() local
1168 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RESP_CSI_RESERVED_PAGE, mac_idx); in resp_pktctl_init_be()
1169 rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_START_PAGE_MASK, qt_cfg.pktid); in resp_pktctl_init_be()
1170 rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_PAGE_NUM_MASK, qt_cfg.pg_num); in resp_pktctl_init_be()
1207 u32 reg; in ptcl_init_be() local
1215 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SIFS_SETTING, mac_idx); in ptcl_init_be()
1216 val32 = rtw89_read32(rtwdev, reg); in ptcl_init_be()
1222 rtw89_write32(rtwdev, reg, val32); in ptcl_init_be()
1224 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_FSM_MON, mac_idx); in ptcl_init_be()
1225 val32 = rtw89_read32(rtwdev, reg); in ptcl_init_be()
1229 rtw89_write32(rtwdev, reg, val32); in ptcl_init_be()
1232 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_COMMON_SETTING_0, mac_idx); in ptcl_init_be()
1233 val8 = rtw89_read8(rtwdev, reg); in ptcl_init_be()
1238 rtw89_write8(rtwdev, reg, val8); in ptcl_init_be()
1240 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AMPDU_AGG_LIMIT, mac_idx); in ptcl_init_be()
1241 rtw89_write32_mask(rtwdev, reg, B_BE_AMPDU_MAX_TIME_MASK, AMPDU_MAX_TIME); in ptcl_init_be()
1249 u32 reg; in cmac_dma_init_be() local
1256 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_CTRL_1, mac_idx); in cmac_dma_init_be()
1258 val32 = rtw89_read32(rtwdev, reg); in cmac_dma_init_be()
1263 rtw89_write32(rtwdev, reg, val32); in cmac_dma_init_be()
1274 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); in cmac_init_be()
1287 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, in cmac_init_be()
1294 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, in cmac_init_be()
1301 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, in cmac_init_be()
1308 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", in cmac_init_be()
1315 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); in cmac_init_be()
1321 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); in cmac_init_be()
1327 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); in cmac_init_be()
1333 rtw89_err(rtwdev, "[ERR]CMAC%d resp pktctl init %d\n", mac_idx, ret); in cmac_init_be()
1339 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); in cmac_init_be()
1345 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); in cmac_init_be()
1351 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); in cmac_init_be()
1360 u32 reg; in tx_idle_poll_band_be() local
1368 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_TX_CTN_SEL, mac_idx); in tx_idle_poll_band_be()
1371 30, 66000, false, rtwdev, reg); in tx_idle_poll_band_be()
1378 u32 val, reg; in dle_buf_req_be() local
1381 reg = wd ? R_BE_WD_BUF_REQ : R_BE_PL_BUF_REQ; in dle_buf_req_be()
1384 rtw89_write32(rtwdev, reg, val); in dle_buf_req_be()
1386 reg = wd ? R_BE_WD_BUF_STATUS : R_BE_PL_BUF_STATUS; in dle_buf_req_be()
1389 1, 2000, false, rtwdev, reg); in dle_buf_req_be()
1395 return -ENOENT; in dle_buf_req_be()
1404 u32 val, cmd_type, reg; in set_cpuio_be() local
1407 cmd_type = ctrl_para->cmd_type; in set_cpuio_be()
1409 reg = wd ? R_BE_WD_CPUQ_OP_3 : R_BE_PL_CPUQ_OP_3; in set_cpuio_be()
1410 val_op3 = u32_replace_bits(0, ctrl_para->start_pktid, in set_cpuio_be()
1412 val_op3 = u32_replace_bits(val_op3, ctrl_para->end_pktid, in set_cpuio_be()
1414 rtw89_write32(rtwdev, reg, val_op3); in set_cpuio_be()
1416 reg = wd ? R_BE_WD_CPUQ_OP_1 : R_BE_PL_CPUQ_OP_1; in set_cpuio_be()
1417 val_op1 = u32_replace_bits(0, ctrl_para->src_pid, in set_cpuio_be()
1419 val_op1 = u32_replace_bits(val_op1, ctrl_para->src_qid, in set_cpuio_be()
1421 val_op1 = u32_replace_bits(val_op1, ctrl_para->macid, in set_cpuio_be()
1423 rtw89_write32(rtwdev, reg, val_op1); in set_cpuio_be()
1425 reg = wd ? R_BE_WD_CPUQ_OP_2 : R_BE_PL_CPUQ_OP_2; in set_cpuio_be()
1426 val_op2 = u32_replace_bits(0, ctrl_para->dst_pid, in set_cpuio_be()
1428 val_op2 = u32_replace_bits(val_op2, ctrl_para->dst_qid, in set_cpuio_be()
1430 val_op2 = u32_replace_bits(val_op2, ctrl_para->macid, in set_cpuio_be()
1432 rtw89_write32(rtwdev, reg, val_op2); in set_cpuio_be()
1434 reg = wd ? R_BE_WD_CPUQ_OP_0 : R_BE_PL_CPUQ_OP_0; in set_cpuio_be()
1437 val_op0 = u32_replace_bits(val_op0, ctrl_para->pkt_num, in set_cpuio_be()
1440 rtw89_write32(rtwdev, reg, val_op0); in set_cpuio_be()
1442 reg = wd ? R_BE_WD_CPUQ_OP_STATUS : R_BE_PL_CPUQ_OP_STATUS; in set_cpuio_be()
1445 1, 2000, false, rtwdev, reg); in set_cpuio_be()
1455 ctrl_para->pktid = u32_get_bits(val, B_BE_WD_CPUQ_OP_PKTID_MASK); in set_cpuio_be()
1485 return -EINVAL; in dle_upd_qta_aval_page_be()
1530 u32 reg; in preload_init_be() local
1536 reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG0 : in preload_init_be()
1538 val32 = rtw89_read32(rtwdev, reg); in preload_init_be()
1541 rtw89_write32(rtwdev, reg, val32); in preload_init_be()
1544 reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG1 : in preload_init_be()
1546 val32 = rtw89_read32(rtwdev, reg); in preload_init_be()
1549 rtw89_write32(rtwdev, reg, val32); in preload_init_be()
1569 const struct rtw89_chip_info *chip = rtwdev->chip; in enable_imr_be()
1571 const struct rtw89_reg_imr *reg; in enable_imr_be() local
1577 table = chip->imr_dmac_table; in enable_imr_be()
1579 table = chip->imr_cmac_table; in enable_imr_be()
1581 return -EINVAL; in enable_imr_be()
1583 for (i = 0; i < table->n_regs; i++) { in enable_imr_be()
1584 reg = &table->regs[i]; in enable_imr_be()
1585 addr = rtw89_mac_reg_by_idx(rtwdev, reg->addr, mac_idx); in enable_imr_be()
1588 val &= ~reg->clr; in enable_imr_be()
1589 val |= reg->set; in enable_imr_be()
1607 if (rtwdev->dbcc_en) in err_imr_ctrl_be()
1621 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); in band1_enable_be()
1627 ret = preload_init_be(rtwdev, RTW89_MAC_1, rtwdev->mac.qta_mode); in band1_enable_be()
1629 rtw89_err(rtwdev, "[ERR]preload init B1 %d\n", ret); in band1_enable_be()
1641 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", RTW89_MAC_1, ret); in band1_enable_be()
1676 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, false); in band1_disable_be()
1696 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) { in dbcc_enable_be()
1705 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) { in dbcc_enable_be()
1755 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in trx_init_be()
1756 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; in trx_init_be()
1761 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); in trx_init_be()
1767 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); in trx_init_be()
1774 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); in trx_init_be()
1811 if (gnt_cfg->band[0].gnt_bt) in rtw89_mac_cfg_gnt_v2()
1815 if (gnt_cfg->band[0].gnt_bt_sw_en) in rtw89_mac_cfg_gnt_v2()
1819 if (gnt_cfg->band[0].gnt_wl) in rtw89_mac_cfg_gnt_v2()
1823 if (gnt_cfg->band[0].gnt_wl_sw_en) in rtw89_mac_cfg_gnt_v2()
1827 if (gnt_cfg->band[1].gnt_bt) in rtw89_mac_cfg_gnt_v2()
1831 if (gnt_cfg->band[1].gnt_bt_sw_en) in rtw89_mac_cfg_gnt_v2()
1835 if (gnt_cfg->band[1].gnt_wl) in rtw89_mac_cfg_gnt_v2()
1839 if (gnt_cfg->band[1].gnt_wl_sw_en) in rtw89_mac_cfg_gnt_v2()
1843 if (gnt_cfg->bt[0].wlan_act_en) in rtw89_mac_cfg_gnt_v2()
1845 if (gnt_cfg->bt[0].wlan_act) in rtw89_mac_cfg_gnt_v2()
1847 if (gnt_cfg->bt[1].wlan_act_en) in rtw89_mac_cfg_gnt_v2()
1849 if (gnt_cfg->bt[1].wlan_act) in rtw89_mac_cfg_gnt_v2()
1860 struct rtw89_btc *btc = &rtwdev->btc; in rtw89_mac_cfg_ctrl_path_v2()
1861 struct rtw89_btc_dm *dm = &btc->dm; in rtw89_mac_cfg_ctrl_path_v2()
1862 struct rtw89_mac_ax_gnt *g = dm->gnt.band; in rtw89_mac_cfg_ctrl_path_v2()
1863 struct rtw89_mac_ax_wl_act *gbt = dm->gnt.bt; in rtw89_mac_cfg_ctrl_path_v2()
1878 return rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt); in rtw89_mac_cfg_ctrl_path_v2()
1885 u32 reg; in rtw89_mac_cfg_plt_be() local
1889 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); in rtw89_mac_cfg_plt_be()
1893 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, plt->band); in rtw89_mac_cfg_plt_be()
1894 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_TX_PLT_GNT_LTE_RX : 0) | in rtw89_mac_cfg_plt_be()
1895 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_TX_PLT_GNT_BT_TX : 0) | in rtw89_mac_cfg_plt_be()
1896 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_TX_PLT_GNT_BT_RX : 0) | in rtw89_mac_cfg_plt_be()
1897 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_TX_PLT_GNT_WL : 0) | in rtw89_mac_cfg_plt_be()
1898 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_RX_PLT_GNT_LTE_RX : 0) | in rtw89_mac_cfg_plt_be()
1899 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_RX_PLT_GNT_BT_TX : 0) | in rtw89_mac_cfg_plt_be()
1900 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_RX_PLT_GNT_BT_RX : 0) | in rtw89_mac_cfg_plt_be()
1901 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_RX_PLT_GNT_WL : 0) | in rtw89_mac_cfg_plt_be()
1903 rtw89_write16(rtwdev, reg, val); in rtw89_mac_cfg_plt_be()
1910 u32 reg; in rtw89_mac_get_plt_cnt_be() local
1913 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, band); in rtw89_mac_get_plt_cnt_be()
1914 cnt = rtw89_read32_mask(rtwdev, reg, B_BE_BT_PLT_PKT_CNT_MASK); in rtw89_mac_get_plt_cnt_be()
1915 rtw89_write16_set(rtwdev, reg, B_BE_BT_PLT_RST); in rtw89_mac_get_plt_cnt_be()
1923 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_DRV_TXEN, mac_idx); in rtw89_set_hw_sch_tx_en_v2() local
1931 val = rtw89_read32(rtwdev, reg); in rtw89_set_hw_sch_tx_en_v2()
1933 rtw89_write32(rtwdev, reg, val); in rtw89_set_hw_sch_tx_en_v2()
1994 u32 reg, val; in rtw89_mac_cfg_phy_rpt_be() local
1996 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx); in rtw89_mac_cfg_phy_rpt_be()
1998 rtw89_write32_mask(rtwdev, reg, B_BE_PHY_RPT_SZ_MASK, val); in rtw89_mac_cfg_phy_rpt_be()
1999 rtw89_write32_mask(rtwdev, reg, B_BE_HDR_CNV_SZ_MASK, MAC_AX_HDR_CNV_SIZE_0); in rtw89_mac_cfg_phy_rpt_be()
2001 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DRV_INFO_OPTION, mac_idx); in rtw89_mac_cfg_phy_rpt_be()
2002 rtw89_write32_mask(rtwdev, reg, B_BE_DRV_INFO_PHYRPT_EN, enable); in rtw89_mac_cfg_phy_rpt_be()
2009 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PPDU_STAT, mac_idx); in rtw89_mac_cfg_ppdu_status_be() local
2017 rtw89_write32_clr(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN); in rtw89_mac_cfg_ppdu_status_be()
2022 rtw89_write32(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN | B_BE_PPDU_MAC_INFO | in rtw89_mac_cfg_ppdu_status_be()
2033 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; in rtw89_mac_get_txpwr_cr_be()
2039 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) in rtw89_mac_get_txpwr_cr_be()
2068 u32 reg; in rtw89_mac_init_bfee_be() local
2078 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); in rtw89_mac_init_bfee_be()
2079 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL | in rtw89_mac_init_bfee_be()
2083 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_CSI_RSC_MASK, CSI_RX_BW_CFG); in rtw89_mac_init_bfee_be()
2085 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CSIRPT_OPTION, mac_idx); in rtw89_mac_init_bfee_be()
2086 rtw89_write32_set(rtwdev, reg, B_BE_CSIPRT_VHTSU_AID_EN | in rtw89_mac_init_bfee_be()
2090 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx); in rtw89_mac_init_bfee_be()
2091 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP_BE); in rtw89_mac_init_bfee_be()
2093 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); in rtw89_mac_init_bfee_be()
2094 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK, in rtw89_mac_init_bfee_be()
2097 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RATE, mac_idx); in rtw89_mac_init_bfee_be()
2103 rtw89_write32(rtwdev, reg, val); in rtw89_mac_init_bfee_be()
2114 u8 mac_idx = rtwvif_link->mac_idx; in rtw89_mac_set_csi_para_reg_be()
2115 u8 port_sel = rtwvif_link->port; in rtw89_mac_set_csi_para_reg_be()
2118 u32 reg; in rtw89_mac_set_csi_para_reg_be() local
2129 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; in rtw89_mac_set_csi_para_reg_be()
2140 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || in rtw89_mac_set_csi_para_reg_be()
2141 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { in rtw89_mac_set_csi_para_reg_be()
2142 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); in rtw89_mac_set_csi_para_reg_be()
2143 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); in rtw89_mac_set_csi_para_reg_be()
2144 t = u32_get_bits(link_sta->vht_cap.cap, in rtw89_mac_set_csi_para_reg_be()
2154 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); in rtw89_mac_set_csi_para_reg_be()
2155 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL); in rtw89_mac_set_csi_para_reg_be()
2166 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, in rtw89_mac_set_csi_para_reg_be()
2169 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1, in rtw89_mac_set_csi_para_reg_be()
2172 rtw89_write16(rtwdev, reg, val); in rtw89_mac_set_csi_para_reg_be()
2183 u8 mac_idx = rtwvif_link->mac_idx; in rtw89_mac_csi_rrsc_be()
2185 u32 reg; in rtw89_mac_csi_rrsc_be() local
2195 if (link_sta->he_cap.has_he) { in rtw89_mac_csi_rrsc_be()
2200 if (link_sta->vht_cap.vht_supported) { in rtw89_mac_csi_rrsc_be()
2205 if (link_sta->ht_cap.ht_supported) { in rtw89_mac_csi_rrsc_be()
2213 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); in rtw89_mac_csi_rrsc_be()
2214 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL); in rtw89_mac_csi_rrsc_be()
2215 rtw89_write32_clr(rtwdev, reg, B_BE_BFMEE_CSI_FORCE_RETE_EN); in rtw89_mac_csi_rrsc_be()
2217 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx); in rtw89_mac_csi_rrsc_be()
2218 rtw89_write32(rtwdev, reg, rrsc); in rtw89_mac_csi_rrsc_be()
2240 rtw89_mac_init_bfee_be(rtwdev, rtwvif_link->mac_idx); in rtw89_mac_bf_assoc_be()
2474 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); in rtw89_mac_dump_err_status_be()
2512 rtwdev->hci.ops->dump_err_status(rtwdev); in rtw89_mac_dump_err_status_be()
2517 rtw89_info(rtwdev, "<---\n"); in rtw89_mac_dump_err_status_be()
2528 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; in mac_is_txq_empty_be()
2548 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; in mac_is_txq_empty_be()