Lines Matching +full:dma +full:- +full:byte +full:- +full:en
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
68 test_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags)) in rtw89_mac_check_mac_en_be()
71 test_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags)) in rtw89_mac_check_mac_en_be()
74 test_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags)) in rtw89_mac_check_mac_en_be()
77 return -EFAULT; in rtw89_mac_check_mac_en_be()
82 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; in is_qta_poh()
87 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_get_mix_info_be()
88 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; in hfc_get_mix_info_be()
89 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; in hfc_get_mix_info_be()
90 struct rtw89_hfc_pub_info *info = ¶m->pub_info; in hfc_get_mix_info_be()
94 info->g0_used = u32_get_bits(val, B_BE_G0_USE_PG_MASK); in hfc_get_mix_info_be()
95 info->g1_used = u32_get_bits(val, B_BE_G1_USE_PG_MASK); in hfc_get_mix_info_be()
98 info->g0_aval = u32_get_bits(val, B_BE_G0_AVAL_PG_MASK); in hfc_get_mix_info_be()
99 info->g1_aval = u32_get_bits(val, B_BE_G1_AVAL_PG_MASK); in hfc_get_mix_info_be()
100 info->pub_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO2), in hfc_get_mix_info_be()
102 info->wp_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_WP_PAGE_INFO1), in hfc_get_mix_info_be()
106 param->en = !!(val & B_BE_HCI_FC_EN); in hfc_get_mix_info_be()
107 param->h2c_en = !!(val & B_BE_HCI_FC_CH12_EN); in hfc_get_mix_info_be()
108 param->mode = u32_get_bits(val, B_BE_HCI_FC_MODE_MASK); in hfc_get_mix_info_be()
109 prec_cfg->ch011_full_cond = u32_get_bits(val, B_BE_HCI_FC_WD_FULL_COND_MASK); in hfc_get_mix_info_be()
110 prec_cfg->h2c_full_cond = u32_get_bits(val, B_BE_HCI_FC_CH12_FULL_COND_MASK); in hfc_get_mix_info_be()
111 prec_cfg->wp_ch07_full_cond = in hfc_get_mix_info_be()
113 prec_cfg->wp_ch811_full_cond = in hfc_get_mix_info_be()
117 prec_cfg->ch011_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH011_V1_MASK); in hfc_get_mix_info_be()
118 prec_cfg->h2c_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH12_V1_MASK); in hfc_get_mix_info_be()
121 pub_cfg->pub_max = u32_get_bits(val, B_BE_PUBPG_ALL_MASK); in hfc_get_mix_info_be()
124 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK); in hfc_get_mix_info_be()
125 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK); in hfc_get_mix_info_be()
128 pub_cfg->wp_thrd = u32_get_bits(val, B_BE_WP_THRD_MASK); in hfc_get_mix_info_be()
131 pub_cfg->grp0 = u32_get_bits(val, B_BE_PUBPG_G0_MASK); in hfc_get_mix_info_be()
132 pub_cfg->grp1 = u32_get_bits(val, B_BE_PUBPG_G1_MASK); in hfc_get_mix_info_be()
137 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_h2c_cfg_be()
138 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; in hfc_h2c_cfg_be()
141 val = u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK); in hfc_h2c_cfg_be()
147 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_mix_cfg_be()
148 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; in hfc_mix_cfg_be()
149 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; in hfc_mix_cfg_be()
152 val = u32_encode_bits(prec_cfg->ch011_prec, B_BE_PREC_PAGE_CH011_V1_MASK) | in hfc_mix_cfg_be()
153 u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK); in hfc_mix_cfg_be()
156 val = u32_encode_bits(pub_cfg->pub_max, B_BE_PUBPG_ALL_MASK); in hfc_mix_cfg_be()
159 val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) | in hfc_mix_cfg_be()
160 u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK); in hfc_mix_cfg_be()
164 param->mode, B_BE_HCI_FC_MODE_MASK); in hfc_mix_cfg_be()
165 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, in hfc_mix_cfg_be()
167 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, in hfc_mix_cfg_be()
169 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, in hfc_mix_cfg_be()
171 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, in hfc_mix_cfg_be()
176 static void hfc_func_en_be(struct rtw89_dev *rtwdev, bool en, bool h2c_en) in hfc_func_en_be() argument
178 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; in hfc_func_en_be()
182 param->en = en; in hfc_func_en_be()
183 param->h2c_en = h2c_en; in hfc_func_en_be()
184 val = en ? (val | B_BE_HCI_FC_EN) : (val & ~B_BE_HCI_FC_EN); in hfc_func_en_be()
216 wde_size_cfg = cfg->wde_size; in dle_mix_cfg_be()
217 ple_size_cfg = cfg->ple_size; in dle_mix_cfg_be()
221 switch (wde_size_cfg->pge_size) { in dle_mix_cfg_be()
232 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); in dle_mix_cfg_be()
233 return -EINVAL; in dle_mix_cfg_be()
236 bound = wde_size_cfg->srt_ofst / DLE_BOUND_UNIT; in dle_mix_cfg_be()
238 val = u32_replace_bits(val, wde_size_cfg->lnk_pge_num, in dle_mix_cfg_be()
244 switch (ple_size_cfg->pge_size) { in dle_mix_cfg_be()
247 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); in dle_mix_cfg_be()
248 return -EINVAL; in dle_mix_cfg_be()
259 bound = ple_size_cfg->srt_ofst / DLE_BOUND_UNIT; in dle_mix_cfg_be()
261 val = u32_replace_bits(val, ple_size_cfg->lnk_pge_num, in dle_mix_cfg_be()
295 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
303 ext_wde_min_qt_wcpu : min_cfg->wcpu; in wde_quota_cfg_be()
304 u16 max_qt_wcpu = max(max_cfg->wcpu, min_qt_wcpu); in wde_quota_cfg_be()
347 switch (rtwdev->hci.type) { in rtw89_mac_dmac_func_pre_en_be()
431 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); in rtw89_mac_disable_cpu_be()
583 static int cmac_func_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) in cmac_func_en_be() argument
588 return -EINVAL; in cmac_func_en_be()
593 if (en) { in cmac_func_en_be()
604 set_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); in cmac_func_en_be()
616 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); in cmac_func_en_be()
771 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); in dmac_init_be()
777 ret = rtw89_mac_preload_init(rtwdev, mac_idx, rtwdev->mac.qta_mode); in dmac_init_be()
914 return -EINVAL; in rtw89_mac_typ_fltr_opt_be()
929 return -EINVAL; in rtw89_mac_typ_fltr_opt_be()
950 u32p_replace_bits(&rtwdev->hal.rx_fltr, 15, B_BE_UID_FILTER_MASK); in rx_fltr_init_be()
1017 const struct rtw89_chip_info *chip = rtwdev->chip; in trxptcl_init_be()
1018 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; in trxptcl_init_be()
1019 struct rtw89_hal *hal = &rtwdev->hal; in trxptcl_init_be()
1060 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); in trxptcl_init_be()
1073 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) { in trxptcl_init_be()
1127 rx_min_qta = rtwdev->mac.dle_info.c0_rx_qta; in rmac_init_be()
1129 rx_min_qta = rtwdev->mac.dle_info.c1_rx_qta; in rmac_init_be()
1131 rx_max_len = rx_max_pg * rtwdev->mac.dle_info.ple_pg_size; in rmac_init_be()
1351 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); in cmac_init_be()
1395 return -ENOENT; in dle_buf_req_be()
1407 cmd_type = ctrl_para->cmd_type; in set_cpuio_be()
1410 val_op3 = u32_replace_bits(0, ctrl_para->start_pktid, in set_cpuio_be()
1412 val_op3 = u32_replace_bits(val_op3, ctrl_para->end_pktid, in set_cpuio_be()
1417 val_op1 = u32_replace_bits(0, ctrl_para->src_pid, in set_cpuio_be()
1419 val_op1 = u32_replace_bits(val_op1, ctrl_para->src_qid, in set_cpuio_be()
1421 val_op1 = u32_replace_bits(val_op1, ctrl_para->macid, in set_cpuio_be()
1426 val_op2 = u32_replace_bits(0, ctrl_para->dst_pid, in set_cpuio_be()
1428 val_op2 = u32_replace_bits(val_op2, ctrl_para->dst_qid, in set_cpuio_be()
1430 val_op2 = u32_replace_bits(val_op2, ctrl_para->macid, in set_cpuio_be()
1437 val_op0 = u32_replace_bits(val_op0, ctrl_para->pkt_num, in set_cpuio_be()
1455 ctrl_para->pktid = u32_get_bits(val, B_BE_WD_CPUQ_OP_PKTID_MASK); in set_cpuio_be()
1485 return -EINVAL; in dle_upd_qta_aval_page_be()
1569 const struct rtw89_chip_info *chip = rtwdev->chip; in enable_imr_be()
1577 table = chip->imr_dmac_table; in enable_imr_be()
1579 table = chip->imr_cmac_table; in enable_imr_be()
1581 return -EINVAL; in enable_imr_be()
1583 for (i = 0; i < table->n_regs; i++) { in enable_imr_be()
1584 reg = &table->regs[i]; in enable_imr_be()
1585 addr = rtw89_mac_reg_by_idx(rtwdev, reg->addr, mac_idx); in enable_imr_be()
1588 val &= ~reg->clr; in enable_imr_be()
1589 val |= reg->set; in enable_imr_be()
1596 static void err_imr_ctrl_be(struct rtw89_dev *rtwdev, bool en) in err_imr_ctrl_be() argument
1598 u32 v32_dmac = en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS; in err_imr_ctrl_be()
1599 u32 v32_cmac0 = en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS; in err_imr_ctrl_be()
1600 u32 v32_cmac1 = en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS; in err_imr_ctrl_be()
1607 if (rtwdev->dbcc_en) in err_imr_ctrl_be()
1621 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); in band1_enable_be()
1627 ret = preload_init_be(rtwdev, RTW89_MAC_1, rtwdev->mac.qta_mode); in band1_enable_be()
1635 rtw89_err(rtwdev, "[ERR]CMAC%d func en %d\n", RTW89_MAC_1, ret); in band1_enable_be()
1676 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, false); in band1_disable_be()
1696 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) { in dbcc_enable_be()
1705 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) { in dbcc_enable_be()
1755 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in trx_init_be()
1756 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; in trx_init_be()
1811 if (gnt_cfg->band[0].gnt_bt) in rtw89_mac_cfg_gnt_v2()
1815 if (gnt_cfg->band[0].gnt_bt_sw_en) in rtw89_mac_cfg_gnt_v2()
1819 if (gnt_cfg->band[0].gnt_wl) in rtw89_mac_cfg_gnt_v2()
1823 if (gnt_cfg->band[0].gnt_wl_sw_en) in rtw89_mac_cfg_gnt_v2()
1827 if (gnt_cfg->band[1].gnt_bt) in rtw89_mac_cfg_gnt_v2()
1831 if (gnt_cfg->band[1].gnt_bt_sw_en) in rtw89_mac_cfg_gnt_v2()
1835 if (gnt_cfg->band[1].gnt_wl) in rtw89_mac_cfg_gnt_v2()
1839 if (gnt_cfg->band[1].gnt_wl_sw_en) in rtw89_mac_cfg_gnt_v2()
1843 if (gnt_cfg->bt[0].wlan_act_en) in rtw89_mac_cfg_gnt_v2()
1845 if (gnt_cfg->bt[0].wlan_act) in rtw89_mac_cfg_gnt_v2()
1847 if (gnt_cfg->bt[1].wlan_act_en) in rtw89_mac_cfg_gnt_v2()
1849 if (gnt_cfg->bt[1].wlan_act) in rtw89_mac_cfg_gnt_v2()
1860 struct rtw89_btc *btc = &rtwdev->btc; in rtw89_mac_cfg_ctrl_path_v2()
1861 struct rtw89_btc_dm *dm = &btc->dm; in rtw89_mac_cfg_ctrl_path_v2()
1862 struct rtw89_mac_ax_gnt *g = dm->gnt.band; in rtw89_mac_cfg_ctrl_path_v2()
1863 struct rtw89_mac_ax_wl_act *gbt = dm->gnt.bt; in rtw89_mac_cfg_ctrl_path_v2()
1878 return rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt); in rtw89_mac_cfg_ctrl_path_v2()
1889 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); in rtw89_mac_cfg_plt_be()
1893 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, plt->band); in rtw89_mac_cfg_plt_be()
1894 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_TX_PLT_GNT_LTE_RX : 0) | in rtw89_mac_cfg_plt_be()
1895 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_TX_PLT_GNT_BT_TX : 0) | in rtw89_mac_cfg_plt_be()
1896 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_TX_PLT_GNT_BT_RX : 0) | in rtw89_mac_cfg_plt_be()
1897 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_TX_PLT_GNT_WL : 0) | in rtw89_mac_cfg_plt_be()
1898 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_RX_PLT_GNT_LTE_RX : 0) | in rtw89_mac_cfg_plt_be()
1899 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_RX_PLT_GNT_BT_TX : 0) | in rtw89_mac_cfg_plt_be()
1900 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_RX_PLT_GNT_BT_RX : 0) | in rtw89_mac_cfg_plt_be()
1901 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_RX_PLT_GNT_WL : 0) | in rtw89_mac_cfg_plt_be()
2033 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; in rtw89_mac_get_txpwr_cr_be()
2039 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) in rtw89_mac_get_txpwr_cr_be()
2114 u8 mac_idx = rtwvif_link->mac_idx; in rtw89_mac_set_csi_para_reg_be()
2115 u8 port_sel = rtwvif_link->port; in rtw89_mac_set_csi_para_reg_be()
2129 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; in rtw89_mac_set_csi_para_reg_be()
2140 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || in rtw89_mac_set_csi_para_reg_be()
2141 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { in rtw89_mac_set_csi_para_reg_be()
2142 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); in rtw89_mac_set_csi_para_reg_be()
2143 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); in rtw89_mac_set_csi_para_reg_be()
2144 t = u32_get_bits(link_sta->vht_cap.cap, in rtw89_mac_set_csi_para_reg_be()
2183 u8 mac_idx = rtwvif_link->mac_idx; in rtw89_mac_csi_rrsc_be()
2195 if (link_sta->he_cap.has_he) { in rtw89_mac_csi_rrsc_be()
2200 if (link_sta->vht_cap.vht_supported) { in rtw89_mac_csi_rrsc_be()
2205 if (link_sta->ht_cap.ht_supported) { in rtw89_mac_csi_rrsc_be()
2240 rtw89_mac_init_bfee_be(rtwdev, rtwvif_link->mac_idx); in rtw89_mac_bf_assoc_be()
2474 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); in rtw89_mac_dump_err_status_be()
2512 rtwdev->hci.ops->dump_err_status(rtwdev); in rtw89_mac_dump_err_status_be()
2517 rtw89_info(rtwdev, "<---\n"); in rtw89_mac_dump_err_status_be()
2528 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; in mac_is_txq_empty_be()
2548 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; in mac_is_txq_empty_be()