Lines Matching refs:rtwdev
40 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
46 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
47 rtw89_write32(rtwdev, mac->indir_access_addr, val);
50 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset,
53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
56 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
57 return rtw89_read32(rtwdev, mac->indir_access_addr);
60 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx,
66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN);
69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN);
72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND);
84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val)
90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val);
95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset);
100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val)
106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset);
111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA);
116 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl)
138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type);
142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data);
145 1, 1000, false, rtwdev, ctrl_reg);
147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n",
152 ctrl->out_data = rtw89_read32(rtwdev, data_reg);
156 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev,
165 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl);
167 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret);
176 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev,
185 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl);
187 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret);
195 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev)
197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ",
198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n",
200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ",
202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n",
204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ",
206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n",
208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
211 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev)
222 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty);
235 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl);
237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
239 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i,
246 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a);
248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n",
253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG);
254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n",
256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n",
258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT);
259 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n",
261 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n",
262 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG));
263 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n",
264 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0));
265 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n",
266 rtw89_read32(rtwdev, R_AX_CCA_CONTROL));
268 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) {
271 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a);
273 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
275 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n",
278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG);
279 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n",
281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n",
283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1);
284 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n",
286 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n",
287 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1));
288 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n",
289 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1));
290 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n",
291 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1));
294 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n",
295 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0));
296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n",
297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1));
299 dump_err_status_dispatcher_ax(rtwdev);
302 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
308 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO);
313 rtw89_info(rtwdev, "quota lost!\n");
314 mac->dump_qta_lost(rtwdev);
321 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev)
323 const struct rtw89_chip_info *chip = rtwdev->chip;
327 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
329 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n");
333 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
334 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);
335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n",
336 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));
339 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",
340 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));
341 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",
342 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));
344 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",
345 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));
346 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",
347 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));
348 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",
349 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));
350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n",
351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));
356 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n",
357 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n",
359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
361 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
362 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));
364 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
365 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));
370 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n",
371 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));
372 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n",
373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));
374 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
375 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
376 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
377 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
378 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
379 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
380 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
381 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
382 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n",
383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));
384 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
385 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
386 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
387 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
399 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));
402 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n",
403 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG));
404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n",
405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR));
406 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n",
407 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL));
408 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n",
409 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC));
410 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n",
411 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS));
412 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n",
413 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA));
414 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n",
415 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2));
417 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
418 rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
419 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
420 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
421 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
422 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
423 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
424 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
425 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
426 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
427 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n",
428 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
429 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
430 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
431 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
432 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
433 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",
434 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
435 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",
436 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
441 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",
442 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
445 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",
446 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
453 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n",
454 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG));
455 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n",
456 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG));
458 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",
459 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
466 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
467 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
468 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
469 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
470 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
471 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
472 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
473 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
478 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
479 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
487 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
488 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
495 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
496 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
497 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
498 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
499 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
500 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
501 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
502 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
503 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
504 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
509 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
510 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
516 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n",
517 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3));
518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n",
519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS));
520 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n",
521 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3));
522 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n",
523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS));
525 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
526 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
527 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
528 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
530 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n",
531 rtw89_read32(rtwdev, R_AX_RX_CTRL0));
532 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n",
533 rtw89_read32(rtwdev, R_AX_RX_CTRL1));
534 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n",
535 rtw89_read32(rtwdev, R_AX_RX_CTRL2));
537 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
538 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
548 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n",
549 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n",
551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
556 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n",
557 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR));
558 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n",
559 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1));
560 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n",
561 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR));
562 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n",
563 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2));
564 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n",
565 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR));
566 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n",
567 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0));
569 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
570 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
573 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
574 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
577 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",
578 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
586 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
587 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));
588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));
590 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
591 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
594 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
595 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
599 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
600 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
601 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
602 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
605 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
606 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
611 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n",
612 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR));
613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n",
614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR));
620 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n",
621 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK));
622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n",
623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT));
625 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
626 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));
627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT));
633 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n",
634 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK,
636 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n",
637 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT,
642 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n",
643 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR));
644 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n",
645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR));
649 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n",
650 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR));
651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n",
652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR));
656 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev,
659 const struct rtw89_chip_info *chip = rtwdev->chip;
664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
667 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n");
669 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n");
676 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);
677 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,
678 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));
679 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,
680 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));
681 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band,
682 rtw89_read32(rtwdev, R_AX_CK_EN + offset));
685 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
686 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));
687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));
692 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band,
693 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));
694 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band,
695 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));
700 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,
701 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));
702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band,
703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));
705 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band,
706 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));
712 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
713 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));
714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
717 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
718 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
723 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band,
724 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));
725 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band,
726 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));
731 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
732 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset));
733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));
736 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band,
737 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset));
739 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
740 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));
743 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,
744 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));
747 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev,
757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
758 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
759 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
762 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n",
763 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4));
764 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n",
765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5));
767 rtw89_mac_dump_dmac_err_status(rtwdev);
768 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0);
769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1);
771 rtwdev->hci.ops->dump_err_status(rtwdev);
774 rtw89_mac_dump_l0_to_l1(rtwdev, err);
776 rtw89_info(rtwdev, "<---\n");
779 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err)
781 struct rtw89_ser *ser = &rtwdev->ser;
785 if (rtwdev->chip->chip_id == RTL8852C) {
786 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
791 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
792 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR);
793 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR);
812 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
819 false, rtwdev, R_AX_HALT_C2H_CTRL);
821 rtw89_warn(rtwdev, "Polling FW err status fail\n");
825 err = rtw89_read32(rtwdev, R_AX_HALT_C2H);
826 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
836 if (rtw89_mac_suppress_log(rtwdev, err))
839 rtw89_fw_st_dbg_dump(rtwdev);
840 mac->dump_err_status(rtwdev, err);
846 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)
848 struct rtw89_ser *ser = &rtwdev->ser;
853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err);
858 100000, false, rtwdev, R_AX_HALT_H2C_CTRL);
860 rtw89_err(rtwdev, "FW doesn't receive previous msg\n");
864 rtw89_write32(rtwdev, R_AX_HALT_H2C, err);
870 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
876 static int hfc_reset_param(struct rtw89_dev *rtwdev)
878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
882 switch (rtwdev->hci.type) {
884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode];
907 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch)
909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
926 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev)
928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
933 if (rtwdev->chip->chip_id == RTL8852A)
942 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev)
944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
953 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch)
955 const struct rtw89_chip_info *chip = rtwdev->chip;
957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
962 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
966 ret = hfc_ch_cfg_chk(rtwdev, ch);
976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);
981 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch)
983 const struct rtw89_chip_info *chip = rtwdev->chip;
985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
991 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);
1008 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev)
1010 const struct rtw89_chip_info *chip = rtwdev->chip;
1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg;
1016 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1020 ret = hfc_pub_cfg_chk(rtwdev);
1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);
1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);
1034 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev)
1036 const struct rtw89_chip_info *chip = rtwdev->chip;
1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1044 val = rtw89_read32(rtwdev, regs->pub_page_info1);
1047 val = rtw89_read32(rtwdev, regs->pub_page_info3);
1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2),
1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1),
1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl);
1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);
1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);
1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);
1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);
1089 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev)
1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1095 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1099 mac->hfc_get_mix_info(rtwdev);
1101 ret = hfc_pub_info_chk(rtwdev);
1108 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev)
1110 const struct rtw89_chip_info *chip = rtwdev->chip;
1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl,
1124 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev)
1126 const struct rtw89_chip_info *chip = rtwdev->chip;
1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);
1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);
1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),
1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1159 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
1161 const struct rtw89_chip_info *chip = rtwdev->chip;
1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1175 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en)
1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1178 const struct rtw89_chip_info *chip = rtwdev->chip;
1184 ret = hfc_reset_param(rtwdev);
1188 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1192 mac->hfc_func_en(rtwdev, false, false);
1195 mac->hfc_h2c_cfg(rtwdev);
1196 mac->hfc_func_en(rtwdev, en, h2c_en);
1203 ret = hfc_ch_ctrl(rtwdev, ch);
1208 ret = hfc_pub_ctrl(rtwdev);
1212 mac->hfc_mix_cfg(rtwdev);
1214 mac->hfc_func_en(rtwdev, en, h2c_en);
1220 ret = hfc_upd_ch_info(rtwdev, ch);
1224 ret = hfc_upd_mix_info(rtwdev);
1230 static int pwr_cmd_poll(struct rtw89_dev *rtwdev,
1239 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr);
1244 rtw89_warn(rtwdev, "[ERR] Polling timeout\n");
1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr);
1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);
1251 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk,
1270 val = rtw89_read8(rtwdev, addr);
1274 rtw89_write8(rtwdev, addr, val);
1277 if (pwr_cmd_poll(rtwdev, cur_cfg))
1294 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev,
1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv),
1310 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev)
1314 switch (rtwdev->ps_mode) {
1331 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev,
1337 spin_lock_bh(&rtwdev->rpwm_lock);
1339 request = rtw89_read16(rtwdev, R_AX_RPWM);
1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) &
1349 rtwdev->mac.rpwm_seq_num);
1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request);
1356 spin_unlock_bh(&rtwdev->rpwm_lock);
1359 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev,
1374 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K))
1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num;
1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr,
1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) &
1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM);
1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num)
1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE);
1406 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter)
1414 state = rtw89_mac_get_req_pwr_state(rtwdev);
1419 rtw89_mac_send_rpwm(rtwdev, state, false);
1422 rtwdev, state);
1427 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n",
1430 rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
1436 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev)
1440 state = rtw89_mac_get_req_pwr_state(rtwdev);
1441 rtw89_mac_send_rpwm(rtwdev, state, true);
1444 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)
1447 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1448 const struct rtw89_chip_info *chip = rtwdev->chip;
1450 int (*cfg_func)(struct rtw89_dev *rtwdev);
1462 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
1463 __rtw89_leave_ps_mode(rtwdev);
1465 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);
1467 rtw89_err(rtwdev, "MAC has already powered on\n");
1471 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq);
1476 if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags))
1477 mac->efuse_read_fw_secure(rtwdev);
1479 set_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1480 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
1481 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
1482 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR);
1484 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1485 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
1486 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
1487 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
1488 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
1489 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR);
1490 rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false);
1491 rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false);
1498 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev)
1500 rtw89_mac_power_switch(rtwdev, false);
1503 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
1526 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1527 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1529 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1532 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en);
1533 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en);
1535 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en);
1536 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en);
1538 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1540 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1542 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1549 static int dmac_func_en_ax(struct rtw89_dev *rtwdev)
1551 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1570 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32);
1578 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32);
1583 static int chip_func_en_ax(struct rtw89_dev *rtwdev)
1585 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1587 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
1588 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
1594 static int sys_init_ax(struct rtw89_dev *rtwdev)
1598 ret = dmac_func_en_ax(rtwdev);
1602 ret = cmac_func_en_ax(rtwdev, 0, true);
1606 ret = chip_func_en_ax(rtwdev);
1701 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,
1704 struct rtw89_mac_info *mac = &rtwdev->mac;
1707 cfg = &rtwdev->chip->dle_mem[mode];
1712 rtw89_warn(rtwdev, "qta mode unmatch!\n");
1726 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev,
1730 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info;
1779 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev)
1785 grpnum = rtwdev->chip->wde_qempty_acq_grpnum;
1790 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
1792 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret);
1804 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel;
1805 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
1807 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret);
1814 if (rtwdev->dbcc_en) {
1828 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
1850 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev,
1853 u32 size = rtwdev->chip->fifo_size;
1856 size -= rtwdev->chip->dle_scc_rsvd_size;
1861 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable)
1864 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
1867 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN,
1871 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable)
1876 if (rtwdev->chip->chip_id == RTL8851B)
1878 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val);
1880 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val);
1884 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)
1890 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG);
1904 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");
1911 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val);
1913 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG);
1921 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");
1936 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val);
1941 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple)
1955 2000, false, rtwdev, reg);
1963 rtw89_write32(rtwdev, \
1970 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev,
1985 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev,
2002 if (rtwdev->chip->chip_id == RTL8852C)
2006 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow)
2012 if (rtwdev->chip->chip_id == RTL8852C)
2015 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) {
2016 rtw89_err(rtwdev, "[ERR]support SCC mode only\n");
2021 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW);
2023 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC);
2025 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
2038 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable)
2040 const struct rtw89_chip_info *chip = rtwdev->chip;
2043 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
2051 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
2053 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
2056 static void dle_quota_cfg(struct rtw89_dev *rtwdev,
2060 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2062 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu);
2063 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt);
2066 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
2069 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2074 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2078 cfg = get_dle_mem_cfg(rtwdev, mode);
2080 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
2086 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode);
2088 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n",
2096 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) {
2097 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
2102 mac->dle_func_en(rtwdev, false);
2103 mac->dle_clk_en(rtwdev, true);
2105 ret = mac->dle_mix_cfg(rtwdev, cfg);
2107 rtw89_err(rtwdev, "[ERR] dle mix cfg\n");
2110 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu);
2112 mac->dle_func_en(rtwdev, true);
2114 ret = mac->chk_dle_rdy(rtwdev, true);
2116 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n");
2120 ret = mac->chk_dle_rdy(rtwdev, false);
2122 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n");
2128 mac->dle_func_en(rtwdev, false);
2129 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n",
2130 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS));
2131 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n",
2132 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS));
2137 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
2146 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size);
2147 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN);
2152 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND);
2153 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size);
2158 static bool is_qta_poh(struct rtw89_dev *rtwdev)
2160 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
2163 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
2166 const struct rtw89_chip_info *chip = rtwdev->chip;
2168 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) ||
2169 !is_qta_poh(rtwdev))
2172 return preload_init_set(rtwdev, mac_idx, mode);
2175 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev)
2193 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
2201 static void _patch_ss2f_path(struct rtw89_dev *rtwdev)
2203 const struct rtw89_chip_info *chip = rtwdev->chip;
2205 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
2208 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK,
2212 static int sta_sch_init_ax(struct rtw89_dev *rtwdev)
2218 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2222 val = rtw89_read8(rtwdev, R_AX_SS_CTRL);
2224 rtw89_write8(rtwdev, R_AX_SS_CTRL, val);
2227 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL);
2229 rtw89_err(rtwdev, "[ERR]STA scheduler init\n");
2233 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG);
2234 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN);
2236 _patch_ss2f_path(rtwdev);
2241 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev)
2245 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2249 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
2250 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
2251 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC,
2253 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);
2258 static int sec_eng_init_ax(struct rtw89_dev *rtwdev)
2260 const struct rtw89_chip_info *chip = rtwdev->chip;
2264 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2268 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL);
2279 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val);
2282 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC);
2286 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val);
2289 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1,
2295 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2299 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
2301 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret);
2305 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode);
2307 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret);
2311 ret = rtw89_mac_hfc_init(rtwdev, true, true, true);
2313 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret);
2317 ret = sta_sch_init_ax(rtwdev);
2319 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret);
2323 ret = mpdu_proc_init_ax(rtwdev);
2325 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret);
2329 ret = sec_eng_init_ax(rtwdev);
2331 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret);
2338 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2344 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2348 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx);
2350 val = rtw89_read32(rtwdev, reg);
2353 rtw89_write32(rtwdev, reg, val);
2356 1, TRXCFG_WAIT_CNT, false, rtwdev, reg);
2358 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n");
2365 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2371 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2375 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx);
2376 if (rtwdev->chip->chip_id == RTL8852C)
2377 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
2380 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
2383 if (rtw89_is_rtl885xb(rtwdev)) {
2384 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx);
2385 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV);
2388 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx);
2389 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN);
2391 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx);
2392 if (rtwdev->chip->chip_id == RTL8852C) {
2393 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
2396 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
2399 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
2406 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev,
2425 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n");
2431 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx);
2434 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx);
2437 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx);
2440 rtw89_err(rtwdev, "[ERR]set rx filter type err\n");
2443 rtw89_write32(rtwdev, reg, val);
2448 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2453 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2458 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST,
2463 mac_ftlr = rtwdev->hal.rx_fltr;
2468 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx),
2470 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx),
2476 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx)
2487 switch (rtwdev->chip->chip_id) {
2490 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx);
2491 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav;
2492 rtw89_write32(rtwdev, reg, val32);
2494 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2495 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca;
2496 rtw89_write32(rtwdev, reg, val32);
2499 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx);
2500 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav;
2501 rtw89_write32(rtwdev, reg, val32);
2503 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2504 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca;
2505 rtw89_write32(rtwdev, reg, val32);
2510 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2515 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2519 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx);
2520 val = rtw89_read32(rtwdev, reg);
2535 rtw89_write32(rtwdev, reg, val);
2537 _patch_dis_resp_chk(rtwdev, mac_idx);
2542 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev)
2544 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN |
2547 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS);
2552 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2557 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2560 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx);
2561 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN);
2563 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx);
2564 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN);
2569 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2574 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2578 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx);
2579 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN);
2581 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx);
2582 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD);
2584 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx);
2585 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE);
2586 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE);
2591 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2593 const struct rtw89_chip_info *chip = rtwdev->chip;
2598 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2602 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2603 val = rtw89_read32(rtwdev, reg);
2607 switch (rtwdev->chip->chip_id) {
2622 rtw89_write32(rtwdev, reg, val);
2624 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx);
2625 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN);
2627 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx);
2628 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
2629 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx);
2630 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);
2635 static void rst_bacam(struct rtw89_dev *rtwdev)
2640 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK,
2645 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK);
2647 rtw89_warn(rtwdev, "failed to reset BA CAM\n");
2650 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2657 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2662 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2667 rst_bacam(rtwdev);
2669 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx);
2670 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL);
2672 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx);
2673 val = rtw89_read16(rtwdev, reg);
2680 rtw89_write16(rtwdev, reg, val);
2682 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx);
2683 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1);
2685 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx);
2687 rx_qta = rtwdev->mac.dle_info.c0_rx_qta;
2689 rx_qta = rtwdev->mac.dle_info.c1_rx_qta;
2691 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size;
2694 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len);
2696 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) {
2697 rtw89_write16_mask(rtwdev,
2698 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx),
2700 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx),
2704 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx);
2705 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK);
2710 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2712 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2716 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2720 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
2721 val = rtw89_read32(rtwdev, reg);
2725 rtw89_write32(rtwdev, reg, val);
2727 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
2728 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx);
2729 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN);
2735 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)
2739 cfg = get_dle_mem_cfg(rtwdev, mode);
2741 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
2748 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2750 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2754 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2758 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
2759 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx);
2760 val = rtw89_read32(rtwdev, reg);
2766 rtw89_write32(rtwdev, reg, val);
2768 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx);
2769 val = rtw89_read32(rtwdev, reg);
2772 rtw89_write32(rtwdev, reg, val);
2776 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2778 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2782 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL,
2785 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1,
2789 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
2790 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx);
2791 rtw89_write32_mask(rtwdev, reg,
2798 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2803 if (!rtw89_is_rtl885xb(rtwdev))
2806 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2810 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx);
2811 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE);
2816 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2820 ret = scheduler_init_ax(rtwdev, mac_idx);
2822 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret);
2826 ret = addr_cam_init_ax(rtwdev, mac_idx);
2828 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx,
2833 ret = rx_fltr_init_ax(rtwdev, mac_idx);
2835 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx,
2840 ret = cca_ctrl_init_ax(rtwdev, mac_idx);
2842 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx,
2847 ret = nav_ctrl_init_ax(rtwdev);
2849 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx,
2854 ret = spatial_reuse_init_ax(rtwdev, mac_idx);
2856 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n",
2861 ret = tmac_init_ax(rtwdev, mac_idx);
2863 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret);
2867 ret = trxptcl_init_ax(rtwdev, mac_idx);
2869 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret);
2873 ret = rmac_init_ax(rtwdev, mac_idx);
2875 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret);
2879 ret = cmac_com_init_ax(rtwdev, mac_idx);
2881 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret);
2885 ret = ptcl_init_ax(rtwdev, mac_idx);
2887 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret);
2891 ret = cmac_dma_init_ax(rtwdev, mac_idx);
2893 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret);
2900 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev,
2903 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2904 const struct rtw89_chip_info *chip = rtwdev->chip;
2926 mac->cnv_efuse_state(rtwdev, false);
2932 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info);
2940 mac->cnv_efuse_state(rtwdev, true);
2945 static int rtw89_mac_setup_phycap_part0(struct rtw89_dev *rtwdev)
2947 const struct rtw89_chip_info *chip = rtwdev->chip;
2949 struct rtw89_efuse *efuse = &rtwdev->efuse;
2951 struct rtw89_hal *hal = &rtwdev->hal;
2958 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 0);
2989 rtw89_debug(rtwdev, RTW89_DBG_FW,
2993 rtw89_debug(rtwdev, RTW89_DBG_FW,
2996 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity);
2997 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity);
3002 static int rtw89_mac_setup_phycap_part1(struct rtw89_dev *rtwdev)
3004 const struct rtw89_chip_variant *variant = rtwdev->variant;
3007 struct rtw89_hal *hal = &rtwdev->hal;
3011 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 1);
3034 rtw89_debug(rtwdev, RTW89_DBG_FW, "phycap qam=%d/%d no_mcs_12_13=%d\n",
3040 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
3042 const struct rtw89_chip_info *chip = rtwdev->chip;
3045 ret = rtw89_mac_setup_phycap_part0(rtwdev);
3050 RTW89_CHK_FW_FEATURE(NO_PHYCAP_P1, &rtwdev->fw))
3053 return rtw89_mac_setup_phycap_part1(rtwdev);
3056 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band,
3071 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
3081 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx,
3084 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx);
3088 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
3092 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
3093 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx,
3096 val = rtw89_read16(rtwdev, reg);
3098 rtw89_write16(rtwdev, reg, val);
3103 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
3106 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx);
3110 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
3114 val = rtw89_read32(rtwdev, reg);
3116 rtw89_write32(rtwdev, reg, val);
3121 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
3126 *tx_en = rtw89_read16(rtwdev,
3127 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx));
3131 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
3137 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
3143 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
3149 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
3162 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
3167 *tx_en = rtw89_read32(rtwdev,
3168 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx));
3172 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
3178 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
3184 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
3190 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
3203 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
3207 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK);
3215 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
3219 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en,
3228 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id)
3236 rtw89_write32(rtwdev, reg, val);
3241 1, 2000, false, rtwdev, reg);
3252 static int set_cpuio_ax(struct rtw89_dev *rtwdev,
3266 rtw89_write32(rtwdev, reg, val);
3278 rtw89_write32(rtwdev, reg, val);
3289 rtw89_write32(rtwdev, reg, val);
3294 1, 2000, false, rtwdev, reg);
3305 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
3308 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3311 cfg = get_dle_mem_cfg(rtwdev, mode);
3313 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
3317 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) {
3318 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
3322 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU);
3324 return mac->dle_quota_change(rtwdev, band1_en);
3327 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en)
3329 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3334 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id);
3336 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n");
3346 ret = mac->set_cpuio(rtwdev, &ctrl_para, true);
3348 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n");
3352 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id);
3354 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n");
3364 ret = mac->set_cpuio(rtwdev, &ctrl_para, false);
3366 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n");
3373 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx)
3379 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
3383 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx);
3389 false, rtwdev, reg);
3396 static int band1_enable_ax(struct rtw89_dev *rtwdev)
3403 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL);
3405 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret);
3410 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4);
3411 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4);
3412 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX);
3413 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX);
3416 ret = band_idle_ck_b(rtwdev, 0);
3418 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret);
3422 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true);
3424 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
3429 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]);
3430 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]);
3433 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en);
3435 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret);
3439 ret = cmac_func_en_ax(rtwdev, 1, true);
3441 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret);
3445 ret = cmac_init_ax(rtwdev, 1);
3447 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret);
3451 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
3457 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev)
3459 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3461 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR);
3462 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
3465 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev)
3467 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3469 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
3472 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev)
3474 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3475 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3477 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3484 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3489 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3492 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR,
3496 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR,
3500 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev)
3502 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3504 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
3508 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
3512 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev)
3514 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3516 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
3518 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
3520 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
3522 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
3526 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev)
3528 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3530 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
3531 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
3534 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev)
3536 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3538 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
3539 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
3542 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev)
3544 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR,
3548 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev)
3550 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3552 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
3554 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
3556 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
3558 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
3560 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
3562 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
3566 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev)
3568 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR);
3569 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET);
3572 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev)
3574 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3576 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
3578 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3580 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3582 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
3584 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR);
3587 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3591 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx);
3592 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN |
3594 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN);
3597 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3599 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3602 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx);
3603 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
3604 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
3607 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3609 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3610 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3613 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx);
3614 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
3615 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
3618 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx);
3619 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
3620 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
3624 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3626 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3629 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx);
3630 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
3631 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
3634 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3636 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3639 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx);
3640 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
3641 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
3644 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3646 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3649 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx);
3650 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
3651 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);
3654 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx,
3659 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel);
3661 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n",
3667 rtw89_wdrls_imr_enable(rtwdev);
3668 rtw89_wsec_imr_enable(rtwdev);
3669 rtw89_mpdu_trx_imr_enable(rtwdev);
3670 rtw89_sta_sch_imr_enable(rtwdev);
3671 rtw89_txpktctl_imr_enable(rtwdev);
3672 rtw89_wde_imr_enable(rtwdev);
3673 rtw89_ple_imr_enable(rtwdev);
3674 rtw89_pktin_imr_enable(rtwdev);
3675 rtw89_dispatcher_imr_enable(rtwdev);
3676 rtw89_cpuio_imr_enable(rtwdev);
3677 rtw89_bbrpt_imr_enable(rtwdev);
3679 rtw89_scheduler_imr_enable(rtwdev, mac_idx);
3680 rtw89_ptcl_imr_enable(rtwdev, mac_idx);
3681 rtw89_cdma_imr_enable(rtwdev, mac_idx);
3682 rtw89_phy_intf_imr_enable(rtwdev, mac_idx);
3683 rtw89_rmac_imr_enable(rtwdev, mac_idx);
3684 rtw89_tmac_imr_enable(rtwdev, mac_idx);
3692 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en)
3694 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR,
3696 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR,
3698 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta)
3699 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1,
3703 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable)
3708 ret = band1_enable_ax(rtwdev);
3710 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret);
3714 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL);
3716 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret);
3720 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n");
3727 static int set_host_rpr_ax(struct rtw89_dev *rtwdev)
3729 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
3730 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3732 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0,
3735 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3737 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0,
3741 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30);
3742 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255);
3747 static int trx_init_ax(struct rtw89_dev *rtwdev)
3749 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3750 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;
3753 ret = dmac_init_ax(rtwdev, 0);
3755 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret);
3759 ret = cmac_init_ax(rtwdev, 0);
3761 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret);
3765 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) {
3766 ret = dbcc_enable_ax(rtwdev, true);
3768 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret);
3773 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
3775 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret);
3779 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
3781 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret);
3785 err_imr_ctrl_ax(rtwdev, true);
3787 ret = set_host_rpr_ax(rtwdev);
3789 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret);
3794 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG,
3800 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev)
3805 const struct rtw89_chip_info *chip = rtwdev->chip;
3813 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0);
3817 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1);
3822 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev)
3826 if (rtw89_is_rtl885xb(rtwdev)) {
3827 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);
3828 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);
3832 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL,
3835 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL);
3838 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL);
3841 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev)
3843 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
3845 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3846 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN |
3848 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3850 rtw89_disable_fw_watchdog(rtwdev);
3852 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3853 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3856 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason,
3862 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN)
3865 rtw89_write32(rtwdev, R_AX_UDM1, 0);
3866 rtw89_write32(rtwdev, R_AX_UDM2, 0);
3867 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0);
3868 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
3869 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0);
3870 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0);
3872 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3874 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL);
3882 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val);
3884 if (rtw89_is_rtl885xb(rtwdev))
3885 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL,
3888 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK,
3890 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3895 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE);
3903 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev)
3905 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3914 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val);
3917 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev)
3919 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3926 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val);
3931 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1);
3935 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val);
3937 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1,
3942 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11);
3943 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN);
3946 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev)
3948 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3951 mac->hci_func_en(rtwdev);
3952 mac->dmac_func_pre_en(rtwdev);
3954 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode);
3956 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret);
3960 ret = rtw89_mac_hfc_init(rtwdev, true, false, true);
3962 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret);
3969 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
3971 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
3973 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL,
3976 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3982 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
3984 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
3986 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL,
3989 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3995 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb)
3999 ret = rtw89_mac_power_switch(rtwdev, true);
4001 rtw89_mac_power_switch(rtwdev, false);
4002 ret = rtw89_mac_power_switch(rtwdev, true);
4007 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true);
4010 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0);
4011 if (rtwdev->dbcc_en)
4012 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1);
4015 ret = rtw89_mac_dmac_pre_init(rtwdev);
4019 if (rtwdev->hci.ops->mac_pre_init) {
4020 ret = rtwdev->hci.ops->mac_pre_init(rtwdev);
4025 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb);
4032 int rtw89_mac_init(struct rtw89_dev *rtwdev)
4034 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4035 const struct rtw89_chip_info *chip = rtwdev->chip;
4039 ret = rtw89_mac_partial_init(rtwdev, include_bb);
4043 ret = rtw89_chip_enable_bb_rf(rtwdev);
4047 ret = mac->sys_init(rtwdev);
4051 ret = mac->trx_init(rtwdev);
4055 ret = rtw89_mac_feat_init(rtwdev);
4059 if (rtwdev->hci.ops->mac_post_init) {
4060 ret = rtwdev->hci.ops->mac_post_init(rtwdev);
4065 rtw89_fw_send_all_early_h2c(rtwdev);
4066 rtw89_fw_h2c_set_ofld_cfg(rtwdev);
4070 rtw89_mac_power_switch(rtwdev, false);
4075 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
4077 struct rtw89_fw_secure *sec = &rtwdev->fw.sec;
4080 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot)
4084 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
4086 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0);
4090 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
4092 struct rtw89_fw_secure *sec = &rtwdev->fw.sec;
4094 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot)
4097 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
4099 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4);
4100 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004);
4101 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0);
4102 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0);
4103 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0);
4104 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B);
4105 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0);
4106 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109);
4109 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause)
4118 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) &&
4119 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4122 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
4126 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause);
4160 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev,
4163 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4170 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif_link->mac_idx);
4171 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif_link->mac_idx);
4173 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type);
4174 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN);
4178 true, rtwdev, reg_info, mask);
4180 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n");
4183 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev,
4186 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4189 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port));
4190 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK,
4192 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, B_AX_BCN_MSK_AREA_MASK,
4194 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK,
4196 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 2);
4197 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early,
4199 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space,
4201 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN);
4203 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM0);
4205 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM1);
4207 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port));
4208 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TBTT_PROHIB_EN);
4221 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev,
4224 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4226 const struct rtw89_chip_info *chip = rtwdev->chip;
4232 if (!rtw89_read32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN))
4237 backup_val = rtw89_read32_port(rtwdev, rtwvif_link, p->tbtt_prohib);
4241 rtw89_mac_bcn_drop(rtwdev, rtwvif_link);
4244 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->tbtt_prohib,
4246 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib,
4248 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->tbtt_early,
4250 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->bcn_early,
4262 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN |
4264 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSFTR_RST);
4265 rtw89_write32_port(rtwdev, rtwvif_link, p->bcn_cnt_tmr, 0);
4268 rtw89_write32_port(rtwdev, rtwvif_link, p->tbtt_prohib, backup_val);
4271 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev,
4274 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4278 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg,
4281 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg,
4285 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev,
4288 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4292 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg,
4295 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg,
4299 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev,
4302 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4305 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_NET_TYPE_MASK,
4309 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev,
4312 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4318 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bits);
4320 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bits);
4323 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev,
4326 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4333 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bit);
4335 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bit);
4338 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
4341 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4345 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN);
4347 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN);
4350 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev,
4356 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif_link, en);
4359 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev,
4362 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4366 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN);
4368 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN);
4371 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev,
4377 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en);
4380 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en)
4386 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4389 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en);
4392 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev,
4395 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4410 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, B_AX_BCN_SPACE_MASK,
4414 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev,
4418 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4423 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif_link->mac_idx);
4424 rtw89_write8(rtwdev, reg, win);
4427 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev,
4430 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4443 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif_link->mac_idx);
4444 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE);
4446 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->dtim_ctrl, B_AX_DTIM_NUM_MASK,
4450 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev,
4453 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4456 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib,
4460 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev,
4463 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4466 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib,
4470 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev,
4473 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4476 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area,
4480 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev,
4483 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4486 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early,
4490 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev,
4493 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4514 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif_link->mac_idx);
4515 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color);
4518 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev,
4521 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4530 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif_link->mac_idx);
4531 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK);
4535 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev,
4538 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4544 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif_link->mac_idx);
4545 val = rtw89_read32(rtwdev, reg);
4549 rtw89_write32(rtwdev, reg, val);
4552 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev,
4555 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4559 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg,
4562 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg,
4566 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev,
4569 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4572 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK,
4576 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev,
4579 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4583 if (rtwdev->chip->chip_id != RTL8852C)
4593 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift,
4597 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
4602 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4607 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif_link->port * 4,
4610 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port);
4611 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val);
4612 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW);
4615 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev,
4625 rtw89_mac_port_tsf_sync(rtwdev, rtwvif_link, rtwvif_src,
4631 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev)
4639 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
4653 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4655 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset,
4659 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
4663 ret = rtw89_mac_port_update(rtwdev, rtwvif_link);
4667 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif_link->mac_id);
4668 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif_link->mac_id);
4670 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif_link->mac_id, false);
4674 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_CREATE);
4678 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, NULL, true);
4682 ret = rtw89_cam_init(rtwdev, rtwvif_link);
4686 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL);
4690 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, NULL);
4694 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, NULL);
4701 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
4705 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_REMOVE);
4709 rtw89_cam_deinit(rtwdev, rtwvif_link);
4711 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL);
4718 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
4725 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link);
4726 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif_link, false);
4727 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif_link, false);
4728 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif_link);
4729 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif_link);
4730 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif_link);
4731 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif_link);
4732 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif_link);
4733 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif_link);
4734 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif_link);
4735 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif_link);
4736 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif_link);
4737 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif_link);
4738 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link);
4739 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link);
4740 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link);
4741 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif_link);
4742 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link);
4743 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link);
4744 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true);
4745 rtw89_mac_port_tsf_resync_all(rtwdev);
4747 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif_link);
4752 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4755 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4760 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif_link->mac_idx, RTW89_CMAC_SEL);
4764 tsf_low = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_l);
4765 tsf_high = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_h);
4790 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
4794 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4795 struct ieee80211_hw *hw = rtwdev->hw;
4821 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr,
4824 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask);
4826 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask);
4829 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
4831 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link);
4834 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
4836 return rtw89_mac_vif_init(rtwdev, rtwvif_link);
4839 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
4841 return rtw89_mac_vif_deinit(rtwdev, rtwvif_link);
4845 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4849 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel)
4851 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
4857 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4862 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif;
4865 u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf;
4878 if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw))
4890 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))
4893 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
4906 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN,
4911 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN,
4918 if (rtw89_is_op_chan(rtwdev, band, chan)) {
4919 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false);
4920 ieee80211_stop_queues(rtwdev->hw);
4924 if (rtwdev->scan_info.abort)
4929 ret = rtw89_hw_scan_offload(rtwdev, rtwvif_link, true);
4931 rtw89_hw_scan_abort(rtwdev, rtwvif_link);
4932 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret);
4935 rtw89_hw_scan_complete(rtwdev, rtwvif_link, false);
4940 if (rtw89_is_op_chan(rtwdev, band, chan)) {
4941 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx,
4942 &rtwdev->scan_info.op_chan);
4943 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true);
4944 ieee80211_wake_queues(rtwdev->hw);
4948 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx,
4958 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4977 rtw89_debug(rtwdev, RTW89_DBG_FW,
4983 if (!rtwdev->scanning && !rtwvif->offchan)
4986 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true);
5007 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
5014 rtw89_for_each_rtwvif(rtwdev, rtwvif)
5016 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif_link, c2h);
5020 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5024 rtw89_debug(rtwdev, RTW89_DBG_FW,
5033 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len)
5036 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
5037 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait;
5048 rtw89_debug(rtwdev, RTW89_DBG_FW,
5092 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5094 rtw89_fw_log_dump(rtwdev, c2h->data, len);
5098 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5103 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h,
5106 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
5115 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n",
5125 rtw89_mac_c2h_tx_duty_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len)
5133 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "C2H TX duty rpt with err=%d\n", err);
5137 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
5140 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE);
5144 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5161 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5166 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5171 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5194 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5199 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5208 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5212 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5227 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5239 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5243 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5295 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5300 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5314 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5318 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5320 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
5338 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5352 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len)
5354 struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
5381 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5383 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
5413 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5417 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5421 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5425 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5429 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5433 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5437 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5441 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5445 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5449 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5453 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5458 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5475 rtw89_mac_c2h_pwr_int_notify(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len)
5490 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid);
5508 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,
5522 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev,
5531 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev,
5540 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev,
5547 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev,
5553 void (* const rtw89_mac_c2h_ap_handler[])(struct rtw89_dev *rtwdev,
5558 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev,
5563 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
5573 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
5582 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
5601 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h);
5622 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
5625 void (*handler)(struct rtw89_dev *rtwdev,
5656 rtw89_info(rtwdev, "MAC c2h class %d not support\n", class);
5660 rtw89_info(rtwdev, "MAC c2h class %d func %d not support\n", class,
5664 handler(rtwdev, skb, len);
5668 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev,
5672 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode;
5673 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx);
5676 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n",
5683 rtw89_err(rtwdev,
5693 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n",
5700 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
5702 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx);
5705 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5710 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN);
5714 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN |
5718 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK,
5725 void __rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx)
5733 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
5734 struct ieee80211_hw *hw = rtwdev->hw;
5750 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx);
5751 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th);
5752 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th);
5755 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev)
5757 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0);
5758 if (rtwdev->dbcc_en)
5759 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_1);
5762 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop)
5767 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5771 10000, 200000, false, rtwdev);
5772 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning))
5773 rtw89_info(rtwdev, "timed out to flush queues\n");
5776 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex)
5778 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
5784 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT);
5786 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN);
5787 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8);
5788 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK);
5789 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16);
5791 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24);
5793 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0);
5795 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16);
5797 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32);
5799 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n");
5803 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32);
5805 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n");
5811 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
5814 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
5816 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE);
5817 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);
5819 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5);
5822 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val);
5825 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
5828 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
5830 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE);
5838 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16);
5840 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE);
5848 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
5850 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
5853 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
5855 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
5858 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
5860 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
5870 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
5873 rtw89_write32_set(rtwdev, R_AX_BTC_CFG,
5875 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN);
5876 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN);
5877 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN);
5881 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
5883 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1,
5887 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
5898 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
5927 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val);
5929 rtw89_err(rtwdev, "Write LTE fail!\n");
5937 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
5978 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val);
5985 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
5991 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);
5995 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band);
6005 rtw89_write16(rtwdev, reg, val);
6010 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)
6014 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD);
6017 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
6025 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val);
6029 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev)
6031 return rtw89_read32(rtwdev, R_AX_SCOREBOARD);
6034 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
6036 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);
6039 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val);
6045 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl)
6047 struct rtw89_btc *btc = &rtwdev->btc;
6062 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt);
6066 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev)
6068 const struct rtw89_chip_info *chip = rtwdev->chip;
6073 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
6074 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3,
6080 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band)
6085 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band);
6086 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK);
6087 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST);
6092 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx,
6097 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
6100 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep);
6101 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);
6103 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
6104 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,
6107 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
6108 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,
6113 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
6115 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6119 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en);
6120 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx);
6122 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
6123 rtw89_write32_set(rtwdev, reg, mask);
6125 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
6126 rtw89_write32_clr(rtwdev, reg, mask);
6130 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
6136 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6142 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx);
6143 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN);
6145 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx);
6146 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP);
6148 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);
6150 rtw89_write32(rtwdev, reg, val32);
6151 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true);
6152 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);
6154 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
6155 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL |
6159 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx);
6160 rtw89_write32(rtwdev, reg,
6165 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx);
6166 rtw89_write32_set(rtwdev, reg,
6172 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev,
6186 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6216 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
6217 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
6228 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
6230 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx);
6232 rtw89_write16(rtwdev, reg, val);
6237 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev,
6247 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6273 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
6274 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
6275 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN);
6276 rtw89_write32(rtwdev,
6277 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx),
6283 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev,
6298 rtw89_debug(rtwdev, RTW89_DBG_BF,
6300 rtw89_mac_init_bfee_ax(rtwdev, rtwvif_link->mac_idx);
6301 rtw89_mac_set_csi_para_reg_ax(rtwdev, rtwvif_link, rtwsta_link);
6302 rtw89_mac_csi_rrsc_ax(rtwdev, rtwvif_link, rtwsta_link);
6306 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev,
6310 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, false);
6313 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
6323 rtw89_err(rtwdev,
6331 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n");
6334 rtw89_write32(rtwdev,
6335 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx),
6337 rtw89_write32(rtwdev,
6338 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx),
6342 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx),
6344 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx),
6346 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx),
6348 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx),
6353 struct rtw89_dev *rtwdev;
6390 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
6396 data.rtwdev = rtwdev;
6399 ieee80211_iterate_stations_atomic(rtwdev->hw,
6403 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count);
6405 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
6407 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
6410 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
6412 struct rtw89_traffic_stats *stats = &rtwdev->stats;
6415 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
6421 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
6427 rtw89_for_each_rtwvif(rtwdev, rtwvif)
6429 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif_link->mac_idx,
6436 rtw89_for_each_rtwvif(rtwdev, rtwvif)
6438 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, en);
6442 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link,
6453 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link);
6455 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6457 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n");
6461 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx);
6462 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK,
6469 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link,
6476 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time);
6478 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time);
6485 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link,
6495 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6497 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n");
6501 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx);
6502 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5;
6508 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
6518 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link);
6520 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link);
6527 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
6537 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6539 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n");
6543 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx);
6544 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK);
6550 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
6553 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6559 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6563 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx);
6565 rtw89_write16_set(rtwdev, reg, set);
6567 rtw89_write16_clr(rtwdev, reg, set);
6573 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
6583 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
6586 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
6588 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
6597 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
6607 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
6610 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
6612 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);
6616 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1);
6622 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev,
6643 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms);
6651 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6662 rtw89_mac_pkt_drop_sta(rtwdev, rtwvif_link, rtwsta_link);
6666 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
6668 ieee80211_iterate_stations_atomic(rtwdev->hw,
6673 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
6676 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6686 50000, false, rtwdev);
6687 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw))
6688 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms);
6695 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
6701 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw))
6708 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
6718 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow)
6720 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6721 const struct rtw89_chip_info *chip = rtwdev->chip;
6725 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true);
6727 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
6731 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
6732 rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
6733 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE);
6734 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
6735 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0);
6736 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0);
6737 rtw89_write32(rtwdev, R_AX_TF_FWD, 0);
6738 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0);
6740 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw))
6743 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
6744 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY);
6746 rtw89_write32_set(rtwdev, R_AX_DBG_WOW,
6749 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false);
6751 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
6755 rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
6756 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
6757 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
6758 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
6759 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
6765 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type)
6767 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL);
6773 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev,
6781 rtwdev, R_AX_WCPU_FW_CTRL);
6785 void rtw89_fwdl_secure_idmem_share_mode_ax(struct rtw89_dev *rtwdev, u8 mode)
6787 struct rtw89_fw_secure *sec = &rtwdev->fw.sec;
6792 rtw89_write32_mask(rtwdev, R_AX_WCPU_FW_CTRL,
6794 rtw89_write32_set(rtwdev, R_AX_WCPU_FW_CTRL,