Lines Matching refs:imr

782 	u32 dmac_err, imr, isr;
792 			imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR);
796 			    ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) {
3459 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3462 	rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
3467 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3469 	rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
3475 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3490 			  imr->mpdu_tx_imr_set);
3497 			  imr->mpdu_rx_imr_set);
3502 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3509 			  imr->sta_sch_imr_set);
3514 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3516 	rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
3517 			  imr->txpktctl_imr_b0_clr);
3518 	rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
3519 			  imr->txpktctl_imr_b0_set);
3520 	rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
3521 			  imr->txpktctl_imr_b1_clr);
3522 	rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
3523 			  imr->txpktctl_imr_b1_set);
3528 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3530 	rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
3531 	rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
3536 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3538 	rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
3539 	rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
3550 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3553 			  imr->host_disp_imr_clr);
3555 			  imr->host_disp_imr_set);
3557 			  imr->cpu_disp_imr_clr);
3559 			  imr->cpu_disp_imr_set);
3561 			  imr->other_disp_imr_clr);
3563 			  imr->other_disp_imr_set);
3574 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3576 	rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
3578 	rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3580 	rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3581 			  imr->bbrpt_err_imr_set);
3582 	rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
3599 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3603 	rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
3604 	rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
3609 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3613 	reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx);
3614 	rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
3615 	rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
3618 		reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx);
3619 		rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
3620 		rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
3626 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3629 	reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx);
3630 	rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
3631 	rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
3636 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3639 	reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx);
3640 	rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
3641 	rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
3646 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3649 	reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx);
3650 	rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
3651 	rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);