Lines Matching +full:dma +full:- +full:byte +full:- +full:en
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
44 u32 addr = mac->mem_base_addrs[sel] + offset;
46 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
47 rtw89_write32(rtwdev, mac->indir_access_addr, val);
53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
54 u32 addr = mac->mem_base_addrs[sel] + offset;
56 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
57 return rtw89_read32(rtwdev, mac->indir_access_addr);
75 return -EINVAL;
79 return -EFAULT;
122 switch (ctrl->type) {
126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) |
127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) |
133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) |
134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) |
138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type);
139 return -EINVAL;
152 ctrl->out_data = rtw89_read32(rtwdev, data_reg);
162 ctrl.type = quota->dle_type;
164 ctrl.addr = quota->qtaid;
171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data);
172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data);
182 ctrl.type = qempty->dle_type;
184 ctrl.addr = qempty->grpsel;
191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data);
305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
314 mac->dump_qta_lost(rtwdev);
323 const struct rtw89_chip_info *chip = rtwdev->chip;
343 if (chip->chip_id == RTL8852C) {
360 if (chip->chip_id == RTL8852C)
369 if (chip->chip_id == RTL8852C) {
401 } else if (chip->chip_id == RTL8922A) {
452 if (chip->chip_id == RTL8922A) {
477 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) {
515 if (chip->chip_id == RTL8922A) {
529 if (chip->chip_id == RTL8852C) {
555 if (chip->chip_id == RTL8922A) {
585 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) {
610 if (chip->chip_id == RTL8922A) {
619 if (chip->chip_id == RTL8922A) {
624 } else if (chip->chip_id == RTL8852C) {
659 const struct rtw89_chip_info *chip = rtwdev->chip;
699 if (chip->chip_id == RTL8852C) {
711 if (chip->chip_id == RTL8852C) {
730 if (chip->chip_id == RTL8852C) {
757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
771 rtwdev->hci.ops->dump_err_status(rtwdev);
776 rtw89_info(rtwdev, "<---\n");
781 struct rtw89_ser *ser = &rtwdev->ser;
785 if (rtwdev->chip->chip_id == RTL8852C) {
797 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags);
801 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags))
804 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags))
814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
840 mac->dump_err_status(rtwdev, err);
848 struct rtw89_ser *ser = &rtwdev->ser;
853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err);
854 return -EINVAL;
861 return -EFAULT;
866 if (ser->prehandle_l1 &&
878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
882 switch (rtwdev->hci.type) {
884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode];
885 param->en = 0;
888 return -EINVAL;
892 param->pub_cfg = *param_ini.pub_cfg;
895 param->prec_cfg = *param_ini.prec_cfg;
898 param->ch_cfg = param_ini.ch_cfg;
900 memset(¶m->ch_info, 0, sizeof(param->ch_info));
901 memset(¶m->pub_info, 0, sizeof(param->pub_info));
902 param->mode = param_ini.mode;
909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
910 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg;
911 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
912 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
915 return -EINVAL;
917 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) ||
918 ch_cfg[ch].max > pub_cfg->pub_max)
919 return -EINVAL;
921 return -EINVAL;
928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
929 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg;
930 struct rtw89_hfc_pub_info *info = ¶m->pub_info;
932 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) {
933 if (rtwdev->chip->chip_id == RTL8852A)
936 return -EFAULT;
944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
945 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
947 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max)
948 return -EFAULT;
955 const struct rtw89_chip_info *chip = rtwdev->chip;
956 const struct rtw89_page_regs *regs = chip->page_regs;
957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
958 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
971 return -EINVAL;
976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);
983 const struct rtw89_chip_info *chip = rtwdev->chip;
984 const struct rtw89_page_regs *regs = chip->page_regs;
985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
986 struct rtw89_hfc_ch_info *info = param->ch_info;
987 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
996 return -EINVAL;
998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);
1003 info[ch].used = cfg[ch].min - info[ch].aval;
1010 const struct rtw89_chip_info *chip = rtwdev->chip;
1011 const struct rtw89_page_regs *regs = chip->page_regs;
1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg;
1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) |
1025 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK);
1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);
1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK);
1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);
1036 const struct rtw89_chip_info *chip = rtwdev->chip;
1037 const struct rtw89_page_regs *regs = chip->page_regs;
1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1039 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
1040 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
1041 struct rtw89_hfc_pub_info *info = ¶m->pub_info;
1044 val = rtw89_read32(rtwdev, regs->pub_page_info1);
1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK);
1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK);
1047 val = rtw89_read32(rtwdev, regs->pub_page_info3);
1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK);
1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK);
1050 info->pub_aval =
1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2),
1053 info->wp_aval =
1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1),
1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0;
1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0;
1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK);
1061 prec_cfg->ch011_full_cond =
1063 prec_cfg->h2c_full_cond =
1065 prec_cfg->wp_ch07_full_cond =
1067 prec_cfg->wp_ch811_full_cond =
1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl);
1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK);
1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK);
1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);
1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK);
1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);
1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK);
1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK);
1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);
1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK);
1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);
1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK);
1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK);
1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1099 mac->hfc_get_mix_info(rtwdev);
1102 if (param->en && ret)
1110 const struct rtw89_chip_info *chip = rtwdev->chip;
1111 const struct rtw89_page_regs *regs = chip->page_regs;
1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1113 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl,
1121 prec_cfg->h2c_full_cond);
1126 const struct rtw89_chip_info *chip = rtwdev->chip;
1127 const struct rtw89_page_regs *regs = chip->page_regs;
1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1129 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
1130 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) |
1134 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK);
1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);
1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec,
1142 u32_encode_bits(prec_cfg->wp_ch811_prec,
1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);
1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),
1147 param->mode, B_AX_HCI_FC_MODE_MASK);
1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1159 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
1161 const struct rtw89_chip_info *chip = rtwdev->chip;
1162 const struct rtw89_page_regs *regs = chip->page_regs;
1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1167 param->en = en;
1168 param->h2c_en = h2c_en;
1169 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN);
1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1175 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en)
1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1178 const struct rtw89_chip_info *chip = rtwdev->chip;
1179 u32 dma_ch_mask = chip->dma_ch_mask;
1192 mac->hfc_func_en(rtwdev, false, false);
1194 if (!en && h2c_en) {
1195 mac->hfc_h2c_cfg(rtwdev);
1196 mac->hfc_func_en(rtwdev, en, h2c_en);
1212 mac->hfc_mix_cfg(rtwdev);
1213 if (en || h2c_en) {
1214 mac->hfc_func_en(rtwdev, en, h2c_en);
1235 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ?
1236 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr;
1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk),
1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr);
1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);
1248 return -EBUSY;
1258 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) {
1259 if (!(cur_cfg->intf_msk & intf_msk) ||
1260 !(cur_cfg->cv_msk & cv_msk))
1263 switch (cur_cfg->cmd) {
1265 addr = cur_cfg->addr;
1267 if (cur_cfg->base == PWR_BASE_SDIO)
1271 val &= ~(cur_cfg->msk);
1272 val |= (cur_cfg->val & cur_cfg->msk);
1278 return -EBUSY;
1281 if (cur_cfg->val == PWR_DELAY_US)
1282 udelay(cur_cfg->addr);
1284 fsleep(cur_cfg->addr * 1000);
1287 return -EINVAL;
1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv),
1303 return -EBUSY;
1314 switch (rtwdev->ps_mode) {
1337 spin_lock_bh(&rtwdev->rpwm_lock);
1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) &
1349 rtwdev->mac.rpwm_seq_num);
1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request);
1356 spin_unlock_bh(&rtwdev->rpwm_lock);
1380 return -EPERM;
1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num;
1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr,
1390 return -EPERM;
1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) &
1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM);
1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num)
1397 return -EPERM;
1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE);
1401 return -EPERM;
1426 if (i == RPWM_TRY_CNT - 1)
1447 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1448 const struct rtw89_chip_info *chip = rtwdev->chip;
1455 cfg_seq = chip->pwr_on_seq;
1456 cfg_func = chip->ops->pwr_on_func;
1458 cfg_seq = chip->pwr_off_seq;
1459 cfg_func = chip->ops->pwr_off_func;
1462 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
1468 return -EBUSY;
1476 if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags))
1477 mac->efuse_read_fw_secure(rtwdev);
1479 set_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1480 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
1481 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
1484 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1485 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
1486 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
1487 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
1488 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
1503 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
1524 if (en) {
1551 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1585 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1704 struct rtw89_mac_info *mac = &rtwdev->mac;
1707 cfg = &rtwdev->chip->dle_mem[mode];
1711 if (cfg->mode != mode) {
1716 mac->dle_info.rsvd_qt = cfg->rsvd_qt;
1717 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size;
1718 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num;
1719 mac->dle_info.qta_mode = mode;
1720 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma;
1721 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma;
1730 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info;
1731 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt;
1735 cfg->pktid = dle_info->ple_free_pg;
1736 cfg->pg_num = rsvd_qt->mpdu_info_tbl;
1739 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl;
1740 cfg->pg_num = rsvd_qt->b0_csi;
1743 cfg->pktid = dle_info->ple_free_pg +
1744 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi;
1745 cfg->pg_num = rsvd_qt->b1_csi;
1748 cfg->pktid = dle_info->ple_free_pg +
1749 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi;
1750 cfg->pg_num = rsvd_qt->b0_lmr;
1753 cfg->pktid = dle_info->ple_free_pg +
1754 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi +
1755 rsvd_qt->b0_lmr;
1756 cfg->pg_num = rsvd_qt->b1_lmr;
1759 cfg->pktid = dle_info->ple_free_pg +
1760 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi +
1761 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr;
1762 cfg->pg_num = rsvd_qt->b0_ftm;
1765 cfg->pktid = dle_info->ple_free_pg +
1766 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi +
1767 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm;
1768 cfg->pg_num = rsvd_qt->b1_ftm;
1771 return -EINVAL;
1774 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size;
1785 grpnum = rtwdev->chip->wde_qempty_acq_grpnum;
1804 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel;
1814 if (rtwdev->dbcc_en) {
1835 const struct rtw89_dle_size *wde = cfg->wde_size;
1836 const struct rtw89_dle_size *ple = cfg->ple_size;
1839 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) +
1840 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num);
1842 if (cfg->rsvd0_size && cfg->rsvd1_size) {
1843 used += cfg->rsvd0_size->size;
1844 used += cfg->rsvd1_size->size;
1853 u32 size = rtwdev->chip->fifo_size;
1856 size -= rtwdev->chip->dle_scc_rsvd_size;
1876 if (rtwdev->chip->chip_id == RTL8851B)
1891 size_cfg = cfg->wde_size;
1893 switch (size_cfg->pge_size) {
1904 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");
1905 return -EINVAL;
1909 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1914 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num)
1915 * size_cfg->pge_size / DLE_BOUND_UNIT;
1916 size_cfg = cfg->ple_size;
1918 switch (size_cfg->pge_size) {
1921 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");
1922 return -EINVAL;
1934 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1968 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
1976 ext_wde_min_qt_wcpu : min_cfg->wcpu;
1980 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1);
2002 if (rtwdev->chip->chip_id == RTL8852C)
2012 if (rtwdev->chip->chip_id == RTL8852C)
2015 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) {
2017 return -EINVAL;
2026 return -EINVAL;
2029 min_cfg = cfg->ple_min_qt;
2030 max_cfg = cfg->ple_max_qt;
2040 const struct rtw89_chip_info *chip = rtwdev->chip;
2043 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
2047 if (chip->chip_id == RTL8852C)
2060 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2062 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu);
2063 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt);
2069 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2081 ret = -EINVAL;
2090 ret = -EINVAL;
2093 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu;
2098 ret = -EINVAL;
2102 mac->dle_func_en(rtwdev, false);
2103 mac->dle_clk_en(rtwdev, true);
2105 ret = mac->dle_mix_cfg(rtwdev, cfg);
2112 mac->dle_func_en(rtwdev, true);
2114 ret = mac->chk_dle_rdy(rtwdev, true);
2120 ret = mac->chk_dle_rdy(rtwdev, false);
2128 mac->dle_func_en(rtwdev, false);
2160 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
2166 const struct rtw89_chip_info *chip = rtwdev->chip;
2168 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) ||
2203 const struct rtw89_chip_info *chip = rtwdev->chip;
2205 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
2260 const struct rtw89_chip_info *chip = rtwdev->chip;
2274 if (chip->chip_id == RTL8852C)
2276 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
2277 chip->chip_id == RTL8851B)
2288 if (chip->chip_id == RTL8852C)
2299 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
2305 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode);
2376 if (rtwdev->chip->chip_id == RTL8852C)
2392 if (rtwdev->chip->chip_id == RTL8852C) {
2426 return -EINVAL;
2441 return -EINVAL;
2463 mac_ftlr = rtwdev->hal.rx_fltr;
2487 switch (rtwdev->chip->chip_id) {
2593 const struct rtw89_chip_info *chip = rtwdev->chip;
2594 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs;
2607 switch (rtwdev->chip->chip_id) {
2627 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx);
2628 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
2629 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx);
2630 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);
2657 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2687 rx_qta = rtwdev->mac.dle_info.c0_rx_qta;
2689 rx_qta = rtwdev->mac.dle_info.c1_rx_qta;
2691 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size;
2696 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) {
2712 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2745 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma);
2750 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2758 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
2893 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret);
2903 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2904 const struct rtw89_chip_info *chip = rtwdev->chip;
2910 if (chip->chip_gen == RTW89_CHIP_AX)
2923 return -EINVAL;
2926 mac->cnv_efuse_state(rtwdev, false);
2936 if (c2h_info->id != c2h_type)
2937 ret = -EINVAL;
2940 mac->cnv_efuse_state(rtwdev, true);
2947 const struct rtw89_chip_info *chip = rtwdev->chip;
2949 struct rtw89_efuse *efuse = &rtwdev->efuse;
2951 struct rtw89_hal *hal = &rtwdev->hal;
2964 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS);
2965 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS);
2966 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM);
2967 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM);
2969 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss;
2970 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss;
2973 hal->antenna_tx = RF_B;
2975 hal->antenna_rx = RF_B;
2978 hal->antenna_tx = RF_B;
2979 hal->tx_path_diversity = true;
2982 if (chip->rf_path_num == 1) {
2983 hal->antenna_tx = RF_A;
2984 hal->antenna_rx = RF_A;
2985 if ((efuse->rfe_type % 3) == 2)
2986 hal->ant_diversity = true;
2991 hal->tx_nss, tx_nss, chip->tx_nss,
2992 hal->rx_nss, rx_nss, chip->rx_nss);
2995 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx);
2996 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity);
2997 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity);
3004 const struct rtw89_chip_variant *variant = rtwdev->variant;
3007 struct rtw89_hal *hal = &rtwdev->hal;
3017 qam_raw = u32_get_bits(phycap->w2, RTW89_C2HREG_PHYCAP_P1_W2_QAM);
3030 if ((variant && variant->no_mcs_12_13) ||
3032 hal->no_mcs_12_13 = true;
3035 qam_raw, qam, hal->no_mcs_12_13);
3042 const struct rtw89_chip_info *chip = rtwdev->chip;
3049 if (chip->chip_gen == RTW89_CHIP_AX ||
3050 RTW89_CHK_FW_FEATURE(NO_PHYCAP_P1, &rtwdev->fw))
3065 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN;
3067 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN);
3068 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK);
3069 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND);
3076 return -EINVAL;
3092 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
3247 return -ENOENT;
3258 cmd_type = ctrl_para->cmd_type;
3262 val = u32_replace_bits(val, ctrl_para->start_pktid,
3264 val = u32_replace_bits(val, ctrl_para->end_pktid,
3270 val = u32_replace_bits(val, ctrl_para->src_pid,
3272 val = u32_replace_bits(val, ctrl_para->src_qid,
3274 val = u32_replace_bits(val, ctrl_para->dst_pid,
3276 val = u32_replace_bits(val, ctrl_para->dst_qid,
3284 val = u32_replace_bits(val, ctrl_para->macid,
3286 val = u32_replace_bits(val, ctrl_para->pkt_num,
3300 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val);
3308 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3314 return -EINVAL;
3319 return -EINVAL;
3324 return mac->dle_quota_change(rtwdev, band1_en);
3329 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3334 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id);
3346 ret = mac->set_cpuio(rtwdev, &ctrl_para, true);
3349 return -EFAULT;
3352 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id);
3364 ret = mac->set_cpuio(rtwdev, &ctrl_para, false);
3367 return -EFAULT;
3422 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true);
3441 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret);
3459 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3462 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
3467 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3469 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
3474 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3475 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3490 imr->mpdu_tx_imr_set);
3497 imr->mpdu_rx_imr_set);
3502 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3509 imr->sta_sch_imr_set);
3514 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3516 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
3517 imr->txpktctl_imr_b0_clr);
3518 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
3519 imr->txpktctl_imr_b0_set);
3520 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
3521 imr->txpktctl_imr_b1_clr);
3522 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
3523 imr->txpktctl_imr_b1_set);
3528 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3530 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
3531 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
3536 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3538 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
3539 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
3550 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3553 imr->host_disp_imr_clr);
3555 imr->host_disp_imr_set);
3557 imr->cpu_disp_imr_clr);
3559 imr->cpu_disp_imr_set);
3561 imr->other_disp_imr_clr);
3563 imr->other_disp_imr_set);
3574 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3576 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
3578 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3580 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3581 imr->bbrpt_err_imr_set);
3582 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
3599 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3603 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
3604 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
3609 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3610 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3613 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx);
3614 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
3615 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
3618 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx);
3619 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
3620 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
3626 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3629 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx);
3630 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
3631 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
3636 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3639 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx);
3640 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
3641 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
3646 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3649 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx);
3650 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
3651 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);
3686 return -EINVAL;
3692 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en)
3695 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS);
3697 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS);
3698 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta)
3700 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS);
3721 return -EINVAL;
3729 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
3749 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3750 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;
3805 const struct rtw89_chip_info *chip = rtwdev->chip;
3808 if (chip->bacam_ver != RTW89_BACAM_V1)
3843 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
3863 return -EFAULT;
3905 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3919 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3948 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3951 mac->hci_func_en(rtwdev);
3952 mac->dmac_func_pre_en(rtwdev);
3954 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode);
4011 if (rtwdev->dbcc_en)
4019 if (rtwdev->hci.ops->mac_pre_init) {
4020 ret = rtwdev->hci.ops->mac_pre_init(rtwdev);
4034 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4035 const struct rtw89_chip_info *chip = rtwdev->chip;
4036 bool include_bb = !!chip->bbmcu_nr;
4047 ret = mac->sys_init(rtwdev);
4051 ret = mac->trx_init(rtwdev);
4059 if (rtwdev->hci.ops->mac_post_init) {
4060 ret = rtwdev->hci.ops->mac_post_init(rtwdev);
4077 struct rtw89_fw_secure *sec = &rtwdev->fw.sec;
4080 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot)
4092 struct rtw89_fw_secure *sec = &rtwdev->fw.sec;
4094 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot)
4116 * be power-off, so ignore this operation.
4118 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) &&
4119 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4163 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4164 const struct rtw89_port_reg *p = mac->port_base;
4165 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif_link->port);
4170 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif_link->mac_idx);
4171 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif_link->mac_idx);
4186 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4187 const struct rtw89_port_reg *p = mac->port_base;
4189 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port));
4190 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK,
4192 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, B_AX_BCN_MSK_AREA_MASK,
4194 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK,
4196 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 2);
4197 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early,
4199 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space,
4201 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN);
4204 if (rtwvif_link->port == RTW89_PORT_0)
4207 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port));
4208 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TBTT_PROHIB_EN);
4224 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4225 const struct rtw89_port_reg *p = mac->port_base;
4226 const struct rtw89_chip_info *chip = rtwdev->chip;
4232 if (!rtw89_read32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN))
4235 if (chip->chip_id == RTL8852A && rtwvif_link->port != RTW89_PORT_0) {
4237 backup_val = rtw89_read32_port(rtwdev, rtwvif_link, p->tbtt_prohib);
4240 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE)
4243 if (chip->chip_id == RTL8852A) {
4244 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->tbtt_prohib,
4246 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib,
4248 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->tbtt_early,
4250 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->bcn_early,
4257 beacon_int = bss_conf->beacon_int;
4262 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN |
4264 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSFTR_RST);
4265 rtw89_write32_port(rtwdev, rtwvif_link, p->bcn_cnt_tmr, 0);
4268 rtw89_write32_port(rtwdev, rtwvif_link, p->tbtt_prohib, backup_val);
4272 struct rtw89_vif_link *rtwvif_link, bool en)
4274 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4275 const struct rtw89_port_reg *p = mac->port_base;
4277 if (en)
4278 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg,
4281 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg,
4286 struct rtw89_vif_link *rtwvif_link, bool en)
4288 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4289 const struct rtw89_port_reg *p = mac->port_base;
4291 if (en)
4292 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg,
4295 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg,
4302 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4303 const struct rtw89_port_reg *p = mac->port_base;
4305 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_NET_TYPE_MASK,
4306 rtwvif_link->net_type);
4312 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4313 const struct rtw89_port_reg *p = mac->port_base;
4314 bool en = rtwvif_link->net_type != RTW89_NET_TYPE_NO_LINK;
4317 if (en)
4318 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bits);
4320 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bits);
4326 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4327 const struct rtw89_port_reg *p = mac->port_base;
4328 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA ||
4329 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC;
4332 if (en)
4333 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bit);
4335 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bit);
4339 struct rtw89_vif_link *rtwvif_link, bool en)
4341 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4342 const struct rtw89_port_reg *p = mac->port_base;
4344 if (en)
4345 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN);
4347 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN);
4353 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA ||
4354 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC;
4356 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif_link, en);
4360 struct rtw89_vif_link *rtwvif_link, bool en)
4362 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4363 const struct rtw89_port_reg *p = mac->port_base;
4365 if (en)
4366 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN);
4368 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN);
4374 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE ||
4375 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC;
4377 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en);
4380 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en)
4388 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE)
4389 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en);
4395 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4396 const struct rtw89_port_reg *p = mac->port_base;
4403 if (bss_conf->beacon_int)
4404 bcn_int = bss_conf->beacon_int;
4410 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, B_AX_BCN_SPACE_MASK,
4417 u8 win = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0;
4418 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4419 const struct rtw89_port_reg *p = mac->port_base;
4420 u8 port = rtwvif_link->port;
4423 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif_link->mac_idx);
4430 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4431 const struct rtw89_port_reg *p = mac->port_base;
4439 dtim_period = bss_conf->dtim_period;
4443 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif_link->mac_idx);
4446 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->dtim_ctrl, B_AX_DTIM_NUM_MASK,
4453 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4454 const struct rtw89_port_reg *p = mac->port_base;
4456 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib,
4463 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4464 const struct rtw89_port_reg *p = mac->port_base;
4466 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib,
4473 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4474 const struct rtw89_port_reg *p = mac->port_base;
4476 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area,
4483 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4484 const struct rtw89_port_reg *p = mac->port_base;
4486 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early,
4493 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4494 const struct rtw89_port_reg *p = mac->port_base;
4501 u8 port = rtwvif_link->port;
4509 bss_color = bss_conf->he_bss_color.color;
4513 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color;
4514 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif_link->mac_idx);
4521 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4522 const struct rtw89_port_reg *p = mac->port_base;
4523 u8 port = rtwvif_link->port;
4526 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE)
4530 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif_link->mac_idx);
4538 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4539 const struct rtw89_port_reg *p = mac->port_base;
4540 u8 port = rtwvif_link->port;
4544 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif_link->mac_idx);
4555 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4556 const struct rtw89_port_reg *p = mac->port_base;
4559 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg,
4562 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg,
4569 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4570 const struct rtw89_port_reg *p = mac->port_base;
4572 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK,
4579 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4580 const struct rtw89_port_reg *p = mac->port_base;
4583 if (rtwdev->chip->chip_id != RTL8852C)
4586 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT &&
4587 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
4593 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift,
4602 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4603 const struct rtw89_port_reg *p = mac->port_base;
4607 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif_link->port * 4,
4608 rtwvif_link->mac_idx);
4610 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port);
4620 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif_link == rtwvif_src)
4624 offset = offset - offset / 4 + get_random_u32() % (offset / 2);
4641 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA)
4643 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE)
4667 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif_link->mac_id);
4668 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif_link->mac_id);
4670 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif_link->mac_id, false);
4720 u8 port = rtwvif_link->port;
4723 return -EINVAL;
4755 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4756 const struct rtw89_port_reg *p = mac->port_base;
4760 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif_link->mac_idx, RTW89_CMAC_SEL);
4764 tsf_low = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_l);
4765 tsf_high = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_h);
4780 ies = rcu_dereference(bss->ies);
4781 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data,
4782 ies->len);
4784 if (!elem || elem->datalen < 10 ||
4785 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT))
4794 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4795 struct ieee80211_hw *hw = rtwdev->hw;
4804 if (!bss_conf->he_support || vif->type != NL80211_IFTYPE_STATION) {
4809 oper = bss_conf->chanreq.oper;
4810 if (!(oper.chan->flags & IEEE80211_CHAN_RADAR)) {
4817 cfg80211_bss_iter(hw->wiphy, &oper,
4821 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr,
4822 rtwvif_link->mac_idx);
4824 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask);
4826 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask);
4851 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
4853 return band == op->band_type && channel == op->primary_channel;
4861 (const struct rtw89_c2h_scanofld *)skb->data;
4862 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif;
4865 u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf;
4876 rtwvif = rtwvif_link->rtwvif;
4878 if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw))
4881 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL);
4882 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS);
4883 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH);
4884 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN);
4885 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND);
4886 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD);
4887 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX);
4890 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))
4893 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
4894 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF);
4895 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF);
4896 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF);
4899 le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD);
4901 actual_period = le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_PERIOD_V1);
4903 le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1);
4920 ieee80211_stop_queues(rtwdev->hw);
4924 if (rtwdev->scan_info.abort)
4927 if (rtwvif_link && rtwvif->scan_req &&
4928 last_chan < rtwvif->scan_req->n_channels) {
4941 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx,
4942 &rtwdev->scan_info.op_chan);
4944 ieee80211_wake_queues(rtwdev->hw);
4948 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx,
4962 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
4965 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data;
4969 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE);
4970 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI;
4971 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT);
4972 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID);
4974 if (mac_id != rtwvif_link->mac_id)
4983 if (!rtwdev->scanning && !rtwvif->offchan)
5026 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data),
5027 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data),
5028 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data),
5029 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data));
5036 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
5037 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait;
5039 (const struct rtw89_c2h_done_ack *)skb_c2h->data;
5040 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT);
5041 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS);
5042 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC);
5043 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN);
5044 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ);
5094 rtw89_fw_log_dump(rtwdev, c2h->data, len);
5106 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
5108 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data;
5109 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN);
5110 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID);
5111 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP);
5128 (struct rtw89_c2h_tx_duty_rpt *)skb_c2h->data;
5131 err = le32_get_bits(c2h->w2, RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR);
5146 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data);
5147 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data);
5173 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data);
5174 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data);
5175 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data);
5208 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5214 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data);
5220 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data);
5221 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data);
5222 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data);
5223 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data);
5224 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data);
5225 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data);
5230 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low,
5231 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low);
5234 rpt->macid_x, (uintmax_t)rpt->tsf_x_high << 32 | rpt->tsf_x_low,
5235 rpt->macid_y, (uintmax_t)rpt->tsf_y_high << 32 | rpt->tsf_y_low);
5239 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5245 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data);
5246 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data);
5247 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data);
5248 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data);
5249 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data);
5314 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5320 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
5326 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data;
5328 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM,
5329 le32_get_bits(c2h_rpt->w2,
5332 for (i = 0; i < rpt->num; i++) {
5333 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high);
5334 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low);
5336 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low;
5341 i, rpt->tsfs[i]);
5344 i, (uintmax_t)rpt->tsfs[i]);
5354 struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
5355 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt;
5356 struct rtw89_wait_info *wait = &rtw_wow->wait;
5358 (const struct rtw89_c2h_wow_aoac_report *)skb->data;
5361 aoac_rpt->rpt_ver = c2h->rpt_ver;
5362 aoac_rpt->sec_type = c2h->sec_type;
5363 aoac_rpt->key_idx = c2h->key_idx;
5364 aoac_rpt->pattern_idx = c2h->pattern_idx;
5365 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok,
5367 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv));
5368 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count,
5369 sizeof(aoac_rpt->eapol_key_replay_count));
5370 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk));
5371 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv));
5372 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv));
5373 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id);
5374 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn);
5375 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk));
5383 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
5394 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data;
5395 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX);
5396 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS);
5397 tsf_high = le32_to_cpu(c2h_rpt->tsf_high);
5398 tsf_low = le32_to_cpu(c2h_rpt->tsf_low);
5446 "MRC C2H STS RPT: tx null-0 fail\n");
5450 "MRC C2H STS RPT: port func en fail\n");
5484 c2h = (const struct rtw89_c2h_pwr_int_notify *)skb->data;
5485 macid = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_MACID);
5486 ps = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS);
5494 rtwsta = rtwsta_link->rtwsta;
5496 set_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags);
5498 clear_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags);
5562 (const struct rtw89_c2h_scanofld *)skb->data;
5563 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
5568 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS);
5569 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN);
5573 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
5672 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode;
5733 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
5734 struct ieee80211_hw *hw = rtwdev->hw;
5735 u32 rts_threshold = hw->wiphy->rts_threshold;
5739 if (rts_threshold == (u32)-1) {
5750 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx);
5758 if (rtwdev->dbcc_en)
5767 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5772 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning))
5778 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
5809 switch (coex->pta_mode) {
5843 return -EINVAL;
5846 switch (coex->direction) {
5863 return -EINVAL;
5879 switch (coex->pta_mode) {
5891 return -EINVAL;
5903 if (gnt_cfg->band[0].gnt_bt)
5906 if (gnt_cfg->band[0].gnt_bt_sw_en)
5909 if (gnt_cfg->band[0].gnt_wl)
5912 if (gnt_cfg->band[0].gnt_wl_sw_en)
5915 if (gnt_cfg->band[1].gnt_bt)
5918 if (gnt_cfg->band[1].gnt_bt_sw_en)
5921 if (gnt_cfg->band[1].gnt_wl)
5924 if (gnt_cfg->band[1].gnt_wl_sw_en)
5942 if (gnt_cfg->band[0].gnt_bt)
5948 if (gnt_cfg->band[0].gnt_bt_sw_en)
5952 if (gnt_cfg->band[0].gnt_wl)
5956 if (gnt_cfg->band[0].gnt_wl_sw_en)
5960 if (gnt_cfg->band[1].gnt_bt)
5966 if (gnt_cfg->band[1].gnt_bt_sw_en)
5970 if (gnt_cfg->band[1].gnt_wl)
5974 if (gnt_cfg->band[1].gnt_wl_sw_en)
5991 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);
5995 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band);
5996 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) |
5997 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) |
5998 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) |
5999 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) |
6000 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) |
6001 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) |
6002 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) |
6003 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) |
6017 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
6047 struct rtw89_btc *btc = &rtwdev->btc;
6048 struct rtw89_btc_dm *dm = &btc->dm;
6049 struct rtw89_mac_ax_gnt *g = dm->gnt.band;
6062 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt);
6068 const struct rtw89_chip_info *chip = rtwdev->chip;
6071 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A)
6073 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
6097 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
6103 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
6107 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
6113 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
6115 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6117 u32 mask = mac->bfee_ctrl.mask;
6119 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en);
6120 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx);
6121 if (en) {
6122 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
6125 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
6178 u8 mac_idx = rtwvif_link->mac_idx;
6179 u8 port_sel = rtwvif_link->port;
6193 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;
6203 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
6204 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
6205 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC);
6206 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK);
6208 link_sta->vht_cap.cap);
6243 u8 mac_idx = rtwvif_link->mac_idx;
6255 if (link_sta->he_cap.has_he) {
6260 if (link_sta->vht_cap.vht_supported) {
6265 if (link_sta->ht_cap.ht_supported) {
6300 rtw89_mac_init_bfee_ax(rtwdev, rtwvif_link->mac_idx);
6310 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, false);
6321 rtwvif_link = rtwvif->links[conf->link_id];
6325 __func__, conf->link_id);
6329 mac_idx = rtwvif_link->mac_idx;
6333 p = (__le32 *)conf->mu_group.membership;
6341 p = (__le32 *)conf->mu_group.position;
6363 struct rtw89_sta_link *down_rtwsta_link = iter_data->down_rtwsta_link;
6368 int *count = &iter_data->count;
6399 ieee80211_iterate_stations_atomic(rtwdev->hw,
6405 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
6407 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
6412 struct rtw89_traffic_stats *stats = &rtwdev->stats;
6414 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv;
6415 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
6421 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
6423 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW)
6429 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif_link->mac_idx,
6433 if (en == old)
6438 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, en);
6446 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx;
6451 if (rtwsta_link->cctl_tx_time) {
6452 rtwsta_link->ampdu_max_time = (max_tx_time - 512) >> 9;
6475 rtwsta_link->cctl_tx_time = true;
6479 rtwsta_link->cctl_tx_time = false;
6488 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx;
6492 if (rtwsta_link->cctl_tx_time) {
6493 *tx_time = (rtwsta_link->ampdu_max_time + 1) << 9;
6514 rtwsta_link->data_tx_cnt_lmt = tx_retry;
6517 rtwsta_link->cctl_tx_retry_limit = true;
6521 rtwsta_link->cctl_tx_retry_limit = false;
6530 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx;
6534 if (rtwsta_link->cctl_tx_retry_limit) {
6535 *tx_retry = rtwsta_link->data_tx_cnt_lmt;
6551 struct rtw89_vif_link *rtwvif_link, bool en)
6553 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6554 u8 mac_idx = rtwvif_link->mac_idx;
6555 u16 set = mac->muedca_ctrl.mask;
6563 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx);
6564 if (en)
6635 params.mac_band = rtwvif_link->mac_idx;
6636 params.macid = rtwsta_link->mac_id;
6637 params.port = rtwvif_link->port;
6639 params.tf_trs = rtwvif_link->trigger;
6650 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
6651 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6661 rtwvif_link = rtwsta_link->rtwvif_link;
6668 ieee80211_iterate_stations_atomic(rtwdev->hw,
6676 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6685 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50,
6687 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw))
6701 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw))
6713 ret = -EINVAL;
6720 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6721 const struct rtw89_chip_info *chip = rtwdev->chip;
6733 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE);
6740 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw))
6743 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
6787 struct rtw89_fw_secure *sec = &rtwdev->fw.sec;
6789 if (!sec->secure_boot)