Lines Matching defs:val
41 u32 val, enum rtw89_mac_mem_sel sel)
47 rtw89_write32(rtwdev, mac->indir_access_addr, val);
63 u32 val, r_val;
67 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN);
70 val = B_AX_CMAC_EN;
73 val = B_AX_CMAC1_FEN;
78 (val & r_val) != val)
84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val)
94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val);
100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val)
111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA);
119 u32 val;
144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE),
216 u32 val, not_empty, i;
253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG);
255 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK));
257 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK));
258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT);
260 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK));
278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG);
280 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK));
282 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK));
283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1);
285 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK));
960 u32 val = 0;
973 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) |
976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);
988 u32 val;
998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);
999 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK);
1001 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK);
1013 u32 val;
1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) |
1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);
1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK);
1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);
1042 u32 val;
1044 val = rtw89_read32(rtwdev, regs->pub_page_info1);
1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK);
1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK);
1047 val = rtw89_read32(rtwdev, regs->pub_page_info3);
1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK);
1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK);
1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0;
1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0;
1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK);
1062 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK);
1064 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK);
1066 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK);
1068 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK);
1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl);
1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK);
1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK);
1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);
1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK);
1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);
1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK);
1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK);
1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);
1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK);
1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);
1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK);
1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK);
1114 u32 val;
1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
1131 u32 val;
1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) |
1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK);
1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);
1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec,
1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);
1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),
1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1164 u32 val;
1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1169 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN);
1170 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) :
1171 (val & ~B_AX_HCI_FC_CH12_EN);
1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1233 u8 val = 0;
1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk),
1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);
1256 u8 val;
1270 val = rtw89_read8(rtwdev, addr);
1271 val &= ~(cur_cfg->msk);
1272 val |= (cur_cfg->val & cur_cfg->msk);
1274 rtw89_write8(rtwdev, addr, val);
1281 if (cur_cfg->val == PWR_DELAY_US)
1452 u8 val;
1465 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);
1466 if (on && val == PWR_ACT) {
1873 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN;
1877 val |= B_AX_AXIDMA_CLK_EN;
1878 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val);
1880 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val);
1887 u32 val;
1890 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG);
1896 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64,
1900 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128,
1908 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK);
1909 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1911 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val);
1913 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG);
1924 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128,
1928 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256,
1933 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK);
1934 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1936 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val);
1961 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \
1965 val); \
1977 u32 val;
1989 u32 val;
2010 u32 val;
2215 u8 val;
2222 val = rtw89_read8(rtwdev, R_AX_SS_CTRL);
2223 val |= B_AX_SS_EN;
2224 rtw89_write8(rtwdev, R_AX_SS_CTRL, val);
2261 u32 val = 0;
2268 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL);
2270 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP);
2272 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC);
2273 val |= (B_AX_MC_DEC | B_AX_BC_DEC);
2275 val |= B_AX_UC_MGNT_DEC;
2278 val &= ~B_AX_TX_PARTIAL_MODE;
2279 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val);
2282 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC);
2283 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC);
2286 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val);
2340 u32 val, reg;
2350 val = rtw89_read32(rtwdev, reg);
2351 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) |
2353 rtw89_write32(rtwdev, reg, val);
2369 u32 val;
2393 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
2395 if (!val)
2412 u32 val;
2416 val = RX_FLTR_FRAME_DROP;
2419 val = RX_FLTR_FRAME_TO_HOST;
2422 val = RX_FLTR_FRAME_TO_WLCPU;
2443 rtw89_write32(rtwdev, reg, val);
2512 u32 val, reg;
2520 val = rtw89_read32(rtwdev, reg);
2521 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA |
2529 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 |
2535 rtw89_write32(rtwdev, reg, val);
2595 u32 reg, val, sifs;
2603 val = rtw89_read32(rtwdev, reg);
2604 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK;
2605 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK);
2620 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK;
2621 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs);
2622 rtw89_write32(rtwdev, reg, val);
2660 u16 val;
2673 val = rtw89_read16(rtwdev, reg);
2674 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO,
2676 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO,
2679 val |= B_AX_RX_DLK_RST_EN;
2680 rtw89_write16(rtwdev, reg, val);
2713 u32 val, reg;
2721 val = rtw89_read32(rtwdev, reg);
2722 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK);
2723 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK);
2724 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK);
2725 rtw89_write32(rtwdev, reg, val);
2751 u32 val, reg;
2760 val = rtw89_read32(rtwdev, reg);
2761 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K,
2763 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B,
2765 val |= B_AX_HW_CTS2SELF_EN;
2766 rtw89_write32(rtwdev, reg, val);
2769 val = rtw89_read32(rtwdev, reg);
2770 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK);
2771 val &= ~B_AX_PTCL_TX_ARB_TO_MODE;
2772 rtw89_write32(rtwdev, reg, val);
3085 u16 val;
3096 val = rtw89_read16(rtwdev, reg);
3097 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
3098 rtw89_write16(rtwdev, reg, val);
3107 u32 val;
3114 val = rtw89_read32(rtwdev, reg);
3115 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
3116 rtw89_write32(rtwdev, reg, val);
3230 u32 val, reg;
3234 val = buf_len;
3235 val |= B_AX_WD_BUF_REQ_EXEC;
3236 rtw89_write32(rtwdev, reg, val);
3240 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE,
3245 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val);
3255 u32 val, cmd_type, reg;
3261 val = 0;
3262 val = u32_replace_bits(val, ctrl_para->start_pktid,
3264 val = u32_replace_bits(val, ctrl_para->end_pktid,
3266 rtw89_write32(rtwdev, reg, val);
3269 val = 0;
3270 val = u32_replace_bits(val, ctrl_para->src_pid,
3272 val = u32_replace_bits(val, ctrl_para->src_qid,
3274 val = u32_replace_bits(val, ctrl_para->dst_pid,
3276 val = u32_replace_bits(val, ctrl_para->dst_qid,
3278 rtw89_write32(rtwdev, reg, val);
3281 val = 0;
3282 val = u32_replace_bits(val, cmd_type,
3284 val = u32_replace_bits(val, ctrl_para->macid,
3286 val = u32_replace_bits(val, ctrl_para->pkt_num,
3288 val |= B_AX_WD_CPUQ_OP_EXEC;
3289 rtw89_write32(rtwdev, reg, val);
3293 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE,
3300 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val);
3377 u8 val;
3385 ret = read_poll_timeout(rtw89_read8, val,
3386 (val & B_AX_PTCL_TX_ON_STAT) == 0,
3859 u32 val;
3874 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL);
3875 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
3876 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE,
3880 val |= B_AX_WCPU_FWDL_EN;
3882 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val);
3906 u32 val;
3909 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN |
3912 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN |
3914 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val);
3920 u32 val;
3923 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN;
3925 val = B_AX_DISPATCHER_CLK_EN;
3926 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val);
3931 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1);
3932 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST);
3933 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) |
3935 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val);
4167 u32 val;
4177 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000,
4542 u32 val;
4545 val = rtw89_read32(rtwdev, reg);
4546 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port));
4548 val &= ~BIT(0);
4549 rtw89_write32(rtwdev, reg, val);
4581 u16 val;
4590 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) |
4594 B_AX_TBTT_SHIFT_OFST_MASK, val);
4604 u32 val, reg;
4606 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu);
4611 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val);
5779 u8 val;
5811 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
5812 val &= ~B_AX_BTMODE_MASK;
5813 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3);
5814 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
5816 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE);
5817 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);
5819 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5);
5820 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK;
5821 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE);
5822 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val);
5825 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
5826 val &= ~B_AX_BTMODE_MASK;
5827 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2);
5828 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
5848 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
5849 val = (val & ~BIT(2)) | BIT(1);
5850 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
5853 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
5854 val = val | BIT(1) | BIT(0);
5855 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
5858 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
5859 val = val & ~(BIT(2) | BIT(1));
5860 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
5901 u32 val = 0, ret;
5904 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL;
5907 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL;
5910 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL;
5913 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL;
5916 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL;
5919 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL;
5922 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL;
5925 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL;
5927 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val);
5940 u32 val = 0;
5943 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL |
5946 val |= B_AX_WL_ACT_VAL;
5949 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL |
5953 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL |
5957 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL |
5961 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL |
5964 val |= B_AX_WL_ACT_VAL;
5967 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL |
5971 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL |
5975 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL |
5978 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val);
5988 u16 val;
5996 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) |
6005 rtw89_write16(rtwdev, reg, val);
6010 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)
6021 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val);
6022 val = B_AX_TOGGLE |
6023 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) |
6025 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val);
6036 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);
6038 val = wl ? val | BIT(2) : val & ~BIT(2);
6039 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val);
6069 u8 val = 0;
6074 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3,
6077 return !!val;
6183 u16 val;
6219 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) |
6232 rtw89_write16(rtwdev, reg, val);
6573 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
6579 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) |
6588 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
6589 offset, val, mask);
6597 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
6616 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1);
6767 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL);
6769 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val);
6777 u8 val;
6779 return read_poll_timeout_atomic(rtw89_read8, val, val & check,