Lines Matching +full:8 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
55 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_TX_NUM GENMASK(15, 8)
62 #define RTW89_C2HREG_PHYCAP_P1_W2_B1_QAM GENMASK(15, 8)
66 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)
70 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)
74 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)
80 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)
84 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)
88 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)
98 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
107 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
257 #define RTW89_DEFAULT_CQM_THOLD -70
281 #define FWDL_SECTION_CHKSUM_LEN 8
333 #define RTW89_SCANOFLD_MAX_SSID 8
342 ((RTW89_H2C_MAX_SIZE / (size)) - RTW89_SCAN_LIST_GUARD)
421 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
424 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
425 #define RTW89_H2C_RA_W0_DCM BIT(16)
426 #define RTW89_H2C_RA_W0_ER BIT(17)
428 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
429 #define RTW89_H2C_RA_W0_SGI BIT(21)
430 #define RTW89_H2C_RA_W0_LDPC BIT(22)
431 #define RTW89_H2C_RA_W0_STBC BIT(23)
434 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
435 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
438 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
440 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
441 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
442 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
443 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
457 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
468 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_SEC_OFFSET()
483 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); in RTW89_SET_FWCMD_SEC_EXT_KEY()
488 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); in RTW89_SET_FWCMD_SEC_SPP_MODE()
518 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); in RTW89_SET_EDCA_BAND()
523 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); in RTW89_SET_EDCA_WMM()
537 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
542 #define FWDL_SECURITY_CHKSUM_LEN 8
566 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
567 #define FWSECTION_HDR_W1_REDL BIT(29)
584 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
591 #define FW_HDR_W4_DATE GENMASK(15, 8)
595 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
597 #define FW_HDR_W7_DYN_HDR BIT(16)
612 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
613 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
636 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
643 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
648 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
649 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
651 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
659 #define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
662 u8 signature[8]; /* equal to mss_signature[] */
706 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); in SET_CTRL_INFO_OPERATION()
708 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
711 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); in SET_CMC_TBL_DATARATE()
713 GENMASK(8, 0)); in SET_CMC_TBL_DATARATE()
715 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
718 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); in SET_CMC_TBL_FORCE_TXOP()
720 BIT(9)); in SET_CMC_TBL_FORCE_TXOP()
736 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
739 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); in SET_CMC_TBL_DARF_TC_INDEX()
741 BIT(15)); in SET_CMC_TBL_DARF_TC_INDEX()
750 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
753 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); in SET_CMC_TBL_ACQ_RPT_EN()
755 BIT(20)); in SET_CMC_TBL_ACQ_RPT_EN()
757 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
760 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); in SET_CMC_TBL_MGQ_RPT_EN()
762 BIT(21)); in SET_CMC_TBL_MGQ_RPT_EN()
764 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
767 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); in SET_CMC_TBL_ULQ_RPT_EN()
769 BIT(22)); in SET_CMC_TBL_ULQ_RPT_EN()
771 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
774 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); in SET_CMC_TBL_TWTQ_RPT_EN()
776 BIT(23)); in SET_CMC_TBL_TWTQ_RPT_EN()
778 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
781 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); in SET_CMC_TBL_DISRTSFB()
783 BIT(25)); in SET_CMC_TBL_DISRTSFB()
785 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
788 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); in SET_CMC_TBL_DISDATAFB()
790 BIT(26)); in SET_CMC_TBL_DISDATAFB()
792 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
795 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); in SET_CMC_TBL_TRYRATE()
797 BIT(27)); in SET_CMC_TBL_TRYRATE()
806 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
809 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); in SET_CMC_TBL_DATA_RTY_LOWEST_RATE()
811 GENMASK(8, 0)); in SET_CMC_TBL_DATA_RTY_LOWEST_RATE()
813 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
816 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); in SET_CMC_TBL_AMPDU_TIME_SEL()
818 BIT(9)); in SET_CMC_TBL_AMPDU_TIME_SEL()
820 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
823 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); in SET_CMC_TBL_AMPDU_LEN_SEL()
825 BIT(10)); in SET_CMC_TBL_AMPDU_LEN_SEL()
827 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
830 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); in SET_CMC_TBL_RTS_TXCNT_LMT_SEL()
832 BIT(11)); in SET_CMC_TBL_RTS_TXCNT_LMT_SEL()
841 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
848 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
851 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); in SET_CMC_TBL_VCS_STBC()
853 BIT(27)); in SET_CMC_TBL_VCS_STBC()
869 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
872 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); in SET_CMC_TBL_DATA_TXCNT_LMT_SEL()
874 BIT(6)); in SET_CMC_TBL_DATA_TXCNT_LMT_SEL()
876 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
879 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); in SET_CMC_TBL_MAX_AGG_NUM_SEL()
881 BIT(7)); in SET_CMC_TBL_MAX_AGG_NUM_SEL()
883 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
886 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); in SET_CMC_TBL_RTS_EN()
888 BIT(8)); in SET_CMC_TBL_RTS_EN()
890 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
893 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); in SET_CMC_TBL_CTS2SELF_EN()
895 BIT(9)); in SET_CMC_TBL_CTS2SELF_EN()
904 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
907 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); in SET_CMC_TBL_HW_RTS_EN()
909 BIT(12)); in SET_CMC_TBL_HW_RTS_EN()
925 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
928 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); in SET_CMC_TBL_UL_MU_DIS()
930 BIT(27)); in SET_CMC_TBL_UL_MU_DIS()
949 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); in SET_CMC_TBL_BA_BMAP()
951 GENMASK(9, 8)); in SET_CMC_TBL_BA_BMAP()
995 #define SET_CMC_TBL_MASK_BMC BIT(0)
998 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); in SET_CMC_TBL_BMC()
1000 BIT(3)); in SET_CMC_TBL_BMC()
1009 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
1012 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); in SET_CMC_TBL_NAVUSEHDR()
1014 BIT(8)); in SET_CMC_TBL_NAVUSEHDR()
1023 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
1026 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); in SET_CMC_TBL_DATA_DCM()
1028 BIT(12)); in SET_CMC_TBL_DATA_DCM()
1030 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
1033 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); in SET_CMC_TBL_DATA_ER()
1035 BIT(13)); in SET_CMC_TBL_DATA_ER()
1037 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
1040 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); in SET_CMC_TBL_DATA_LDPC()
1042 BIT(14)); in SET_CMC_TBL_DATA_LDPC()
1044 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
1047 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); in SET_CMC_TBL_DATA_STBC()
1049 BIT(15)); in SET_CMC_TBL_DATA_STBC()
1051 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
1054 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); in SET_CMC_TBL_A_CTRL_BQR()
1056 BIT(16)); in SET_CMC_TBL_A_CTRL_BQR()
1058 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
1061 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); in SET_CMC_TBL_A_CTRL_UPH()
1063 BIT(17)); in SET_CMC_TBL_A_CTRL_UPH()
1065 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
1068 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); in SET_CMC_TBL_A_CTRL_BSR()
1070 BIT(18)); in SET_CMC_TBL_A_CTRL_BSR()
1072 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
1075 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); in SET_CMC_TBL_A_CTRL_CAS()
1077 BIT(19)); in SET_CMC_TBL_A_CTRL_CAS()
1079 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
1082 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); in SET_CMC_TBL_DATA_BW_ER()
1084 BIT(20)); in SET_CMC_TBL_DATA_BW_ER()
1086 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
1089 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); in SET_CMC_TBL_LSIG_TXOP_EN()
1091 BIT(21)); in SET_CMC_TBL_LSIG_TXOP_EN()
1093 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
1096 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); in SET_CMC_TBL_CTRL_CNT_VLD()
1098 BIT(27)); in SET_CMC_TBL_CTRL_CNT_VLD()
1107 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
1110 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); in SET_CMC_TBL_RESP_REF_RATE()
1112 GENMASK(8, 0)); in SET_CMC_TBL_RESP_REF_RATE()
1114 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
1117 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); in SET_CMC_TBL_ALL_ACK_SUPPORT()
1119 BIT(12)); in SET_CMC_TBL_ALL_ACK_SUPPORT()
1121 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
1124 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); in SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT()
1126 BIT(13)); in SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT()
1163 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
1166 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); in SET_CMC_TBL_ANTSEL_A()
1168 BIT(28)); in SET_CMC_TBL_ANTSEL_A()
1170 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
1173 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); in SET_CMC_TBL_ANTSEL_B()
1175 BIT(29)); in SET_CMC_TBL_ANTSEL_B()
1177 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
1180 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); in SET_CMC_TBL_ANTSEL_C()
1182 BIT(30)); in SET_CMC_TBL_ANTSEL_C()
1184 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
1187 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); in SET_CMC_TBL_ANTSEL_D()
1189 BIT(31)); in SET_CMC_TBL_ANTSEL_D()
1228 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
1231 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); in SET_CMC_TBL_PAID()
1233 GENMASK(16, 8)); in SET_CMC_TBL_PAID()
1235 #define SET_CMC_TBL_MASK_ULDL BIT(0)
1238 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); in SET_CMC_TBL_ULDL()
1240 BIT(17)); in SET_CMC_TBL_ULDL()
1279 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); in SET_CMC_TBL_NC()
1286 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); in SET_CMC_TBL_NR()
1293 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); in SET_CMC_TBL_NG()
1300 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); in SET_CMC_TBL_CB()
1302 GENMASK(9, 8)); in SET_CMC_TBL_CB()
1307 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); in SET_CMC_TBL_CS()
1311 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
1314 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); in SET_CMC_TBL_CSI_TXBF_EN()
1316 BIT(12)); in SET_CMC_TBL_CSI_TXBF_EN()
1318 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
1321 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); in SET_CMC_TBL_CSI_STBC_EN()
1323 BIT(13)); in SET_CMC_TBL_CSI_STBC_EN()
1325 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
1328 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); in SET_CMC_TBL_CSI_LDPC_EN()
1330 BIT(14)); in SET_CMC_TBL_CSI_LDPC_EN()
1332 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
1335 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); in SET_CMC_TBL_CSI_PARA_EN()
1337 BIT(15)); in SET_CMC_TBL_CSI_PARA_EN()
1339 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
1342 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); in SET_CMC_TBL_CSI_FIX_RATE()
1349 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); in SET_CMC_TBL_CSI_GI_LTF()
1356 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28)); in SET_CMC_TBL_NOMINAL_PKT_PADDING160()
1364 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); in SET_CMC_TBL_CSI_BW()
1406 #define CCTLINFO_G7_C0_OP BIT(7)
1410 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1412 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1413 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1414 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1415 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1416 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1417 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1418 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1419 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1420 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1429 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1430 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1431 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1432 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1434 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1436 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1438 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1442 #define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1443 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1445 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1450 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1451 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1452 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1453 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1456 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1458 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1459 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1460 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1461 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1462 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1463 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1464 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1471 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1478 #define CCTLINFO_G7_W6_ULDL BIT(31)
1479 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1483 #define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1485 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1486 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1487 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1491 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1492 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1493 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1494 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1495 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1496 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1497 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1498 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1499 #define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1519 #define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1523 #define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1527 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1530 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1533 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1534 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1535 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1536 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1573 #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1577 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1582 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1585 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1588 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1589 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1590 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1591 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1603 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1610 #define RTW89_H2C_ROLE_MAINTAIN_W0_SELF_ROLE GENMASK(9, 8)
1634 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1635 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1637 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1638 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1647 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1649 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1652 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1653 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1654 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1658 #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1664 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1673 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); in SET_GENERAL_PKT_PROBRSP_ID()
1693 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); in SET_GENERAL_PKT_CTS2SELF_ID()
1703 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); in SET_LOG_CFG_PATH()
1721 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1722 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1725 #define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1729 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1730 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1738 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1739 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1741 #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1745 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1746 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1747 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1756 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1765 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); in SET_LPS_PARM_PSMODE()
1785 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); in SET_LPS_PARM_VOUAPSD()
1790 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); in SET_LPS_PARM_VIUAPSD()
1795 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); in SET_LPS_PARM_BEUAPSD()
1800 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); in SET_LPS_PARM_BKUAPSD()
1805 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); in SET_LPS_PARM_LASTRPWM()
1851 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_PKT_DROP_MACID()
1871 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS()
1901 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); in RTW89_SET_KEEP_ALIVE_PKT_NULL_ID()
1916 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); in RTW89_SET_DISCONNECT_DETECT_ENABLE()
1921 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); in RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN()
1926 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); in RTW89_SET_DISCONNECT_DETECT_DISCONNECT()
1931 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); in RTW89_SET_DISCONNECT_DETECT_MAC_ID()
1954 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1955 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1956 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1957 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1958 #define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)
1976 #define RTW89_H2C_NLO_W0_ENABLE BIT(0)
1977 #define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
1982 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); in RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE()
1987 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); in RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE()
1992 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); in RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE()
1997 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); in RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE()
2002 le32p_replace_bits((__le32 *)h2c, val, BIT(4)); in RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE()
2007 le32p_replace_bits((__le32 *)h2c, val, BIT(5)); in RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE()
2012 le32p_replace_bits((__le32 *)h2c, val, BIT(6)); in RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE()
2017 le32p_replace_bits((__le32 *)h2c, val, BIT(7)); in RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE()
2027 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); in RTW89_SET_WOW_CAM_UPD_R_W()
2062 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22)); in RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH()
2067 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23)); in RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR()
2072 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24)); in RTW89_SET_WOW_CAM_UPD_UC()
2077 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25)); in RTW89_SET_WOW_CAM_UPD_MC()
2082 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26)); in RTW89_SET_WOW_CAM_UPD_BC()
2087 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31)); in RTW89_SET_WOW_CAM_UPD_VALID()
2096 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2097 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2098 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2099 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2100 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2104 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)
2112 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2113 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2282 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2283 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2287 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2288 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2289 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2292 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2293 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2294 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2295 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2296 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2315 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ROLE_NONE()
2320 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); in RTW89_SET_FWCMD_CXROLE_ROLE_STA()
2325 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); in RTW89_SET_FWCMD_CXROLE_ROLE_AP()
2330 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); in RTW89_SET_FWCMD_CXROLE_ROLE_VAP()
2335 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); in RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC()
2340 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); in RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER()
2345 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); in RTW89_SET_FWCMD_CXROLE_ROLE_MESH()
2350 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); in RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR()
2355 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); in RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV()
2360 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); in RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC()
2365 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); in RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO()
2370 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); in RTW89_SET_FWCMD_CXROLE_ROLE_NAN()
2375 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED()
2385 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); in RTW89_SET_FWCMD_CXROLE_ACT_PHY()
2390 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); in RTW89_SET_FWCMD_CXROLE_ACT_NOA()
2400 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS()
2410 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXROLE_ACT_ROLE()
2445 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2()
2455 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); in RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2()
2460 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); in RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2()
2470 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2()
2480 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2()
2505 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0)); in RTW89_SET_FWCMD_CXROLE_DBCC_EN()
2510 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1)); in RTW89_SET_FWCMD_CXROLE_DBCC_CHG()
2515 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2)); in RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY()
2520 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4)); in RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG()
2525 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); in RTW89_SET_FWCMD_CXCTRL_MANUAL()
2530 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); in RTW89_SET_FWCMD_CXCTRL_IGNORE_BT()
2535 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); in RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN()
2575 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_CXTRX_BTTXPWR()
2645 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); in RTW89_SET_FWCMD_CXRFK_BAND()
2660 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8)); in RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP()
2679 #define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2684 #define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2685 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2686 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2689 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2690 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2691 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2692 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2693 #define RTW89_H2C_CHINFO_W1_MACID_TX BIT(29)
2695 #define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2699 #define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2716 #define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2721 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2722 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2723 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2724 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2726 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2730 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
2733 #define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
2737 #define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
2762 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2763 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2776 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2778 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2781 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2782 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2783 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2786 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2801 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
2816 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2819 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
2825 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
2827 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_TXBCN BIT(19)
2829 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
2852 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2853 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2854 #define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
2857 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
2859 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
2865 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
2869 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
2875 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8)
2878 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
2886 #define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
2902 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8)); in RTW89_SET_FWCMD_P2P_P2PID()
2917 le32p_replace_bits((__le32 *)cmd, val, BIT(20)); in RTW89_SET_FWCMD_P2P_TYPE()
2922 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); in RTW89_SET_FWCMD_P2P_ALL_SLEP()
2952 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8)); in RTW89_SET_FWCMD_NOA_CTWINDOW()
2957 le32p_replace_bits((__le32 *)cmd, val, BIT(0)); in RTW89_SET_FWCMD_TSF32_TOGL_BAND()
2962 le32p_replace_bits((__le32 *)cmd, val, BIT(1)); in RTW89_SET_FWCMD_TSF32_TOGL_EN()
3013 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0()
3043 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8)); in RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL()
3048 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9)); in RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY()
3053 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10)); in RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH()
3068 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18)); in RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G()
3073 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19)); in RTW89_SET_FWCMD_ADD_MCC_PTA_EN()
3078 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20)); in RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS()
3093 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0)); in RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN()
3098 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM()
3121 u32 macid: 8;
3133 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); in RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP()
3153 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); in RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN()
3178 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8)); in RTW89_SET_FWCMD_STOP_MCC_GROUP()
3183 le32p_replace_bits((__le32 *)cmd, val, BIT(10)); in RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS()
3193 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); in RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS()
3216 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X()
3231 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID()
3252 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE()
3269 u32 start_macid: 8;
3270 u32 macid_x: 8;
3271 u32 macid_y: 8;
3286 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); in RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP()
3292 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID()
3366 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3390 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3391 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3392 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3393 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3395 #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3398 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3399 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3402 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3412 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3415 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3428 #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3429 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3451 #define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3458 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3459 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3460 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3461 #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3500 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3517 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3518 #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3543 #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3544 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3556 #define RTW89_H2C_AP_INFO_W0_PWR_INT_EN BIT(0)
3558 #define RTW89_C2H_HEADER_LEN 8
3567 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3582 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr)); in RTW89_SKB_C2H_CB()
3584 rtw89_static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr)); in RTW89_SKB_C2H_CB()
3587 return (struct rtw89_fw_c2h_attr *)skb->cb; in RTW89_SKB_C2H_CB()
3598 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3608 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3627 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3639 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3651 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3653 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3656 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3657 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3673 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3674 * HT-new: [6:5]: NA, [4:0]: MCS
3689 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3712 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3714 #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
3723 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3730 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3750 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3767 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3829 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3847 u8 ptk_tx_iv[8];
3848 u8 eapol_key_replay_count[8];
3850 u8 ptk_rx_iv[8];
3851 u8 gtk_rx_iv[4][8];
3861 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3869 #define RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS BIT(16)
3878 #define RTW89_H2C_TX_DUTY_W1_STOP BIT(0)
3884 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3885 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3886 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3889 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_L4 GENMASK(11, 8)
3900 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3908 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3933 u8 rsvd1[8];
3954 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
3978 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3979 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3980 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3981 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3982 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3983 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3984 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3988 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3989 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
3992 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3993 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3994 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3995 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3996 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3999 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
4000 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
4001 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
4002 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
4003 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
4004 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
4040 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
4041 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
4059 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
4060 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
4061 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
4062 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
4064 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
4065 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
4066 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
4067 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
4069 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
4070 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
4071 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
4072 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
4073 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
4074 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
4075 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
4076 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
4087 u8 priv[8];
4134 if (compat->mfw_hdr.sig == RTW89_MFW_SIG) in rtw89_compat_fw_hdr_ver_code()
4135 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr); in rtw89_compat_fw_hdr_ver_code()
4137 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr); in rtw89_compat_fw_hdr_ver_code()
4146 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format); in rtw89_fw_get_filename()
4159 #define H2C_HEADER_LEN 8
4162 #define H2C_HDR_FUNC GENMASK(15, 8)
4166 #define H2C_HDR_REC_ACK BIT(14)
4167 #define H2C_HDR_DONE_ACK BIT(15)
4173 /* CLASS 5 - FW STATUS TEST */
4179 /* CLASS 0 - FW INFO */
4184 /* CLASS 1 - WOW */
4206 /* CLASS 2 - PS */
4222 /* CLASS 3 - FW download */
4226 /* CLASS 5 - Frame Exchange */
4236 /* CLASS 6 - Address CAM */
4240 /* CLASS 8 - Media Status Report */
4246 /* CLASS 9 - FW offload */
4282 /* CLASS 10 - Security CAM */
4286 /* CLASS 12 - BA CAM */
4292 /* CLASS 14 - MCC */
4311 /* CLASS 20 - MLO */
4331 /* CLASS 24 - MRC */
4352 /* CLASS 36 - AP */
4407 #define RTW89_H2C_MCC_DIG_W0_DM_EN BIT(8)
4409 #define RTW89_H2C_MCC_DIG_W0_SET BIT(11)
4410 #define RTW89_H2C_MCC_DIG_W0_PHY0_EN BIT(12)
4411 #define RTW89_H2C_MCC_DIG_W0_PHY1_EN BIT(13)
4415 #define RTW89_H2C_MCC_DIG_W1_ADDR_MSB GENMASK(15, 8)
4419 #define RTW89_H2C_MCC_DIG_W2_VAL_MSB GENMASK(15, 8)
4702 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
4706 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
4971 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_fw_h2c_init_ba_cam()
4973 if (chip->bacam_ver == RTW89_BACAM_V0_EXT) in rtw89_fw_h2c_init_ba_cam()
4981 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_default_cmac_tbl()
4983 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); in rtw89_chip_h2c_default_cmac_tbl()
4990 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_default_dmac_tbl()
4992 if (chip->ops->h2c_default_dmac_tbl) in rtw89_chip_h2c_default_dmac_tbl()
4993 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link); in rtw89_chip_h2c_default_dmac_tbl()
5001 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_update_beacon()
5003 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link); in rtw89_chip_h2c_update_beacon()
5010 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_assoc_cmac_tbl()
5012 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); in rtw89_chip_h2c_assoc_cmac_tbl()
5020 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_ampdu_link_cmac_tbl()
5022 if (chip->ops->h2c_ampdu_cmac_tbl) in rtw89_chip_h2c_ampdu_link_cmac_tbl()
5023 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link, in rtw89_chip_h2c_ampdu_link_cmac_tbl()
5039 rtwvif_link = rtwsta_link->rtwvif_link; in rtw89_chip_h2c_ampdu_cmac_tbl()
5053 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_txtime_cmac_tbl()
5055 return chip->ops->h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); in rtw89_chip_h2c_txtime_cmac_tbl()
5063 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_punctured_cmac_tbl()
5065 if (!chip->ops->h2c_punctured_cmac_tbl) in rtw89_chip_h2c_punctured_cmac_tbl()
5068 return chip->ops->h2c_punctured_cmac_tbl(rtwdev, rtwvif_link, punctured); in rtw89_chip_h2c_punctured_cmac_tbl()
5075 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_chip_h2c_ba_cam()
5082 rtwvif_link = rtwsta_link->rtwvif_link; in rtw89_chip_h2c_ba_cam()
5083 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link, in rtw89_chip_h2c_ba_cam()