Lines Matching +full:24 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
50 #define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24)
53 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24)
57 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24)
68 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
72 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
76 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
78 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
82 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
86 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
104 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
249 #define RTW89_DEFAULT_CQM_THOLD -70
332 ((RTW89_H2C_MAX_SIZE / (size)) - RTW89_SCAN_LIST_GUARD)
410 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
414 #define RTW89_H2C_RA_W0_DCM BIT(16)
415 #define RTW89_H2C_RA_W0_ER BIT(17)
417 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
418 #define RTW89_H2C_RA_W0_SGI BIT(21)
419 #define RTW89_H2C_RA_W0_LDPC BIT(22)
420 #define RTW89_H2C_RA_W0_STBC BIT(23)
421 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
423 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
424 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
427 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
429 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
430 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
431 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
432 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
435 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
472 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
477 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
507 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
512 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
552 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
553 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
555 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
556 #define FWSECTION_HDR_W1_REDL BIT(29)
575 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
578 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
582 #define FW_HDR_W4_MIN GENMASK(31, 24)
586 #define FW_HDR_W7_DYN_HDR BIT(16)
588 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
598 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
599 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
601 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
602 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
606 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
627 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
630 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
634 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
638 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
640 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
683 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
692 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
695 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
697 BIT(9));
713 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
716 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
718 BIT(15));
727 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
730 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
732 BIT(20));
734 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
737 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
739 BIT(21));
741 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
744 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
746 BIT(22));
748 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
751 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
753 BIT(23));
755 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
758 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
760 BIT(25));
762 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
765 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
767 BIT(26));
769 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
772 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
774 BIT(27));
790 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
793 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
795 BIT(9));
797 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
800 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
802 BIT(10));
804 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
807 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
809 BIT(11));
821 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
823 GENMASK(24, 16));
825 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
828 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
830 BIT(27));
846 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
849 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
851 BIT(6));
853 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
856 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
858 BIT(7));
860 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
863 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
865 BIT(8));
867 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
870 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
872 BIT(9));
881 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
884 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
886 BIT(12));
902 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
905 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
907 BIT(27));
947 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
949 GENMASK(24, 22));
972 #define SET_CMC_TBL_MASK_BMC BIT(0)
975 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
977 BIT(3));
986 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
989 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
991 BIT(8));
1000 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
1003 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
1005 BIT(12));
1007 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
1010 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
1012 BIT(13));
1014 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
1017 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
1019 BIT(14));
1021 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
1024 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1026 BIT(15));
1028 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
1031 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1033 BIT(16));
1035 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
1038 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1040 BIT(17));
1042 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
1045 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1047 BIT(18));
1049 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
1052 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1054 BIT(19));
1056 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
1059 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1061 BIT(20));
1063 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
1066 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1068 BIT(21));
1070 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
1073 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1075 BIT(27));
1091 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
1094 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1096 BIT(12));
1098 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
1101 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1103 BIT(13));
1129 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1131 GENMASK(25, 24));
1140 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
1143 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1145 BIT(28));
1147 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
1150 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1152 BIT(29));
1154 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
1157 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1159 BIT(30));
1161 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
1164 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1166 BIT(31));
1212 #define SET_CMC_TBL_MASK_ULDL BIT(0)
1215 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1217 BIT(17));
1242 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1244 GENMASK(27, 24));
1288 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
1291 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1293 BIT(12));
1295 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
1298 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1300 BIT(13));
1302 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
1305 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1307 BIT(14));
1309 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
1312 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1314 BIT(15));
1319 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1321 GENMASK(24, 16));
1383 #define CCTLINFO_G7_C0_OP BIT(7)
1387 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1389 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1390 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1391 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1392 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1393 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1394 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1395 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1396 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1397 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1406 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1407 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1408 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1409 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1411 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1413 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1415 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1420 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1422 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1425 #define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1427 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1428 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1429 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1430 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1433 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1435 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1436 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1437 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1438 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1439 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1440 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1441 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1451 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1455 #define CCTLINFO_G7_W6_ULDL BIT(31)
1456 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1462 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1463 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1464 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1468 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1469 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1470 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1471 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1472 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1473 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1474 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1475 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1482 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1498 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1504 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1510 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1511 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1512 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1513 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1552 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1558 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1559 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1565 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1566 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1567 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1568 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1580 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1619 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1620 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1622 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1623 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1628 #define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1632 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1634 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1635 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1636 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1637 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1647 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1666 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1704 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1705 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1712 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1713 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1721 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1722 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1728 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1729 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1730 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1731 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1739 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1763 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1768 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1773 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1778 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1783 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1839 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1884 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1889 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1894 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1899 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1904 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1919 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1932 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1933 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1934 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1935 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1938 #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
1950 u8 rsvd3[24];
1954 #define RTW89_H2C_NLO_W0_ENABLE BIT(0)
1955 #define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
1956 #define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
1960 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1965 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1970 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1975 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
1980 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
1985 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
1990 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
1995 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
2000 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2005 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2040 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2045 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2050 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2055 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2060 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2065 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2074 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2075 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2076 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2077 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2078 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2080 #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2090 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2091 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2093 #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2255 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2256 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2260 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2261 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2262 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2265 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2266 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2267 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2268 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2269 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2288 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2293 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2298 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2303 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2308 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2313 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2318 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2323 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2328 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2333 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2338 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2343 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2348 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2358 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2363 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2373 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2418 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2428 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2433 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2443 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2478 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2483 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2493 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2498 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2503 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2508 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2654 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2658 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2659 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2662 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2663 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2664 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2665 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2669 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2673 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2690 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2693 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2694 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2695 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2696 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2698 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2700 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2707 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2711 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2734 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2735 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2750 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2753 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2754 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2755 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2760 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2773 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
2787 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2788 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
2794 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
2801 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
2822 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2823 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2825 #define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
2827 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
2833 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
2837 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
2856 #define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
2880 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2885 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2920 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2925 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2986 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3006 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
3011 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
3016 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
3031 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
3036 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
3041 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
3056 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
3096 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3116 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3121 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3146 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3156 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3225 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3249 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3265 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3329 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3353 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3354 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3355 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3356 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3361 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3362 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3363 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3375 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3376 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3392 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3421 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3422 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3423 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3463 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3480 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3507 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3519 #define RTW89_H2C_AP_INFO_W0_PWR_INT_EN BIT(0)
3543 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3545 rtw89_static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3548 return (struct rtw89_fw_c2h_attr *)skb->cb;
3561 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3587 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3611 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3616 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3617 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3620 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3621 * HT-new: [6:5]: NA, [4:0]: MCS
3655 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3658 #define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
3659 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3789 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3797 #define RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS BIT(16)
3806 #define RTW89_H2C_TX_DUTY_W1_STOP BIT(0)
3812 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3813 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3814 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3819 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3898 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3899 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3900 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3901 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3902 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3903 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3904 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3908 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3909 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
3912 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3913 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3914 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3915 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3916 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3919 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
3920 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3921 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3922 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3923 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3924 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3970 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
3971 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
3972 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
3973 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
3975 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
3976 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
3977 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
3978 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
3980 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
3981 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
3982 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
3983 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
3984 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
3985 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
3986 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
3987 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
4044 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
4045 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
4047 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
4056 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
4067 #define H2C_SEC_CAM_LEN 24
4074 #define H2C_HDR_H2C_SEQ GENMASK(31, 24)
4076 #define H2C_HDR_REC_ACK BIT(14)
4077 #define H2C_HDR_DONE_ACK BIT(15)
4083 /* CLASS 5 - FW STATUS TEST */
4089 /* CLASS 0 - FW INFO */
4094 /* CLASS 1 - WOW */
4116 /* CLASS 2 - PS */
4132 /* CLASS 3 - FW download */
4136 /* CLASS 5 - Frame Exchange */
4146 /* CLASS 6 - Address CAM */
4150 /* CLASS 8 - Media Status Report */
4156 /* CLASS 9 - FW offload */
4192 /* CLASS 10 - Security CAM */
4196 /* CLASS 12 - BA CAM */
4202 /* CLASS 14 - MCC */
4221 /* CLASS 24 - MRC */
4242 /* CLASS 36 - AP */
4786 const struct rtw89_chip_info *chip = rtwdev->chip;
4788 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
4796 const struct rtw89_chip_info *chip = rtwdev->chip;
4798 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4805 const struct rtw89_chip_info *chip = rtwdev->chip;
4807 if (chip->ops->h2c_default_dmac_tbl)
4808 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4816 const struct rtw89_chip_info *chip = rtwdev->chip;
4818 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link);
4825 const struct rtw89_chip_info *chip = rtwdev->chip;
4827 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4835 const struct rtw89_chip_info *chip = rtwdev->chip;
4837 if (chip->ops->h2c_ampdu_cmac_tbl)
4838 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link,
4854 rtwvif_link = rtwsta_link->rtwvif_link;
4868 const struct rtw89_chip_info *chip = rtwdev->chip;
4875 rtwvif_link = rtwsta_link->rtwvif_link;
4876 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link,