Lines Matching +full:pwr +full:- +full:sel
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
65 u32 h2c_desc_size = rtwdev->chip->h2c_desc_size;
74 memset(skb->data, 0, len);
91 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
95 ret = read_poll_timeout_atomic(mac->fwdl_get_status, val,
102 return -EINVAL;
106 return -EINVAL;
110 return -EINVAL;
114 return -EBUSY;
118 set_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
137 return -EINVAL;
139 info->section_num = le32_get_bits(fw_hdr->w6, FW_HDR_W6_SEC_NUM);
140 base_hdr_len = struct_size(fw_hdr, sections, info->section_num);
141 info->dynamic_hdr_en = le32_get_bits(fw_hdr->w7, FW_HDR_W7_DYN_HDR);
143 if (info->dynamic_hdr_en) {
144 info->hdr_len = le32_get_bits(fw_hdr->w3, FW_HDR_W3_LEN);
145 info->dynamic_hdr_len = info->hdr_len - base_hdr_len;
147 if (le32_to_cpu(fwdynhdr->hdr_len) != info->dynamic_hdr_len) {
149 return -EINVAL;
152 info->hdr_len = base_hdr_len;
153 info->dynamic_hdr_len = 0;
156 bin = fw + info->hdr_len;
159 section_info = info->section_info;
160 for (i = 0; i < info->section_num; i++) {
161 section = &fw_hdr->sections[i];
162 section_info->type =
163 le32_get_bits(section->w1, FWSECTION_HDR_W1_SECTIONTYPE);
164 if (section_info->type == FWDL_SECURITY_SECTION_TYPE) {
165 section_info->mssc =
166 le32_get_bits(section->w2, FWSECTION_HDR_W2_MSSC);
167 mssc_len += section_info->mssc * FWDL_SECURITY_SIGLEN;
169 section_info->mssc = 0;
172 section_info->len = le32_get_bits(section->w1, FWSECTION_HDR_W1_SEC_SIZE);
173 if (le32_get_bits(section->w1, FWSECTION_HDR_W1_CHECKSUM))
174 section_info->len += FWDL_SECTION_CHKSUM_LEN;
175 section_info->redl = le32_get_bits(section->w1, FWSECTION_HDR_W1_REDL);
176 section_info->dladdr =
177 le32_get_bits(section->w0, FWSECTION_HDR_W0_DL_ADDR) & 0x1fffffff;
178 section_info->addr = bin;
179 bin += section_info->len;
185 return -EINVAL;
195 struct rtw89_fw_secure *sec = &rtwdev->fw.sec;
201 if (sec->mss_dev_type == RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF) {
202 if (!mss_hdr->defen)
203 return -ENOENT;
205 mss_sel_idx = sec->mss_cust_idx * le16_to_cpu(mss_hdr->msskey_num_max) +
206 sec->mss_key_num;
208 if (mss_hdr->defen)
212 mss_sel_idx += sec->mss_dev_type * le16_to_cpu(mss_hdr->msskey_num_max) *
213 le16_to_cpu(mss_hdr->msscust_max) +
214 sec->mss_cust_idx * le16_to_cpu(mss_hdr->msskey_num_max) +
215 sec->mss_key_num;
222 return -EFAULT;
224 if (!(mss_hdr->rmp_tbl[sel_byte_idx] & BIT(sel_bit_idx)))
225 return -ENOENT;
227 *key_idx = hweight8(mss_hdr->rmp_tbl[sel_byte_idx] & (BIT(sel_bit_idx) - 1));
230 *key_idx += hweight8(mss_hdr->rmp_tbl[i]);
247 const struct rtw89_fw_mss_pool_hdr *mss_hdr = content + section_info->len;
250 const struct rtw89_fw_mss_pool_hdr *mss_hdr = (const void *)(content + section_info->len);
253 struct rtw89_fw_secure *sec = &rtwdev->fw.sec;
260 if (memcmp(mss_signature, mss_hdr->signature, sizeof(mss_signature)) != 0) {
262 return -ENOENT;
265 if (mss_hdr->rmpfmt == MSS_POOL_RMP_TBL_BITMASK) {
266 rmp_tbl_size = (le16_to_cpu(mss_hdr->msskey_num_max) *
267 le16_to_cpu(mss_hdr->msscust_max) *
268 mss_hdr->mssdev_max) >> 3;
269 if (mss_hdr->defen)
273 mss_hdr->rmpfmt);
274 return -EINVAL;
277 if (rmp_tbl_size + sizeof(*mss_hdr) != le32_to_cpu(mss_hdr->key_raw_offset)) {
280 le32_to_cpu(mss_hdr->key_raw_offset));
281 return -EINVAL;
284 key_sign_len = le16_to_cpu(section_content->key_sign_len.v) >> 2;
288 if (info->dsp_checksum)
292 le16_to_cpu(mss_hdr->keypair_num) * key_sign_len;
294 if (!sec->secure_boot)
297 sb_sel_ver = le32_to_cpu(section_content->sb_sel_ver.v);
298 if (sb_sel_ver && sb_sel_ver != sec->sb_sel_mgn)
305 section_info->key_addr = content + section_info->len +
306 le32_to_cpu(mss_hdr->key_raw_offset) +
308 section_info->key_len = key_sign_len;
309 section_info->key_idx = real_key_idx;
312 if (info->secure_section_exist) {
313 section_info->ignore = true;
317 info->secure_section_exist = true;
322 section_info->ignore = true;
340 section_info->mssc =
341 le32_get_bits(section->w2, FWSECTION_HDR_V1_W2_MSSC);
343 if (section_info->mssc == FORMATTED_MSSC) {
347 return -EINVAL;
349 *mssc_len = section_info->mssc * FWDL_SECURITY_SIGLEN;
350 if (info->dsp_checksum)
351 *mssc_len += section_info->mssc * FWDL_SECURITY_CHKSUM_LEN;
353 info->secure_section_exist = true;
373 info->section_num = le32_get_bits(fw_hdr->w6, FW_HDR_V1_W6_SEC_NUM);
374 info->dsp_checksum = le32_get_bits(fw_hdr->w6, FW_HDR_V1_W6_DSP_CHKSUM);
375 base_hdr_len = struct_size(fw_hdr, sections, info->section_num);
376 info->dynamic_hdr_en = le32_get_bits(fw_hdr->w7, FW_HDR_V1_W7_DYN_HDR);
378 if (info->dynamic_hdr_en) {
379 info->hdr_len = le32_get_bits(fw_hdr->w5, FW_HDR_V1_W5_HDR_SIZE);
380 info->dynamic_hdr_len = info->hdr_len - base_hdr_len;
382 if (le32_to_cpu(fwdynhdr->hdr_len) != info->dynamic_hdr_len) {
384 return -EINVAL;
387 info->hdr_len = base_hdr_len;
388 info->dynamic_hdr_len = 0;
391 bin = fw + info->hdr_len;
394 section_info = info->section_info;
395 for (i = 0; i < info->section_num; i++) {
396 section = &fw_hdr->sections[i];
398 section_info->type =
399 le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_SECTIONTYPE);
400 section_info->len =
401 le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_SEC_SIZE);
402 if (le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_CHECKSUM))
403 section_info->len += FWDL_SECTION_CHKSUM_LEN;
404 section_info->redl = le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_REDL);
405 section_info->dladdr =
406 le32_get_bits(section->w0, FWSECTION_HDR_V1_W0_DL_ADDR);
407 section_info->addr = bin;
409 if (section_info->type == FWDL_SECURITY_SECTION_TYPE) {
415 section_info->mssc = 0;
420 "section[%d] type=%d len=0x%-6x mssc=%d mssc_len=%d addr=%tx\n",
421 i, section_info->type, section_info->len,
422 section_info->mssc, mssc_len, bin - fw);
425 section_info->ignore, section_info->key_addr,
426 section_info->key_addr ?
427 section_info->key_addr - section_info->addr : 0,
428 section_info->key_len, section_info->key_idx);
430 bin += section_info->len + mssc_len;
436 return -EINVAL;
439 if (!info->secure_section_exist)
449 const u8 *fw = fw_suit->data;
450 u32 len = fw_suit->size;
453 rtw89_err(rtwdev, "fw type %d isn't recognized\n", fw_suit->type);
454 return -ENOENT;
457 switch (fw_suit->hdr_ver) {
463 return -ENOENT;
471 struct rtw89_fw_info *fw_info = &rtwdev->fw;
472 const struct firmware *firmware = fw_info->req.firmware;
473 const u8 *mfw = firmware->data;
474 u32 mfw_len = firmware->size;
479 if (mfw_hdr->sig != RTW89_MFW_SIG) {
483 return -EINVAL;
484 fw_suit->data = mfw;
485 fw_suit->size = mfw_len;
489 for (i = 0; i < mfw_hdr->fw_nr; i++) {
490 tmp = &mfw_hdr->info[i];
491 if (tmp->type != type)
502 if (tmp->cv <= rtwdev->hal.cv && !tmp->mp) {
503 if (!mfw_info || mfw_info->cv < tmp->cv)
513 return -ENOENT;
516 fw_suit->data = mfw + le32_to_cpu(mfw_info->shift);
517 fw_suit->size = le32_to_cpu(mfw_info->size);
523 struct rtw89_fw_info *fw_info = &rtwdev->fw;
524 const struct firmware *firmware = fw_info->req.firmware;
526 (const struct rtw89_mfw_hdr *)firmware->data;
530 if (mfw_hdr->sig != RTW89_MFW_SIG) {
535 mfw_info = &mfw_hdr->info[mfw_hdr->fw_nr - 1];
536 size = le32_to_cpu(mfw_info->shift) + le32_to_cpu(mfw_info->size);
545 fw_suit->major_ver = le32_get_bits(hdr->w1, FW_HDR_W1_MAJOR_VERSION);
546 fw_suit->minor_ver = le32_get_bits(hdr->w1, FW_HDR_W1_MINOR_VERSION);
547 fw_suit->sub_ver = le32_get_bits(hdr->w1, FW_HDR_W1_SUBVERSION);
548 fw_suit->sub_idex = le32_get_bits(hdr->w1, FW_HDR_W1_SUBINDEX);
549 fw_suit->commitid = le32_get_bits(hdr->w2, FW_HDR_W2_COMMITID);
550 fw_suit->build_year = le32_get_bits(hdr->w5, FW_HDR_W5_YEAR);
551 fw_suit->build_mon = le32_get_bits(hdr->w4, FW_HDR_W4_MONTH);
552 fw_suit->build_date = le32_get_bits(hdr->w4, FW_HDR_W4_DATE);
553 fw_suit->build_hour = le32_get_bits(hdr->w4, FW_HDR_W4_HOUR);
554 fw_suit->build_min = le32_get_bits(hdr->w4, FW_HDR_W4_MIN);
555 fw_suit->cmd_ver = le32_get_bits(hdr->w7, FW_HDR_W7_CMD_VERSERION);
562 fw_suit->major_ver = le32_get_bits(hdr->w1, FW_HDR_V1_W1_MAJOR_VERSION);
563 fw_suit->minor_ver = le32_get_bits(hdr->w1, FW_HDR_V1_W1_MINOR_VERSION);
564 fw_suit->sub_ver = le32_get_bits(hdr->w1, FW_HDR_V1_W1_SUBVERSION);
565 fw_suit->sub_idex = le32_get_bits(hdr->w1, FW_HDR_V1_W1_SUBINDEX);
566 fw_suit->commitid = le32_get_bits(hdr->w2, FW_HDR_V1_W2_COMMITID);
567 fw_suit->build_year = le32_get_bits(hdr->w5, FW_HDR_V1_W5_YEAR);
568 fw_suit->build_mon = le32_get_bits(hdr->w4, FW_HDR_V1_W4_MONTH);
569 fw_suit->build_date = le32_get_bits(hdr->w4, FW_HDR_V1_W4_DATE);
570 fw_suit->build_hour = le32_get_bits(hdr->w4, FW_HDR_V1_W4_HOUR);
571 fw_suit->build_min = le32_get_bits(hdr->w4, FW_HDR_V1_W4_MIN);
572 fw_suit->cmd_ver = le32_get_bits(hdr->w7, FW_HDR_V1_W3_CMD_VERSERION);
579 const struct rtw89_fw_hdr *v0 = (const struct rtw89_fw_hdr *)fw_suit->data;
580 const struct rtw89_fw_hdr_v1 *v1 = (const struct rtw89_fw_hdr_v1 *)fw_suit->data;
585 fw_suit->type = type;
586 fw_suit->hdr_ver = le32_get_bits(v0->w3, FW_HDR_W3_HDR_VER);
588 switch (fw_suit->hdr_ver) {
597 fw_suit->hdr_ver);
598 return -ENOENT;
603 fw_suit->major_ver, fw_suit->minor_ver, fw_suit->sub_ver,
604 fw_suit->sub_idex, fw_suit->commitid, fw_suit->cmd_ver, type);
633 struct rtw89_hal *hal = &rtwdev->hal;
639 if (hal->cv < elm->u.bbmcu.cv)
643 if (fw_suit->data)
646 fw_suit->data = elm->u.bbmcu.contents;
647 fw_suit->size = le32_to_cpu(elm->size);
712 if (chip->chip_id != ent->chip_id)
715 if (ent->cond(ver_code, ent->ver_code))
716 RTW89_SET_FW_FEATURE(ent->feature, fw);
722 const struct rtw89_chip_info *chip = rtwdev->chip;
729 rtw89_fw_iterate_feature_cfg(&rtwdev->fw, chip, suit_ver_code);
744 for (fw_format = chip->fw_format_max; fw_format >= 0; fw_format--) {
746 chip->fw_basename, fw_format);
761 ver_code = rtw89_compat_fw_hdr_ver_code(firmware->data);
774 const struct rtw89_chip_info *chip = rtwdev->chip;
777 if (chip->try_ce_fw) {
806 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
815 return -ENOMEM;
817 switch (le32_to_cpu(elm->id)) {
819 elm_info->bb_tbl = tbl;
822 elm_info->bb_gain = tbl;
833 idx = elm->u.reg2.idx;
835 elm_info->rf_radio[idx] = tbl;
836 tbl->rf_path = rf_path;
837 tbl->config = rtw89_phy_config_rf_reg_v1;
840 elm_info->rf_nctl = tbl;
844 return -ENOENT;
847 n_regs = le32_to_cpu(elm->size) / sizeof(tbl->regs[0]);
848 regs = kcalloc(n_regs, sizeof(tbl->regs[0]), GFP_KERNEL);
853 regs[i].addr = le32_to_cpu(elm->u.reg2.regs[i].addr);
854 regs[i].data = le32_to_cpu(elm->u.reg2.regs[i].data);
857 tbl->n_regs = n_regs;
858 tbl->regs = regs;
864 return -ENOMEM;
872 const struct __rtw89_fw_txpwr_element *txpwr_elm = &elm->u.txpwr;
874 struct rtw89_efuse *efuse = &rtwdev->efuse;
877 if (!rtwdev->rfe_data) {
878 rtwdev->rfe_data = kzalloc(sizeof(*rtwdev->rfe_data), GFP_KERNEL);
879 if (!rtwdev->rfe_data)
880 return -ENOMEM;
884 conf = (void *)rtwdev->rfe_data + offset;
886 conf = (void *)((u8 *)rtwdev->rfe_data + offset);
890 if (txpwr_elm->rfe_type == efuse->rfe_type)
894 if (txpwr_elm->rfe_type == RTW89_TXPWR_CONF_DFLT_RFE_TYPE &&
896 conf->rfe_type == RTW89_TXPWR_CONF_DFLT_RFE_TYPE))
900 elm->id, txpwr_elm->rfe_type);
905 elm->id, txpwr_elm->rfe_type);
907 conf->rfe_type = txpwr_elm->rfe_type;
908 conf->ent_sz = txpwr_elm->ent_sz;
909 conf->num_ents = le32_to_cpu(txpwr_elm->num_ents);
910 conf->data = txpwr_elm->content;
919 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
920 const struct rtw89_chip_info *chip = rtwdev->chip;
927 if (chip->support_bands & BIT(NL80211_BAND_6GHZ))
929 if (chip->support_bands & BIT(NL80211_BAND_5GHZ))
931 if (chip->support_bands & BIT(NL80211_BAND_2GHZ))
934 bitmap = le32_to_cpu(elm->u.txpwr_trk.bitmap);
939 return -ENOENT;
942 elm_info->txpwr_trk = kzalloc(sizeof(*elm_info->txpwr_trk), GFP_KERNEL);
943 if (!elm_info->txpwr_trk)
944 return -ENOMEM;
962 elm_info->txpwr_trk->delta[type] = &elm->u.txpwr_trk.contents[offset];
965 if (offset * DELTA_SWINGIDX_SIZE > le32_to_cpu(elm->size))
973 offset, le32_to_cpu(elm->size));
974 kfree(elm_info->txpwr_trk);
975 elm_info->txpwr_trk = NULL;
977 return -EFAULT;
985 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
988 if (elm_info->rfk_log_fmt)
991 elm_info->rfk_log_fmt = kzalloc(sizeof(*elm_info->rfk_log_fmt), GFP_KERNEL);
992 if (!elm_info->rfk_log_fmt)
996 rfk_id = elm->u.rfk_log_fmt.rfk_id;
1000 elm_info->rfk_log_fmt->elm[rfk_id] = elm;
1067 struct rtw89_fw_info *fw_info = &rtwdev->fw;
1068 const struct firmware *firmware = fw_info->req.firmware;
1069 const struct rtw89_chip_info *chip = rtwdev->chip;
1070 u32 unrecognized_elements = chip->needed_fw_elms;
1078 BUILD_BUG_ON(sizeof(chip->needed_fw_elms) * 8 < RTW89_FW_ELEMENT_ID_NUM);
1083 return -EINVAL;
1085 while (offset + sizeof(*hdr) < firmware->size) {
1086 hdr = (const struct rtw89_fw_element_hdr *)(firmware->data + offset);
1088 elm_size = le32_to_cpu(hdr->size);
1089 if (offset + elm_size >= firmware->size) {
1094 elem_id = le32_to_cpu(hdr->id);
1099 if (!handler->fn)
1102 ret = handler->fn(rtwdev, hdr, handler->arg);
1108 if (handler->name)
1110 handler->name, hdr->ver);
1121 return -ENOENT;
1135 if (!(rtwdev->fw.h2c_seq % 4))
1137 hdr->hdr0 = cpu_to_le32(FIELD_PREP(H2C_HDR_DEL_TYPE, type) |
1141 FIELD_PREP(H2C_HDR_H2C_SEQ, rtwdev->fw.h2c_seq));
1143 hdr->hdr1 = cpu_to_le32(FIELD_PREP(H2C_HDR_TOTAL_LEN,
1148 rtwdev->fw.h2c_seq++;
1160 hdr->hdr0 = cpu_to_le32(FIELD_PREP(H2C_HDR_DEL_TYPE, type) |
1164 FIELD_PREP(H2C_HDR_H2C_SEQ, rtwdev->fw.h2c_seq));
1166 hdr->hdr1 = cpu_to_le32(FIELD_PREP(H2C_HDR_TOTAL_LEN,
1174 le32p_replace_bits(&fw_hdr->w7, FWDL_SECTION_PER_PKT_LEN,
1189 le32p_replace_bits(&fw_hdr->w7, FWDL_SECTION_PER_PKT_LEN,
1192 for (sec_idx = 0; sec_idx < info->section_num; sec_idx++) {
1193 section_info = &info->section_info[sec_idx];
1194 section = &fw_hdr->sections[sec_idx];
1196 if (section_info->ignore)
1200 fw_hdr->sections[dst_sec_idx] = *section;
1205 le32p_replace_bits(&fw_hdr->w6, dst_sec_idx, FW_HDR_V1_W6_SEC_NUM);
1207 return (info->section_num - dst_sec_idx) * sizeof(*section);
1214 u32 len = info->hdr_len - info->dynamic_hdr_len;
1216 const u8 *fw = fw_suit->data;
1225 return -ENOMEM;
1230 switch (fw_suit->hdr_ver) {
1232 fw_hdr = (struct rtw89_fw_hdr *)skb->data;
1236 fw_hdr_v1 = (struct rtw89_fw_hdr_v1 *)skb->data;
1240 ret = -EOPNOTSUPP;
1245 len -= truncated;
1256 ret = -1;
1271 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1280 ret = mac->fwdl_check_path_ready(rtwdev, false);
1296 const u8 *section = info->addr;
1297 u32 residue_len = info->len;
1302 if (info->ignore)
1305 if (info->key_addr && info->key_len) {
1306 if (info->len > FWDL_SECTION_PER_PKT_LEN || info->len < info->key_len)
1308 info->len, FWDL_SECTION_PER_PKT_LEN, info->key_len);
1322 return -ENOMEM;
1327 memcpy(skb->data + pkt_len - info->key_len,
1328 info->key_addr, info->key_len);
1333 ret = -1;
1338 residue_len -= pkt_len;
1352 switch (fw_suit->type) {
1366 struct rtw89_fw_hdr_section_info *section_info = info->section_info;
1367 const struct rtw89_chip_info *chip = rtwdev->chip;
1369 u8 section_num = info->section_num;
1372 while (section_num--) {
1379 if (chip->chip_gen == RTW89_CHIP_AX)
1386 fw_suit->type);
1395 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
1439 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1449 if (rtwdev->chip->chip_id == RTL8922A &&
1450 (fw_suit->type == RTW89_FW_NORMAL || fw_suit->type == RTW89_FW_WOWLAN))
1453 ret = mac->fwdl_check_path_ready(rtwdev, true);
1474 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1475 struct rtw89_fw_info *fw_info = &rtwdev->fw;
1477 u8 bbmcu_nr = rtwdev->chip->bbmcu_nr;
1481 mac->disable_cpu(rtwdev);
1482 ret = mac->fwdl_enable_wcpu(rtwdev, 0, true, include_bb);
1498 fw_info->h2c_seq = 0;
1499 fw_info->rec_seq = 0;
1500 fw_info->h2c_counter = 0;
1501 fw_info->c2h_counter = 0;
1502 rtwdev->mac.rpwm_seq_num = RPWM_SEQ_NUM_MAX;
1503 rtwdev->mac.cpwm_seq_num = CPWM_SEQ_NUM_MAX;
1537 struct rtw89_fw_info *fw = &rtwdev->fw;
1539 wait_for_completion(&fw->req.completion);
1540 if (!fw->req.firmware)
1541 return -EINVAL;
1552 if (req->firmware) {
1555 complete_all(&req->completion);
1560 ret = firmware_request_nowarn(&req->firmware, fw_name, rtwdev->dev);
1562 ret = request_firmware(&req->firmware, fw_name, rtwdev->dev);
1564 complete_all(&req->completion);
1573 const struct rtw89_chip_info *chip = rtwdev->chip;
1577 chip->fw_basename, rtwdev->fw.fw_format);
1579 rtw89_load_firmware_req(rtwdev, &rtwdev->fw.req, fw_name, false);
1587 kfree(tbl->regs);
1593 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1596 rtw89_free_phy_tbl_from_elm(elm_info->bb_tbl);
1597 rtw89_free_phy_tbl_from_elm(elm_info->bb_gain);
1598 for (i = 0; i < ARRAY_SIZE(elm_info->rf_radio); i++)
1599 rtw89_free_phy_tbl_from_elm(elm_info->rf_radio[i]);
1600 rtw89_free_phy_tbl_from_elm(elm_info->rf_nctl);
1602 kfree(elm_info->txpwr_trk);
1603 kfree(elm_info->rfk_log_fmt);
1608 struct rtw89_fw_info *fw = &rtwdev->fw;
1610 cancel_work_sync(&rtwdev->load_firmware_work);
1612 if (fw->req.firmware) {
1613 release_firmware(fw->req.firmware);
1618 fw->req.firmware = NULL;
1621 kfree(fw->log.fmts);
1627 struct rtw89_fw_log *fw_log = &rtwdev->fw.log;
1630 if (fmt_id > fw_log->last_fmt_id)
1633 for (i = 0; i < fw_log->fmt_count; i++) {
1634 if (le32_to_cpu(fw_log->fmt_ids[i]) == fmt_id)
1642 struct rtw89_fw_log *log = &rtwdev->fw.log;
1644 struct rtw89_fw_suit *suit = &log->suit;
1653 suit_hdr = (const struct rtw89_fw_logsuit_hdr *)suit->data;
1654 fmt_count = le32_to_cpu(suit_hdr->count);
1655 log->fmt_ids = suit_hdr->ids;
1657 fmts_ptr = &suit_hdr->ids[fmt_count];
1659 fmts_ptr = (const u8 *)&suit_hdr->ids[fmt_count];
1661 fmts_end_ptr = suit->data + suit->size;
1662 log->fmts = kcalloc(fmt_count, sizeof(char *), GFP_KERNEL);
1663 if (!log->fmts)
1664 return -ENOMEM;
1667 fmts_ptr = memchr_inv(fmts_ptr, 0, fmts_end_ptr - fmts_ptr);
1671 (*log->fmts)[i] = fmts_ptr;
1672 log->last_fmt_id = le32_to_cpu(log->fmt_ids[i]);
1673 log->fmt_count++;
1682 struct rtw89_fw_log *log = &rtwdev->fw.log;
1683 struct rtw89_fw_suit *suit = &log->suit;
1685 if (!suit || !suit->data) {
1687 return -EINVAL;
1689 if (log->fmts)
1699 const char *(*fmts)[] = rtwdev->fw.log.fmts;
1704 if (log_fmt->argc > RTW89_C2H_FW_LOG_MAX_PARA_NUM) {
1706 log_fmt->argc);
1711 for (i = 0 ; i < log_fmt->argc; i++)
1712 args[i] = le32_to_cpu(log_fmt->u.argv[i]);
1717 "fw_enc(%d, %d, %d) %*ph", le32_to_cpu(log_fmt->fmt_id),
1718 para_int, log_fmt->argc, (int)sizeof(args), args);
1721 "fw_enc(%d, %d, %d, %s)", le32_to_cpu(log_fmt->fmt_id),
1722 para_int, log_fmt->argc, log_fmt->u.raw);
1746 len -= RTW89_C2H_HEADER_LEN;
1752 if (log_fmt->signature != cpu_to_le16(RTW89_C2H_FW_LOG_SIGNATURE))
1755 if (!rtwdev->fw.log.fmts)
1758 para_int = u8_get_bits(log_fmt->feature, RTW89_C2H_FW_LOG_FEATURE_PARA_INT);
1759 fmt_idx = rtw89_fw_log_get_fmt_idx(rtwdev, le32_to_cpu(log_fmt->fmt_id));
1761 if (!para_int && log_fmt->argc != 0 && fmt_idx != 0)
1763 (*rtwdev->fw.log.fmts)[fmt_idx], log_fmt->u.raw);
1785 return -ENOMEM;
1788 rtw89_cam_fill_addr_cam_info(rtwdev, rtwvif, rtwsta, scan_mac_addr, skb->data);
1789 rtw89_cam_fill_bssid_cam_info(rtwdev, rtwvif, rtwsta, skb->data);
1822 return -ENOMEM;
1825 h2c = (struct rtw89_h2c_dctlinfo_ud_v1 *)skb->data;
1861 return -ENOMEM;
1864 h2c = (struct rtw89_h2c_dctlinfo_ud_v2 *)skb->data;
1892 u8 mac_id = rtwsta ? rtwsta->mac_id : rtwvif->mac_id;
1901 return -ENOMEM;
1904 h2c = (struct rtw89_h2c_dctlinfo_ud_v2 *)skb->data;
1906 h2c->c0 = le32_encode_bits(mac_id, DCTLINFO_V2_C0_MACID) |
1909 h2c->m0 = cpu_to_le32(DCTLINFO_V2_W0_ALL);
1910 h2c->m1 = cpu_to_le32(DCTLINFO_V2_W1_ALL);
1911 h2c->m2 = cpu_to_le32(DCTLINFO_V2_W2_ALL);
1912 h2c->m3 = cpu_to_le32(DCTLINFO_V2_W3_ALL);
1913 h2c->m4 = cpu_to_le32(DCTLINFO_V2_W4_ALL);
1914 h2c->m5 = cpu_to_le32(DCTLINFO_V2_W5_ALL);
1915 h2c->m6 = cpu_to_le32(DCTLINFO_V2_W6_ALL);
1916 h2c->m7 = cpu_to_le32(DCTLINFO_V2_W7_ALL);
1917 h2c->m8 = cpu_to_le32(DCTLINFO_V2_W8_ALL);
1918 h2c->m9 = cpu_to_le32(DCTLINFO_V2_W9_ALL);
1919 h2c->m10 = cpu_to_le32(DCTLINFO_V2_W10_ALL);
1920 h2c->m11 = cpu_to_le32(DCTLINFO_V2_W11_ALL);
1921 h2c->m12 = cpu_to_le32(DCTLINFO_V2_W12_ALL);
1946 const struct rtw89_chip_info *chip = rtwdev->chip;
1947 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
1949 u8 macid = rtwsta->mac_id;
1956 rtw89_core_acquire_sta_ba_entry(rtwdev, rtwsta, params->tid, &entry_idx) :
1957 rtw89_core_release_sta_ba_entry(rtwdev, rtwsta, params->tid, &entry_idx);
1964 valid ? "alloc" : "free", params->tid);
1971 return -ENOMEM;
1974 h2c = (struct rtw89_h2c_ba_cam *)skb->data;
1976 h2c->w0 = le32_encode_bits(macid, RTW89_H2C_BA_CAM_W0_MACID);
1977 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
1978 h2c->w1 |= le32_encode_bits(entry_idx, RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1);
1980 h2c->w0 |= le32_encode_bits(entry_idx, RTW89_H2C_BA_CAM_W0_ENTRY_IDX);
1983 h2c->w0 |= le32_encode_bits(valid, RTW89_H2C_BA_CAM_W0_VALID) |
1984 le32_encode_bits(params->tid, RTW89_H2C_BA_CAM_W0_TID);
1985 if (params->buf_size > 64)
1986 h2c->w0 |= le32_encode_bits(4, RTW89_H2C_BA_CAM_W0_BMAP_SIZE);
1988 h2c->w0 |= le32_encode_bits(0, RTW89_H2C_BA_CAM_W0_BMAP_SIZE);
1990 h2c->w0 |= le32_encode_bits(1, RTW89_H2C_BA_CAM_W0_INIT_REQ) |
1991 le32_encode_bits(params->ssn, RTW89_H2C_BA_CAM_W0_SSN);
1993 if (chip->bacam_ver == RTW89_BACAM_V0_EXT) {
1994 h2c->w1 |= le32_encode_bits(1, RTW89_H2C_BA_CAM_W1_STD_EN) |
1995 le32_encode_bits(rtwvif->mac_idx, RTW89_H2C_BA_CAM_W1_BAND);
2030 return -ENOMEM;
2033 h2c = (struct rtw89_h2c_ba_cam *)skb->data;
2035 h2c->w0 = le32_encode_bits(1, RTW89_H2C_BA_CAM_W0_VALID);
2036 h2c->w1 = le32_encode_bits(entry_idx, RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1) |
2062 const struct rtw89_chip_info *chip = rtwdev->chip;
2063 u8 entry_idx = chip->bacam_num;
2067 for (i = 0; i < chip->bacam_dynamic_num; i++) {
2077 const struct rtw89_chip_info *chip = rtwdev->chip;
2078 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
2080 u8 macid = rtwsta->mac_id;
2088 rtw89_core_acquire_sta_ba_entry(rtwdev, rtwsta, params->tid, &entry_idx) :
2089 rtw89_core_release_sta_ba_entry(rtwdev, rtwsta, params->tid, &entry_idx);
2096 valid ? "alloc" : "free", params->tid);
2103 return -ENOMEM;
2106 h2c = (struct rtw89_h2c_ba_cam_v1 *)skb->data;
2108 if (params->buf_size > 512)
2110 else if (params->buf_size > 256)
2112 else if (params->buf_size > 64)
2117 h2c->w0 = le32_encode_bits(valid, RTW89_H2C_BA_CAM_V1_W0_VALID) |
2120 le32_encode_bits(params->tid, RTW89_H2C_BA_CAM_V1_W0_TID_MASK) |
2122 le32_encode_bits(params->ssn, RTW89_H2C_BA_CAM_V1_W0_SSN_MASK);
2124 entry_idx += chip->bacam_dynamic_num; /* std entry right after dynamic ones */
2125 h2c->w1 = le32_encode_bits(entry_idx, RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK) |
2127 le32_encode_bits(!!rtwvif->mac_idx, RTW89_H2C_BA_CAM_V1_W1_BAND_SEL);
2160 return -ENOMEM;
2163 h2c = (struct rtw89_h2c_ba_cam_init *)skb->data;
2165 h2c->w0 = le32_encode_bits(users, RTW89_H2C_BA_CAM_INIT_USERS_MASK) |
2203 return -ENOMEM;
2207 SET_LOG_CFG_LEVEL(skb->data, RTW89_FW_LOG_LEVEL_LOUD);
2208 SET_LOG_CFG_PATH(skb->data, BIT(RTW89_FW_LOG_LEVEL_C2H));
2209 SET_LOG_CFG_COMP(skb->data, comp);
2210 SET_LOG_CFG_COMP_EXT(skb->data, 0);
2237 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2239 struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
2245 if (rtw_wow->ptk_alg == 3)
2247 else if (rtw_wow->akm == 1 || rtw_wow->akm == 2)
2249 else if (rtw_wow->akm > 2 && rtw_wow->akm < 7)
2259 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA |
2262 ether_addr_copy(hdr->addr1, bss_conf->bssid);
2263 ether_addr_copy(hdr->addr2, vif->addr);
2264 ether_addr_copy(hdr->addr3, bss_conf->bssid);
2269 memcpy(eapol_pkt->gtkbody, gtkbody, sizeof(gtkbody));
2270 eapol_pkt->key_des_ver = key_des_ver;
2279 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2290 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
2293 ether_addr_copy(hdr->addr1, bss_conf->bssid);
2294 ether_addr_copy(hdr->addr2, vif->addr);
2295 ether_addr_copy(hdr->addr3, bss_conf->bssid);
2300 sa_query->category = WLAN_CATEGORY_SA_QUERY;
2301 sa_query->action = WLAN_ACTION_SA_QUERY_RESPONSE;
2310 struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
2323 if (rtw_wow->ptk_alg)
2329 hdr->frame_control = fc;
2330 ether_addr_copy(hdr->addr1, rtwvif->bssid);
2331 ether_addr_copy(hdr->addr2, rtwvif->mac_addr);
2332 ether_addr_copy(hdr->addr3, rtwvif->bssid);
2337 memcpy(arp_skb->llc_hdr, rfc1042_header, sizeof(rfc1042_header));
2338 arp_skb->llc_type = htons(ETH_P_ARP);
2340 arp_hdr = &arp_skb->arp_hdr;
2341 arp_hdr->ar_hrd = htons(ARPHRD_ETHER);
2342 arp_hdr->ar_pro = htons(ETH_P_IP);
2343 arp_hdr->ar_hln = ETH_ALEN;
2344 arp_hdr->ar_pln = 4;
2345 arp_hdr->ar_op = htons(ARPOP_REPLY);
2347 ether_addr_copy(arp_skb->sender_hw, rtwvif->mac_addr);
2348 arp_skb->sender_ip = rtwvif->ip_addr;
2365 return -ENOMEM;
2369 skb = ieee80211_pspoll_get(rtwdev->hw, vif);
2372 skb = ieee80211_proberesp_get(rtwdev->hw, vif);
2375 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, false);
2378 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, true);
2396 ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, skb);
2402 list_add_tail(&info->list, &rtwvif->general_pkt_list);
2403 *id = info->id;
2408 return -ENOMEM;
2414 struct list_head *pkt_list = &rtwvif->general_pkt_list;
2419 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
2421 rtw89_core_release_bit_map(rtwdev->pkt_offload, info->id);
2422 list_del(&info->list);
2456 return -ENOMEM;
2459 SET_GENERAL_PKT_MACID(skb->data, macid);
2460 SET_GENERAL_PKT_PROBRSP_ID(skb->data, H2C_GENERAL_PKT_ID_UND);
2461 SET_GENERAL_PKT_PSPOLL_ID(skb->data, pkt_id_ps_poll);
2462 SET_GENERAL_PKT_NULL_ID(skb->data, pkt_id_null);
2463 SET_GENERAL_PKT_QOS_NULL_ID(skb->data, pkt_id_qos_null);
2464 SET_GENERAL_PKT_CTS2SELF_ID(skb->data, H2C_GENERAL_PKT_ID_UND);
2495 return -ENOMEM;
2499 SET_LPS_PARM_MACID(skb->data, lps_param->macid);
2500 SET_LPS_PARM_PSMODE(skb->data, lps_param->psmode);
2501 SET_LPS_PARM_LASTRPWM(skb->data, lps_param->lastrpwm);
2502 SET_LPS_PARM_RLBM(skb->data, 1);
2503 SET_LPS_PARM_SMARTPS(skb->data, 1);
2504 SET_LPS_PARM_AWAKEINTERVAL(skb->data, 1);
2505 SET_LPS_PARM_VOUAPSD(skb->data, 0);
2506 SET_LPS_PARM_VIUAPSD(skb->data, 0);
2507 SET_LPS_PARM_BEUAPSD(skb->data, 0);
2508 SET_LPS_PARM_BKUAPSD(skb->data, 0);
2532 rtwvif->sub_entity_idx);
2533 const struct rtw89_chip_info *chip = rtwdev->chip;
2540 if (chip->chip_gen != RTW89_CHIP_BE)
2546 return -ENOMEM;
2549 h2c = (struct rtw89_h2c_lps_ch_info *)skb->data;
2551 h2c->info[0].central_ch = chan->channel;
2552 h2c->info[0].pri_ch = chan->primary_channel;
2553 h2c->info[0].band = chan->band_type;
2554 h2c->info[0].bw = chan->band_width;
2555 h2c->mlo_dbcc_mode_lps = cpu_to_le32(MLO_2_PLUS_0_1RF);
2585 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2586 bool p2p_type_gc = rtwvif->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT;
2587 u8 ctwindow_oppps = vif->bss_conf.p2p_noa_attr.oppps_ctwindow;
2595 return -ENOMEM;
2598 cmd = skb->data;
2600 RTW89_SET_FWCMD_P2P_MACID(cmd, rtwvif->mac_id);
2607 RTW89_SET_FWCMD_NOA_START_TIME(cmd, desc->start_time);
2608 RTW89_SET_FWCMD_NOA_INTERVAL(cmd, desc->interval);
2609 RTW89_SET_FWCMD_NOA_DURATION(cmd, desc->duration);
2610 RTW89_SET_FWCMD_NOA_COUNT(cmd, desc->count);
2635 const struct rtw89_chip_info *chip = rtwdev->chip;
2636 struct rtw89_hal *hal = &rtwdev->hal;
2640 if (chip->rf_path_num == 1) {
2644 ntx_path = hal->antenna_tx ? hal->antenna_tx : RF_B;
2645 map_b = hal->antenna_tx == RF_AB ? 1 : 0;
2648 SET_CMC_TBL_NTX_PATH_EN(skb->data, ntx_path);
2649 SET_CMC_TBL_PATH_MAP_A(skb->data, 0);
2650 SET_CMC_TBL_PATH_MAP_B(skb->data, map_b);
2651 SET_CMC_TBL_PATH_MAP_C(skb->data, 0);
2652 SET_CMC_TBL_PATH_MAP_D(skb->data, 0);
2660 const struct rtw89_chip_info *chip = rtwdev->chip;
2661 u8 macid = rtwsta ? rtwsta->mac_id : rtwvif->mac_id;
2668 return -ENOMEM;
2671 SET_CTRL_INFO_MACID(skb->data, macid);
2672 SET_CTRL_INFO_OPERATION(skb->data, 1);
2673 if (chip->h2c_cctl_func_id == H2C_FUNC_MAC_CCTLINFO_UD) {
2674 SET_CMC_TBL_TXPWR_MODE(skb->data, 0);
2676 SET_CMC_TBL_ANTSEL_A(skb->data, 0);
2677 SET_CMC_TBL_ANTSEL_B(skb->data, 0);
2678 SET_CMC_TBL_ANTSEL_C(skb->data, 0);
2679 SET_CMC_TBL_ANTSEL_D(skb->data, 0);
2681 SET_CMC_TBL_DOPPLER_CTRL(skb->data, 0);
2682 SET_CMC_TBL_TXPWR_TOLERENCE(skb->data, 0);
2683 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE)
2684 SET_CMC_TBL_DATA_DCM(skb->data, 0);
2688 chip->h2c_cctl_func_id, 0, 1,
2709 u8 mac_id = rtwsta ? rtwsta->mac_id : rtwvif->mac_id;
2718 return -ENOMEM;
2721 h2c = (struct rtw89_h2c_cctlinfo_ud_g7 *)skb->data;
2723 h2c->c0 = le32_encode_bits(mac_id, CCTLINFO_G7_C0_MACID) |
2726 h2c->w0 = le32_encode_bits(4, CCTLINFO_G7_W0_DATARATE);
2727 h2c->m0 = cpu_to_le32(CCTLINFO_G7_W0_ALL);
2729 h2c->w1 = le32_encode_bits(4, CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE) |
2732 h2c->m1 = cpu_to_le32(CCTLINFO_G7_W1_ALL);
2734 h2c->m2 = cpu_to_le32(CCTLINFO_G7_W2_ALL);
2736 h2c->m3 = cpu_to_le32(CCTLINFO_G7_W3_ALL);
2738 h2c->w4 = le32_encode_bits(0xFFFF, CCTLINFO_G7_W4_ACT_SUBCH_CBW);
2739 h2c->m4 = cpu_to_le32(CCTLINFO_G7_W4_ALL);
2741 h2c->w5 = le32_encode_bits(2, CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0) |
2746 h2c->m5 = cpu_to_le32(CCTLINFO_G7_W5_ALL);
2748 h2c->w6 = le32_encode_bits(0xb, CCTLINFO_G7_W6_RESP_REF_RATE);
2749 h2c->m6 = cpu_to_le32(CCTLINFO_G7_W6_ALL);
2751 h2c->w7 = le32_encode_bits(1, CCTLINFO_G7_W7_NC) |
2756 h2c->m7 = cpu_to_le32(CCTLINFO_G7_W7_ALL);
2758 h2c->m8 = cpu_to_le32(CCTLINFO_G7_W8_ALL);
2760 h2c->w14 = le32_encode_bits(0, CCTLINFO_G7_W14_VO_CURR_RATE) |
2763 h2c->m14 = cpu_to_le32(CCTLINFO_G7_W14_ALL);
2765 h2c->w15 = le32_encode_bits(0, CCTLINFO_G7_W15_BE_CURR_RATE_H) |
2768 h2c->m15 = cpu_to_le32(CCTLINFO_G7_W15_ALL);
2794 u8 nss = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1;
2795 u8 ppe_thres_hdr = sta->deflink.he_cap.ppe_thres[0];
2802 sta->deflink.he_cap.he_cap_elem.phy_cap_info[6]);
2807 sta->deflink.he_cap.he_cap_elem.phy_cap_info[9]);
2829 ppe = le16_to_cpu(*((__le16 *)&sta->deflink.he_cap.ppe_thres[idx]));
2847 const struct rtw89_chip_info *chip = rtwdev->chip;
2849 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2851 rtwvif->sub_entity_idx);
2854 u8 mac_id = rtwsta ? rtwsta->mac_id : rtwvif->mac_id;
2859 if (sta && sta->deflink.he_cap.has_he)
2862 if (vif->p2p)
2864 else if (chan->band_type == RTW89_BAND_2G)
2872 return -ENOMEM;
2875 SET_CTRL_INFO_MACID(skb->data, mac_id);
2876 SET_CTRL_INFO_OPERATION(skb->data, 1);
2877 SET_CMC_TBL_DISRTSFB(skb->data, 1);
2878 SET_CMC_TBL_DISDATAFB(skb->data, 1);
2879 SET_CMC_TBL_RTS_RTY_LOWEST_RATE(skb->data, lowest_rate);
2880 SET_CMC_TBL_RTS_TXCNT_LMT_SEL(skb->data, 0);
2881 SET_CMC_TBL_DATA_TXCNT_LMT_SEL(skb->data, 0);
2882 if (vif->type == NL80211_IFTYPE_STATION)
2883 SET_CMC_TBL_ULDL(skb->data, 1);
2885 SET_CMC_TBL_ULDL(skb->data, 0);
2886 SET_CMC_TBL_MULTI_PORT_ID(skb->data, rtwvif->port);
2887 if (chip->h2c_cctl_func_id == H2C_FUNC_MAC_CCTLINFO_UD_V1) {
2888 SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_20]);
2889 SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_40]);
2890 SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_80]);
2891 SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_160]);
2892 } else if (chip->h2c_cctl_func_id == H2C_FUNC_MAC_CCTLINFO_UD) {
2893 SET_CMC_TBL_NOMINAL_PKT_PADDING(skb->data, pads[RTW89_CHANNEL_WIDTH_20]);
2894 SET_CMC_TBL_NOMINAL_PKT_PADDING40(skb->data, pads[RTW89_CHANNEL_WIDTH_40]);
2895 SET_CMC_TBL_NOMINAL_PKT_PADDING80(skb->data, pads[RTW89_CHANNEL_WIDTH_80]);
2896 SET_CMC_TBL_NOMINAL_PKT_PADDING160(skb->data, pads[RTW89_CHANNEL_WIDTH_160]);
2899 SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(skb->data,
2900 sta->deflink.he_cap.has_he);
2901 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE)
2902 SET_CMC_TBL_DATA_DCM(skb->data, 0);
2906 chip->h2c_cctl_func_id, 0, 1,
2926 u8 nss = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1;
2935 ppe_th = !!u8_get_bits(sta->deflink.eht_cap.eht_cap_elem.phy_cap_info[5],
2940 pad = u8_get_bits(sta->deflink.eht_cap.eht_cap_elem.phy_cap_info[5],
2949 ppe_thres_hdr = get_unaligned_le16(sta->deflink.eht_cap.eht_ppe_thres);
2966 ppe = get_unaligned_le16(sta->deflink.eht_cap.eht_ppe_thres + idx);
2985 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2987 u8 mac_id = rtwsta ? rtwsta->mac_id : rtwvif->mac_id;
2997 if (sta->deflink.eht_cap.has_eht)
2999 else if (sta->deflink.he_cap.has_he)
3003 if (vif->p2p)
3005 else if (chan->band_type == RTW89_BAND_2G)
3013 return -ENOMEM;
3016 h2c = (struct rtw89_h2c_cctlinfo_ud_g7 *)skb->data;
3018 h2c->c0 = le32_encode_bits(mac_id, CCTLINFO_G7_C0_MACID) |
3021 h2c->w0 = le32_encode_bits(1, CCTLINFO_G7_W0_DISRTSFB) |
3023 h2c->m0 = cpu_to_le32(CCTLINFO_G7_W0_DISRTSFB |
3026 h2c->w1 = le32_encode_bits(lowest_rate, CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE);
3027 h2c->m1 = cpu_to_le32(CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE);
3029 h2c->w2 = le32_encode_bits(0, CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL);
3030 h2c->m2 = cpu_to_le32(CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL);
3032 h2c->w3 = le32_encode_bits(0, CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL);
3033 h2c->m3 = cpu_to_le32(CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL);
3035 h2c->w4 = le32_encode_bits(rtwvif->port, CCTLINFO_G7_W4_MULTI_PORT_ID);
3036 h2c->m4 = cpu_to_le32(CCTLINFO_G7_W4_MULTI_PORT_ID);
3038 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) {
3039 h2c->w4 |= le32_encode_bits(0, CCTLINFO_G7_W4_DATA_DCM);
3040 h2c->m4 |= cpu_to_le32(CCTLINFO_G7_W4_DATA_DCM);
3043 if (vif->bss_conf.eht_support) {
3044 u16 punct = vif->bss_conf.chanreq.oper.punctured;
3046 h2c->w4 |= le32_encode_bits(~punct,
3048 h2c->m4 |= cpu_to_le32(CCTLINFO_G7_W4_ACT_SUBCH_CBW);
3051 h2c->w5 = le32_encode_bits(pads[RTW89_CHANNEL_WIDTH_20],
3061 h2c->m5 = cpu_to_le32(CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 |
3067 h2c->w6 = le32_encode_bits(vif->type == NL80211_IFTYPE_STATION ? 1 : 0,
3069 h2c->m6 = cpu_to_le32(CCTLINFO_G7_W6_ULDL);
3072 h2c->w8 = le32_encode_bits(sta->deflink.he_cap.has_he,
3074 h2c->m8 = cpu_to_le32(CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT);
3100 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3112 return -ENOMEM;
3115 h2c = (struct rtw89_h2c_cctlinfo_ud_g7 *)skb->data;
3117 for_each_set_bit(tid, rtwsta->ampdu_map, IEEE80211_NUM_TIDS) {
3119 agg_num = rtwsta->ampdu_params[tid].agg_num;
3121 agg_num = min(agg_num, rtwsta->ampdu_params[tid].agg_num);
3137 h2c->c0 = le32_encode_bits(rtwsta->mac_id, CCTLINFO_G7_C0_MACID) |
3140 h2c->w3 = le32_encode_bits(ba_bmap, CCTLINFO_G7_W3_BA_BMAP);
3141 h2c->m3 = cpu_to_le32(CCTLINFO_G7_W3_BA_BMAP);
3165 const struct rtw89_chip_info *chip = rtwdev->chip;
3172 return -ENOMEM;
3175 SET_CTRL_INFO_MACID(skb->data, rtwsta->mac_id);
3176 SET_CTRL_INFO_OPERATION(skb->data, 1);
3177 if (rtwsta->cctl_tx_time) {
3178 SET_CMC_TBL_AMPDU_TIME_SEL(skb->data, 1);
3179 SET_CMC_TBL_AMPDU_MAX_TIME(skb->data, rtwsta->ampdu_max_time);
3181 if (rtwsta->cctl_tx_retry_limit) {
3182 SET_CMC_TBL_DATA_TXCNT_LMT_SEL(skb->data, 1);
3183 SET_CMC_TBL_DATA_TX_CNT_LMT(skb->data, rtwsta->data_tx_cnt_lmt);
3188 chip->h2c_cctl_func_id, 0, 1,
3207 const struct rtw89_chip_info *chip = rtwdev->chip;
3211 if (chip->h2c_cctl_func_id != H2C_FUNC_MAC_CCTLINFO_UD)
3217 return -ENOMEM;
3220 SET_CTRL_INFO_MACID(skb->data, rtwsta->mac_id);
3221 SET_CTRL_INFO_OPERATION(skb->data, 1);
3247 rtwvif->sub_entity_idx);
3261 if (vif->p2p)
3263 else if (chan->band_type == RTW89_BAND_2G)
3268 skb_beacon = ieee80211_beacon_get_tim(rtwdev->hw, vif, &tim_offset,
3272 return -ENOMEM;
3283 tim_offset -= ieee80211_hdrlen(hdr->frame_control);
3285 bcn_total_len = len + skb_beacon->len;
3290 return -ENOMEM;
3293 h2c = (struct rtw89_h2c_bcn_upd *)skb->data;
3295 h2c->w0 = le32_encode_bits(rtwvif->port, RTW89_H2C_BCN_UPD_W0_PORT) |
3297 le32_encode_bits(rtwvif->mac_idx, RTW89_H2C_BCN_UPD_W0_BAND) |
3299 h2c->w1 = le32_encode_bits(rtwvif->mac_id, RTW89_H2C_BCN_UPD_W1_MACID) |
3304 skb_put_data(skb, skb_beacon->data, skb_beacon->len);
3340 if (vif->p2p)
3342 else if (chan->band_type == RTW89_BAND_2G)
3347 skb_beacon = ieee80211_beacon_get_tim(rtwdev->hw, vif, &tim_offset,
3351 return -ENOMEM;
3362 tim_offset -= ieee80211_hdrlen(hdr->frame_control);
3364 bcn_total_len = len + skb_beacon->len;
3369 return -ENOMEM;
3372 h2c = (struct rtw89_h2c_bcn_upd_be *)skb->data;
3374 h2c->w0 = le32_encode_bits(rtwvif->port, RTW89_H2C_BCN_UPD_BE_W0_PORT) |
3376 le32_encode_bits(rtwvif->mac_idx, RTW89_H2C_BCN_UPD_BE_W0_BAND) |
3378 h2c->w1 = le32_encode_bits(rtwvif->mac_id, RTW89_H2C_BCN_UPD_BE_W1_MACID) |
3383 skb_put_data(skb, skb_beacon->data, skb_beacon->len);
3413 u8 mac_id = rtwsta ? rtwsta->mac_id : rtwvif->mac_id;
3417 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) {
3421 self_role = rtwvif->self_role;
3423 self_role = rtwvif->self_role;
3429 return -ENOMEM;
3432 SET_FWROLE_MAINTAIN_MACID(skb->data, mac_id);
3433 SET_FWROLE_MAINTAIN_SELF_ROLE(skb->data, self_role);
3434 SET_FWROLE_MAINTAIN_UPD_MODE(skb->data, upd_mode);
3435 SET_FWROLE_MAINTAIN_WIFI_ROLE(skb->data, rtwvif->wifi_role);
3465 if (sta->deflink.eht_cap.has_eht)
3467 else if (sta->deflink.he_cap.has_he)
3473 if (vif->bss_conf.eht_support)
3475 else if (vif->bss_conf.he_support)
3485 u8 mac_id = rtwsta ? rtwsta->mac_id : rtwvif->mac_id;
3486 u8 self_role = rtwvif->self_role;
3488 u8 net_type = rtwvif->net_type;
3495 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
3508 return -ENOMEM;
3511 h2c = (struct rtw89_h2c_join *)skb->data;
3513 h2c->w0 = le32_encode_bits(mac_id, RTW89_H2C_JOININFO_W0_MACID) |
3515 le32_encode_bits(rtwvif->mac_idx, RTW89_H2C_JOININFO_W0_BAND) |
3516 le32_encode_bits(rtwvif->wmm, RTW89_H2C_JOININFO_W0_WMM) |
3517 le32_encode_bits(rtwvif->trigger, RTW89_H2C_JOININFO_W0_TGR) |
3522 le32_encode_bits(rtwvif->port, RTW89_H2C_JOININFO_W0_PORT_ID) |
3524 le32_encode_bits(rtwvif->wifi_role, RTW89_H2C_JOININFO_W0_WIFI_ROLE) |
3530 h2c_v1 = (struct rtw89_h2c_join_v1 *)skb->data;
3534 h2c_v1->w1 = le32_encode_bits(sta_type, RTW89_H2C_JOININFO_W1_STA_TYPE);
3535 h2c_v1->w2 = 0;
3566 return -ENOMEM;
3569 h2c = (struct rtw89_h2c_notify_dbcc *)skb->data;
3571 h2c->w0 = le32_encode_bits(en, RTW89_H2C_NOTIFY_DBCC_EN);
3602 if (RTW89_CHK_FW_FEATURE(MACID_PAUSE_SLEEP, &rtwdev->fw)) {
3613 return -ENOMEM;
3618 h2c_new = (struct rtw89_fw_macid_pause_sleep_grp *)skb->data;
3620 h2c_new->n[0].pause_mask_grp[grp] = set;
3621 h2c_new->n[0].sleep_mask_grp[grp] = set;
3623 h2c_new->n[0].pause_grp[grp] = set;
3624 h2c_new->n[0].sleep_grp[grp] = set;
3627 h2c = (struct rtw89_fw_macid_pause_grp *)skb->data;
3629 h2c->mask_grp[grp] = set;
3631 h2c->pause_grp[grp] = set;
3662 return -ENOMEM;
3665 RTW89_SET_EDCA_SEL(skb->data, 0);
3666 RTW89_SET_EDCA_BAND(skb->data, rtwvif->mac_idx);
3667 RTW89_SET_EDCA_WMM(skb->data, 0);
3668 RTW89_SET_EDCA_AC(skb->data, ac);
3669 RTW89_SET_EDCA_PARAM(skb->data, val);
3701 return -ENOMEM;
3704 cmd = skb->data;
3706 RTW89_SET_FWCMD_TSF32_TOGL_BAND(cmd, rtwvif->mac_idx);
3708 RTW89_SET_FWCMD_TSF32_TOGL_PORT(cmd, rtwvif->port);
3739 return -ENOMEM;
3766 struct ieee80211_bss_conf *bss_conf = vif ? &vif->bss_conf : NULL;
3774 if (!RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
3775 return -EINVAL;
3777 if (!rtwvif || !bss_conf || rtwvif->net_type != RTW89_NET_TYPE_INFRA)
3778 return -EINVAL;
3783 return -ENOMEM;
3787 h2c = (struct rtw89_h2c_bcnfltr *)skb->data;
3789 if (bss_conf->cqm_rssi_hyst)
3790 hyst = bss_conf->cqm_rssi_hyst;
3791 if (bss_conf->cqm_rssi_thold)
3792 thold = bss_conf->cqm_rssi_thold;
3794 h2c->w0 = le32_encode_bits(connect, RTW89_H2C_BCNFLTR_W0_MON_RSSI) |
3803 le32_encode_bits(rtwvif->mac_id, RTW89_H2C_BCNFLTR_W0_MAC_ID);
3831 if (!RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
3832 return -EINVAL;
3835 return -EINVAL;
3840 return -ENOMEM;
3843 rssi = phy_ppdu->rssi_avg >> RSSI_FACTOR;
3845 h2c = (struct rtw89_h2c_ofld_rssi *)skb->data;
3847 h2c->w0 = le32_encode_bits(phy_ppdu->mac_id, RTW89_H2C_OFLD_RSSI_W0_MACID) |
3849 h2c->w1 = le32_encode_bits(rssi, RTW89_H2C_OFLD_RSSI_W1_VAL);
3870 struct rtw89_traffic_stats *stats = &rtwvif->stats;
3876 if (rtwvif->net_type != RTW89_NET_TYPE_INFRA)
3877 return -EINVAL;
3882 return -ENOMEM;
3886 h2c = (struct rtw89_h2c_ofld *)skb->data;
3888 h2c->w0 = le32_encode_bits(rtwvif->mac_id, RTW89_H2C_OFLD_W0_MAC_ID) |
3889 le32_encode_bits(stats->tx_throughput, RTW89_H2C_OFLD_W0_TX_TP) |
3890 le32_encode_bits(stats->rx_throughput, RTW89_H2C_OFLD_W0_RX_TP);
3911 const struct rtw89_chip_info *chip = rtwdev->chip;
3919 if (chip->chip_gen == RTW89_CHIP_BE) {
3927 return -ENOMEM;
3930 h2c = (struct rtw89_h2c_ra *)skb->data;
3933 "ra cmd msk: %llx ", ra->ra_mask);
3935 "ra cmd msk: %jx ", (uintmax_t)ra->ra_mask);
3938 h2c->w0 = le32_encode_bits(ra->mode_ctrl, RTW89_H2C_RA_W0_MODE) |
3939 le32_encode_bits(ra->bw_cap, RTW89_H2C_RA_W0_BW_CAP) |
3940 le32_encode_bits(ra->macid, RTW89_H2C_RA_W0_MACID) |
3941 le32_encode_bits(ra->dcm_cap, RTW89_H2C_RA_W0_DCM) |
3942 le32_encode_bits(ra->er_cap, RTW89_H2C_RA_W0_ER) |
3943 le32_encode_bits(ra->init_rate_lv, RTW89_H2C_RA_W0_INIT_RATE_LV) |
3944 le32_encode_bits(ra->upd_all, RTW89_H2C_RA_W0_UPD_ALL) |
3945 le32_encode_bits(ra->en_sgi, RTW89_H2C_RA_W0_SGI) |
3946 le32_encode_bits(ra->ldpc_cap, RTW89_H2C_RA_W0_LDPC) |
3947 le32_encode_bits(ra->stbc_cap, RTW89_H2C_RA_W0_STBC) |
3948 le32_encode_bits(ra->ss_num, RTW89_H2C_RA_W0_SS_NUM) |
3949 le32_encode_bits(ra->giltf, RTW89_H2C_RA_W0_GILTF) |
3950 le32_encode_bits(ra->upd_bw_nss_mask, RTW89_H2C_RA_W0_UPD_BW_NSS_MASK) |
3951 le32_encode_bits(ra->upd_mask, RTW89_H2C_RA_W0_UPD_MASK);
3952 h2c->w1 = le32_encode_bits(ra->ra_mask, RTW89_H2C_RA_W1_RAMASK_LO32);
3953 h2c->w2 = le32_encode_bits(ra->ra_mask >> 32, RTW89_H2C_RA_W2_RAMASK_HI32);
3954 h2c->w3 = le32_encode_bits(ra->fix_giltf_en, RTW89_H2C_RA_W3_FIX_GILTF_EN) |
3955 le32_encode_bits(ra->fix_giltf, RTW89_H2C_RA_W3_FIX_GILTF);
3961 h2c_v1->w4 = le32_encode_bits(ra->mode_ctrl, RTW89_H2C_RA_V1_W4_MODE_EHT) |
3962 le32_encode_bits(ra->bw_cap, RTW89_H2C_RA_V1_W4_BW_EHT);
3968 h2c->w2 |= le32_encode_bits(1, RTW89_H2C_RA_W2_BFEE_CSI_CTL);
3969 h2c->w3 |= le32_encode_bits(ra->band_num, RTW89_H2C_RA_W3_BAND_NUM) |
3970 le32_encode_bits(ra->cr_tbl_sel, RTW89_H2C_RA_W3_CR_TBL_SEL) |
3971 le32_encode_bits(ra->fixed_csi_rate_en, RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN) |
3972 le32_encode_bits(ra->ra_csi_rate_en, RTW89_H2C_RA_W3_RA_CSI_RATE_EN) |
3973 le32_encode_bits(ra->csi_mcs_ss_idx, RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX) |
3974 le32_encode_bits(ra->csi_mode, RTW89_H2C_RA_W3_FIXED_CSI_MODE) |
3975 le32_encode_bits(ra->csi_gi_ltf, RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF) |
3976 le32_encode_bits(ra->csi_bw, RTW89_H2C_RA_W3_FIXED_CSI_BW);
3999 struct rtw89_btc *btc = &rtwdev->btc;
4000 struct rtw89_btc_dm *dm = &btc->dm;
4001 struct rtw89_btc_init_info *init_info = &dm->init_info.init;
4002 struct rtw89_btc_module *module = &init_info->module;
4003 struct rtw89_btc_ant_info *ant = &module->ant;
4012 return -ENOMEM;
4015 h2c = (struct rtw89_h2c_cxinit *)skb->data;
4017 h2c->hdr.type = type;
4018 h2c->hdr.len = len - H2C_LEN_CXDRVHDR;
4020 h2c->ant_type = ant->type;
4021 h2c->ant_num = ant->num;
4022 h2c->ant_iso = ant->isolation;
4023 h2c->ant_info =
4024 u8_encode_bits(ant->single_pos, RTW89_H2C_CXINIT_ANT_INFO_POS) |
4025 u8_encode_bits(ant->diversity, RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY) |
4026 u8_encode_bits(ant->btg_pos, RTW89_H2C_CXINIT_ANT_INFO_BTG_POS) |
4027 u8_encode_bits(ant->stream_cnt, RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT);
4029 h2c->mod_rfe = module->rfe_type;
4030 h2c->mod_cv = module->cv;
4031 h2c->mod_info =
4032 u8_encode_bits(module->bt_solo, RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO) |
4033 u8_encode_bits(module->bt_pos, RTW89_H2C_CXINIT_MOD_INFO_BT_POS) |
4034 u8_encode_bits(module->switch_type, RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE) |
4035 u8_encode_bits(module->wa_type, RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE);
4036 h2c->mod_adie_kt = module->kt_ver_adie;
4037 h2c->wl_gch = init_info->wl_guard_ch;
4039 h2c->info =
4040 u8_encode_bits(init_info->wl_only, RTW89_H2C_CXINIT_INFO_WL_ONLY) |
4041 u8_encode_bits(init_info->wl_init_ok, RTW89_H2C_CXINIT_INFO_WL_INITOK) |
4042 u8_encode_bits(init_info->dbcc_en, RTW89_H2C_CXINIT_INFO_DBCC_EN) |
4043 u8_encode_bits(init_info->cx_other, RTW89_H2C_CXINIT_INFO_CX_OTHER) |
4044 u8_encode_bits(init_info->bt_only, RTW89_H2C_CXINIT_INFO_BT_ONLY);
4066 struct rtw89_btc *btc = &rtwdev->btc;
4067 struct rtw89_btc_dm *dm = &btc->dm;
4068 struct rtw89_btc_init_info_v7 *init_info = &dm->init_info.init_v7;
4077 return -ENOMEM;
4080 h2c = (struct rtw89_h2c_cxinit_v7 *)skb->data;
4082 h2c->hdr.type = type;
4083 h2c->hdr.ver = btc->ver->fcxinit;
4084 h2c->hdr.len = len - H2C_LEN_CXDRVHDR_V7;
4085 h2c->init = *init_info;
4112 struct rtw89_btc *btc = &rtwdev->btc;
4113 const struct rtw89_btc_ver *ver = btc->ver;
4114 struct rtw89_btc_wl_info *wl = &btc->cx.wl;
4115 struct rtw89_btc_wl_role_info *role_info = &wl->role_info;
4116 struct rtw89_btc_wl_role_info_bpos *bpos = &role_info->role_map.role;
4117 struct rtw89_btc_wl_active_role *active = role_info->active_role;
4125 len = H2C_LEN_CXDRVINFO_ROLE_SIZE(ver->max_role_num);
4130 return -ENOMEM;
4133 cmd = skb->data;
4136 RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR);
4138 RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt);
4139 RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, role_info->link_mode);
4141 RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, bpos->none);
4142 RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, bpos->station);
4143 RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, bpos->ap);
4144 RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, bpos->vap);
4145 RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, bpos->adhoc);
4146 RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, bpos->adhoc_master);
4147 RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, bpos->mesh);
4148 RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, bpos->moniter);
4149 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, bpos->p2p_device);
4150 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, bpos->p2p_gc);
4151 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, bpos->p2p_go);
4152 RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, bpos->nan);
4155 RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, active->connected, i, offset);
4156 RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, active->pid, i, offset);
4157 RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, active->phy, i, offset);
4158 RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, active->noa, i, offset);
4159 RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, active->band, i, offset);
4160 RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, active->client_ps, i, offset);
4161 RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, active->bw, i, offset);
4162 RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, active->role, i, offset);
4163 RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, active->ch, i, offset);
4164 RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, active->tx_lvl, i, offset);
4165 RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, active->rx_lvl, i, offset);
4166 RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, active->tx_rate, i, offset);
4167 RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, active->rx_rate, i, offset);
4193 struct rtw89_btc *btc = &rtwdev->btc;
4194 const struct rtw89_btc_ver *ver = btc->ver;
4195 struct rtw89_btc_wl_info *wl = &btc->cx.wl;
4196 struct rtw89_btc_wl_role_info_v1 *role_info = &wl->role_info_v1;
4197 struct rtw89_btc_wl_role_info_bpos *bpos = &role_info->role_map.role;
4198 struct rtw89_btc_wl_active_role_v1 *active = role_info->active_role_v1;
4205 len = H2C_LEN_CXDRVINFO_ROLE_SIZE_V1(ver->max_role_num);
4210 return -ENOMEM;
4213 cmd = skb->data;
4216 RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR);
4218 RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt);
4219 RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, role_info->link_mode);
4221 RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, bpos->none);
4222 RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, bpos->station);
4223 RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, bpos->ap);
4224 RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, bpos->vap);
4225 RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, bpos->adhoc);
4226 RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, bpos->adhoc_master);
4227 RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, bpos->mesh);
4228 RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, bpos->moniter);
4229 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, bpos->p2p_device);
4230 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, bpos->p2p_gc);
4231 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, bpos->p2p_go);
4232 RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, bpos->nan);
4236 RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, active->connected, i, offset);
4237 RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, active->pid, i, offset);
4238 RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, active->phy, i, offset);
4239 RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, active->noa, i, offset);
4240 RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, active->band, i, offset);
4241 RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, active->client_ps, i, offset);
4242 RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, active->bw, i, offset);
4243 RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, active->role, i, offset);
4244 RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, active->ch, i, offset);
4245 RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, active->tx_lvl, i, offset);
4246 RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, active->rx_lvl, i, offset);
4247 RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, active->tx_rate, i, offset);
4248 RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, active->rx_rate, i, offset);
4249 RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(cmd, active->noa_duration, i, offset);
4252 offset = len - H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN;
4253 RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(cmd, role_info->mrole_type, offset);
4254 RTW89_SET_FWCMD_CXROLE_MROLE_NOA(cmd, role_info->mrole_noa_duration, offset);
4255 RTW89_SET_FWCMD_CXROLE_DBCC_EN(cmd, role_info->dbcc_en, offset);
4256 RTW89_SET_FWCMD_CXROLE_DBCC_CHG(cmd, role_info->dbcc_chg, offset);
4257 RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(cmd, role_info->dbcc_2g_phy, offset);
4258 RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(cmd, role_info->link_mode_chg, offset);
4283 struct rtw89_btc *btc = &rtwdev->btc;
4284 const struct rtw89_btc_ver *ver = btc->ver;
4285 struct rtw89_btc_wl_info *wl = &btc->cx.wl;
4286 struct rtw89_btc_wl_role_info_v2 *role_info = &wl->role_info_v2;
4287 struct rtw89_btc_wl_role_info_bpos *bpos = &role_info->role_map.role;
4288 struct rtw89_btc_wl_active_role_v2 *active = role_info->active_role_v2;
4295 len = H2C_LEN_CXDRVINFO_ROLE_SIZE_V2(ver->max_role_num);
4300 return -ENOMEM;
4303 cmd = skb->data;
4306 RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR);
4308 RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt);
4309 RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, role_info->link_mode);
4311 RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, bpos->none);
4312 RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, bpos->station);
4313 RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, bpos->ap);
4314 RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, bpos->vap);
4315 RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, bpos->adhoc);
4316 RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, bpos->adhoc_master);
4317 RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, bpos->mesh);
4318 RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, bpos->moniter);
4319 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, bpos->p2p_device);
4320 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, bpos->p2p_gc);
4321 RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, bpos->p2p_go);
4322 RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, bpos->nan);
4326 RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(cmd, active->connected, i, offset);
4327 RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(cmd, active->pid, i, offset);
4328 RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(cmd, active->phy, i, offset);
4329 RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(cmd, active->noa, i, offset);
4330 RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(cmd, active->band, i, offset);
4331 RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(cmd, active->client_ps, i, offset);
4332 RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(cmd, active->bw, i, offset);
4333 RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(cmd, active->role, i, offset);
4334 RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(cmd, active->ch, i, offset);
4335 RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(cmd, active->noa_duration, i, offset);
4338 offset = len - H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN;
4339 RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(cmd, role_info->mrole_type, offset);
4340 RTW89_SET_FWCMD_CXROLE_MROLE_NOA(cmd, role_info->mrole_noa_duration, offset);
4341 RTW89_SET_FWCMD_CXROLE_DBCC_EN(cmd, role_info->dbcc_en, offset);
4342 RTW89_SET_FWCMD_CXROLE_DBCC_CHG(cmd, role_info->dbcc_chg, offset);
4343 RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(cmd, role_info->dbcc_2g_phy, offset);
4344 RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(cmd, role_info->link_mode_chg, offset);
4366 struct rtw89_btc *btc = &rtwdev->btc;
4367 struct rtw89_btc_wl_role_info_v8 *role = &btc->cx.wl.role_info_v8;
4376 return -ENOMEM;
4379 h2c = (struct rtw89_h2c_cxrole_v8 *)skb->data;
4381 h2c->hdr.type = type;
4382 h2c->hdr.len = len - H2C_LEN_CXDRVHDR_V7;
4383 memcpy(&h2c->_u8, role, sizeof(h2c->_u8));
4384 h2c->_u32.role_map = cpu_to_le32(role->role_map);
4385 h2c->_u32.mrole_type = cpu_to_le32(role->mrole_type);
4386 h2c->_u32.mrole_noa_duration = cpu_to_le32(role->mrole_noa_duration);
4409 struct rtw89_btc *btc = &rtwdev->btc;
4410 const struct rtw89_btc_ver *ver = btc->ver;
4411 struct rtw89_btc_ctrl *ctrl = &btc->ctrl.ctrl;
4419 return -ENOMEM;
4422 cmd = skb->data;
4425 RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_CTRL - H2C_LEN_CXDRVHDR);
4427 RTW89_SET_FWCMD_CXCTRL_MANUAL(cmd, ctrl->manual);
4428 RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(cmd, ctrl->igno_bt);
4429 RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(cmd, ctrl->always_freerun);
4430 if (ver->fcxctrl == 0)
4431 RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(cmd, ctrl->trace_step);
4453 struct rtw89_btc *btc = &rtwdev->btc;
4454 struct rtw89_btc_ctrl_v7 *ctrl = &btc->ctrl.ctrl_v7;
4463 return -ENOMEM;
4466 h2c = (struct rtw89_h2c_cxctrl_v7 *)skb->data;
4468 h2c->hdr.type = type;
4469 h2c->hdr.ver = btc->ver->fcxctrl;
4470 h2c->hdr.len = sizeof(*h2c) - H2C_LEN_CXDRVHDR_V7;
4471 h2c->ctrl = *ctrl;
4493 struct rtw89_btc *btc = &rtwdev->btc;
4494 struct rtw89_btc_trx_info *trx = &btc->dm.trx_info;
4502 return -ENOMEM;
4505 cmd = skb->data;
4508 RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_TRX - H2C_LEN_CXDRVHDR);
4510 RTW89_SET_FWCMD_CXTRX_TXLV(cmd, trx->tx_lvl);
4511 RTW89_SET_FWCMD_CXTRX_RXLV(cmd, trx->rx_lvl);
4512 RTW89_SET_FWCMD_CXTRX_WLRSSI(cmd, trx->wl_rssi);
4513 RTW89_SET_FWCMD_CXTRX_BTRSSI(cmd, trx->bt_rssi);
4514 RTW89_SET_FWCMD_CXTRX_TXPWR(cmd, trx->tx_power);
4515 RTW89_SET_FWCMD_CXTRX_RXGAIN(cmd, trx->rx_gain);
4516 RTW89_SET_FWCMD_CXTRX_BTTXPWR(cmd, trx->bt_tx_power);
4517 RTW89_SET_FWCMD_CXTRX_BTRXGAIN(cmd, trx->bt_rx_gain);
4518 RTW89_SET_FWCMD_CXTRX_CN(cmd, trx->cn);
4519 RTW89_SET_FWCMD_CXTRX_NHM(cmd, trx->nhm);
4520 RTW89_SET_FWCMD_CXTRX_BTPROFILE(cmd, trx->bt_profile);
4521 RTW89_SET_FWCMD_CXTRX_RSVD2(cmd, trx->rsvd2);
4522 RTW89_SET_FWCMD_CXTRX_TXRATE(cmd, trx->tx_rate);
4523 RTW89_SET_FWCMD_CXTRX_RXRATE(cmd, trx->rx_rate);
4524 RTW89_SET_FWCMD_CXTRX_TXTP(cmd, trx->tx_tp);
4525 RTW89_SET_FWCMD_CXTRX_RXTP(cmd, trx->rx_tp);
4526 RTW89_SET_FWCMD_CXTRX_RXERRRA(cmd, trx->rx_err_ratio);
4549 struct rtw89_btc *btc = &rtwdev->btc;
4550 struct rtw89_btc_wl_info *wl = &btc->cx.wl;
4551 struct rtw89_btc_wl_rfk_info *rfk_info = &wl->rfk_info;
4559 return -ENOMEM;
4562 cmd = skb->data;
4565 RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_RFK - H2C_LEN_CXDRVHDR);
4567 RTW89_SET_FWCMD_CXRFK_STATE(cmd, rfk_info->state);
4568 RTW89_SET_FWCMD_CXRFK_PATH_MAP(cmd, rfk_info->path_map);
4569 RTW89_SET_FWCMD_CXRFK_PHY_MAP(cmd, rfk_info->phy_map);
4570 RTW89_SET_FWCMD_CXRFK_BAND(cmd, rfk_info->band);
4571 RTW89_SET_FWCMD_CXRFK_TYPE(cmd, rfk_info->type);
4594 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
4603 return -ENOMEM;
4606 cmd = skb->data;
4626 rtw89_core_release_bit_map(rtwdev->pkt_offload, id);
4633 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
4640 alloc_id = rtw89_core_acquire_bit_map(rtwdev->pkt_offload,
4643 return -ENOSPC;
4647 skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_LEN_PKT_OFLD + skb_ofld->len);
4650 rtw89_core_release_bit_map(rtwdev->pkt_offload, alloc_id);
4651 return -ENOMEM;
4654 cmd = skb->data;
4658 RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(cmd, skb_ofld->len);
4659 skb_put_data(skb, skb_ofld->data, skb_ofld->len);
4664 H2C_LEN_PKT_OFLD + skb_ofld->len);
4673 rtw89_core_release_bit_map(rtwdev->pkt_offload, alloc_id);
4683 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
4698 return -ENOMEM;
4701 h2c = (struct rtw89_h2c_chinfo *)skb->data;
4703 h2c->ch_num = ch_num;
4704 h2c->elem_size = sizeof(*elem) / 4; /* in unit of 4 bytes */
4709 elem->w0 = le32_encode_bits(ch_info->period, RTW89_H2C_CHINFO_W0_PERIOD) |
4710 le32_encode_bits(ch_info->dwell_time, RTW89_H2C_CHINFO_W0_DWELL) |
4711 le32_encode_bits(ch_info->central_ch, RTW89_H2C_CHINFO_W0_CENTER_CH) |
4712 le32_encode_bits(ch_info->pri_ch, RTW89_H2C_CHINFO_W0_PRI_CH);
4714 elem->w1 = le32_encode_bits(ch_info->bw, RTW89_H2C_CHINFO_W1_BW) |
4715 le32_encode_bits(ch_info->notify_action, RTW89_H2C_CHINFO_W1_ACTION) |
4716 le32_encode_bits(ch_info->num_pkt, RTW89_H2C_CHINFO_W1_NUM_PKT) |
4717 le32_encode_bits(ch_info->tx_pkt, RTW89_H2C_CHINFO_W1_TX) |
4718 le32_encode_bits(ch_info->pause_data, RTW89_H2C_CHINFO_W1_PAUSE_DATA) |
4719 le32_encode_bits(ch_info->ch_band, RTW89_H2C_CHINFO_W1_BAND) |
4720 le32_encode_bits(ch_info->probe_id, RTW89_H2C_CHINFO_W1_PKT_ID) |
4721 le32_encode_bits(ch_info->dfs_ch, RTW89_H2C_CHINFO_W1_DFS) |
4722 le32_encode_bits(ch_info->tx_null, RTW89_H2C_CHINFO_W1_TX_NULL) |
4723 le32_encode_bits(ch_info->rand_seq_num, RTW89_H2C_CHINFO_W1_RANDOM);
4725 elem->w2 = le32_encode_bits(ch_info->pkt_id[0], RTW89_H2C_CHINFO_W2_PKT0) |
4726 le32_encode_bits(ch_info->pkt_id[1], RTW89_H2C_CHINFO_W2_PKT1) |
4727 le32_encode_bits(ch_info->pkt_id[2], RTW89_H2C_CHINFO_W2_PKT2) |
4728 le32_encode_bits(ch_info->pkt_id[3], RTW89_H2C_CHINFO_W2_PKT3);
4730 elem->w3 = le32_encode_bits(ch_info->pkt_id[4], RTW89_H2C_CHINFO_W3_PKT4) |
4731 le32_encode_bits(ch_info->pkt_id[5], RTW89_H2C_CHINFO_W3_PKT5) |
4732 le32_encode_bits(ch_info->pkt_id[6], RTW89_H2C_CHINFO_W3_PKT6) |
4733 le32_encode_bits(ch_info->pkt_id[7], RTW89_H2C_CHINFO_W3_PKT7);
4754 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
4769 return -ENOMEM;
4773 h2c = (struct rtw89_h2c_chinfo *)skb->data;
4775 h2c->ch_num = ch_num;
4776 h2c->elem_size = sizeof(*elem) / 4; /* in unit of 4 bytes */
4777 h2c->arg = u8_encode_bits(RTW89_PHY_0, RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK);
4782 elem->w0 = le32_encode_bits(ch_info->period, RTW89_H2C_CHINFO_BE_W0_PERIOD) |
4783 le32_encode_bits(ch_info->dwell_time, RTW89_H2C_CHINFO_BE_W0_DWELL) |
4784 le32_encode_bits(ch_info->central_ch,
4786 le32_encode_bits(ch_info->pri_ch, RTW89_H2C_CHINFO_BE_W0_PRI_CH);
4788 elem->w1 = le32_encode_bits(ch_info->bw, RTW89_H2C_CHINFO_BE_W1_BW) |
4789 le32_encode_bits(ch_info->ch_band, RTW89_H2C_CHINFO_BE_W1_CH_BAND) |
4790 le32_encode_bits(ch_info->dfs_ch, RTW89_H2C_CHINFO_BE_W1_DFS) |
4791 le32_encode_bits(ch_info->pause_data,
4793 le32_encode_bits(ch_info->tx_null, RTW89_H2C_CHINFO_BE_W1_TX_NULL) |
4794 le32_encode_bits(ch_info->rand_seq_num,
4796 le32_encode_bits(ch_info->notify_action,
4798 le32_encode_bits(ch_info->probe_id != 0xff ? 1 : 0,
4800 le32_encode_bits(ch_info->leave_crit,
4802 le32_encode_bits(ch_info->chkpt_timer,
4805 elem->w2 = le32_encode_bits(ch_info->leave_time,
4807 le32_encode_bits(ch_info->leave_th,
4809 le32_encode_bits(ch_info->tx_pkt_ctrl,
4812 elem->w3 = le32_encode_bits(ch_info->pkt_id[0], RTW89_H2C_CHINFO_BE_W3_PKT0) |
4813 le32_encode_bits(ch_info->pkt_id[1], RTW89_H2C_CHINFO_BE_W3_PKT1) |
4814 le32_encode_bits(ch_info->pkt_id[2], RTW89_H2C_CHINFO_BE_W3_PKT2) |
4815 le32_encode_bits(ch_info->pkt_id[3], RTW89_H2C_CHINFO_BE_W3_PKT3);
4817 elem->w4 = le32_encode_bits(ch_info->pkt_id[4], RTW89_H2C_CHINFO_BE_W4_PKT4) |
4818 le32_encode_bits(ch_info->pkt_id[5], RTW89_H2C_CHINFO_BE_W4_PKT5) |
4819 le32_encode_bits(ch_info->pkt_id[6], RTW89_H2C_CHINFO_BE_W4_PKT6) |
4820 le32_encode_bits(ch_info->pkt_id[7], RTW89_H2C_CHINFO_BE_W4_PKT7);
4822 elem->w5 = le32_encode_bits(ch_info->sw_def, RTW89_H2C_CHINFO_BE_W5_SW_DEF) |
4823 le32_encode_bits(ch_info->fw_probe0_ssids,
4826 elem->w6 = le32_encode_bits(ch_info->fw_probe0_shortssids,
4828 le32_encode_bits(ch_info->fw_probe0_bssids,
4851 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
4852 struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
4862 return -ENOMEM;
4865 h2c = (struct rtw89_h2c_scanofld *)skb->data;
4867 h2c->w0 = le32_encode_bits(rtwvif->mac_id, RTW89_H2C_SCANOFLD_W0_MACID) |
4868 le32_encode_bits(rtwvif->port, RTW89_H2C_SCANOFLD_W0_PORT_ID) |
4870 le32_encode_bits(option->enable, RTW89_H2C_SCANOFLD_W0_OPERATION);
4872 h2c->w1 = le32_encode_bits(true, RTW89_H2C_SCANOFLD_W1_NOTIFY_END) |
4873 le32_encode_bits(option->target_ch_mode,
4879 if (option->target_ch_mode) {
4880 h2c->w1 |= le32_encode_bits(op->band_width,
4882 le32_encode_bits(op->primary_channel,
4884 le32_encode_bits(op->channel,
4886 h2c->w0 |= le32_encode_bits(op->band_type,
4895 if (option->enable)
4916 sband = rtwdev->hw->wiphy->bands[NL80211_BAND_6GHZ];
4918 option->prohib_chan = U64_MAX;
4922 for (i = 0; i < sband->n_channels; i++) {
4923 chan = &sband->channels[i];
4924 if (chan->flags & IEEE80211_CHAN_DISABLED) {
4925 idx = (chan->hw_value - 1) / 4;
4926 option->prohib_chan |= BIT(idx);
4935 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
4936 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
4937 struct cfg80211_scan_request *req = rtwvif->scan_req;
4939 struct rtw89_chan *op = &scan_info->op_chan;
4944 u8 macc_role_size = sizeof(*macc_role) * option->num_macc_role;
4945 u8 opch_size = sizeof(*opch) * option->num_opch;
4963 return -ENOMEM;
4967 h2c = (struct rtw89_h2c_scanofld_be *)skb->data;
4968 ptr = skb->data;
4972 list_for_each_entry(pkt_info, &scan_info->pkt_list[NL80211_BAND_6GHZ], list) {
4973 if (pkt_info->wildcard_6ghz) {
4975 probe_id[NL80211_BAND_6GHZ] = pkt_info->id;
4980 h2c->w0 = le32_encode_bits(option->operation, RTW89_H2C_SCANOFLD_BE_W0_OP) |
4981 le32_encode_bits(option->scan_mode,
4983 le32_encode_bits(option->repeat, RTW89_H2C_SCANOFLD_BE_W0_REPEAT) |
4986 le32_encode_bits(rtwvif->mac_id, RTW89_H2C_SCANOFLD_BE_W0_MACID) |
4987 le32_encode_bits(rtwvif->port, RTW89_H2C_SCANOFLD_BE_W0_PORT) |
4988 le32_encode_bits(option->band, RTW89_H2C_SCANOFLD_BE_W0_BAND);
4990 h2c->w1 = le32_encode_bits(option->num_macc_role, RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE) |
4991 le32_encode_bits(option->num_opch, RTW89_H2C_SCANOFLD_BE_W1_NUM_OP) |
4992 le32_encode_bits(option->norm_pd, RTW89_H2C_SCANOFLD_BE_W1_NORM_PD);
4994 h2c->w2 = le32_encode_bits(option->slow_pd, RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD) |
4995 le32_encode_bits(option->norm_cy, RTW89_H2C_SCANOFLD_BE_W2_NORM_CY) |
4996 le32_encode_bits(option->opch_end, RTW89_H2C_SCANOFLD_BE_W2_OPCH_END);
4998 h2c->w3 = le32_encode_bits(0, RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID) |
5003 h2c->w4 = le32_encode_bits(probe_id[NL80211_BAND_5GHZ],
5009 h2c->w5 = le32_encode_bits(option->mlo_mode, RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE);
5011 h2c->w6 = le32_encode_bits(option->prohib_chan,
5013 h2c->w7 = le32_encode_bits(option->prohib_chan >> 32,
5015 if (req->no_cck) {
5016 h2c->w0 |= le32_encode_bits(true, RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE);
5017 h2c->w8 = le32_encode_bits(RTW89_HW_RATE_OFDM6,
5026 for (i = 0; i < option->num_macc_role; i++) {
5027 macc_role = (struct rtw89_h2c_scanofld_be_macc_role *)&h2c->role[i];
5028 macc_role->w0 =
5036 for (i = 0; i < option->num_opch; i++) {
5042 opch->w0 = le32_encode_bits(rtwvif->mac_id,
5044 le32_encode_bits(option->band,
5046 le32_encode_bits(rtwvif->port,
5055 opch->w1 = le32_encode_bits(RTW89_CHANNEL_TIME,
5057 le32_encode_bits(op->band_type,
5059 le32_encode_bits(op->band_width,
5063 le32_encode_bits(op->primary_channel,
5065 le32_encode_bits(op->channel,
5068 opch->w2 = le32_encode_bits(0,
5075 opch->w3 = le32_encode_bits(RTW89_SCANOFLD_PKT_NONE,
5091 if (option->enable)
5110 u8 class = info->rf_path == RF_PATH_A ?
5117 return -ENOMEM;
5119 skb_put_data(skb, info->rtw89_phy_config_rf_h2c[page], len);
5140 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
5149 return -ENOMEM;
5152 mccch = (struct rtw89_fw_h2c_rf_get_mccch *)skb->data;
5154 idx = rfk_mcc->table_idx;
5155 mccch->ch_0 = cpu_to_le32(rfk_mcc->ch[0]);
5156 mccch->ch_1 = cpu_to_le32(rfk_mcc->ch[1]);
5157 mccch->band_0 = cpu_to_le32(rfk_mcc->band[0]);
5158 mccch->band_1 = cpu_to_le32(rfk_mcc->band[1]);
5159 mccch->current_channel = cpu_to_le32(rfk_mcc->ch[idx]);
5160 mccch->current_band_type = cpu_to_le32(rfk_mcc->band[idx]);
5184 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
5186 u8 tbl_sel = rfk_mcc->table_idx;
5196 return -ENOMEM;
5199 h2c = (struct rtw89_fw_h2c_rfk_pre_info *)skb->data;
5201 h2c->mlo_mode = cpu_to_le32(rtwdev->mlo_dbcc_mode);
5207 h2c->dbcc.ch[path][tbl] = cpu_to_le32(rfk_mcc->ch[tbl]);
5208 h2c->dbcc.band[path][tbl] = cpu_to_le32(rfk_mcc->band[tbl]);
5213 h2c->tbl.cur_ch[path] = cpu_to_le32(rfk_mcc->ch[tbl_sel]);
5214 h2c->tbl.cur_band[path] = cpu_to_le32(rfk_mcc->band[tbl_sel]);
5217 h2c->phy_idx = cpu_to_le32(phy_idx);
5218 h2c->cur_band = cpu_to_le32(rfk_mcc->band[tbl_sel]);
5219 h2c->cur_bw = cpu_to_le32(rfk_mcc->bw[tbl_sel]);
5220 h2c->cur_center_ch = cpu_to_le32(rfk_mcc->ch[tbl_sel]);
5223 h2c->ktbl_sel0 = cpu_to_le32(val32);
5225 h2c->ktbl_sel1 = cpu_to_le32(val32);
5227 h2c->rfmod0 = cpu_to_le32(val32);
5229 h2c->rfmod1 = cpu_to_le32(val32);
5232 h2c->mlo_1_1 = cpu_to_le32(1);
5234 h2c->rfe_type = cpu_to_le32(rtwdev->efuse.rfe_type);
5259 struct rtw89_hal *hal = &rtwdev->hal;
5268 return -ENOMEM;
5271 h2c = (struct rtw89_h2c_rf_tssi *)skb->data;
5273 h2c->len = cpu_to_le16(len);
5274 h2c->phy = phy_idx;
5275 h2c->ch = chan->channel;
5276 h2c->bw = chan->band_width;
5277 h2c->band = chan->band_type;
5278 h2c->hwtx_en = true;
5279 h2c->cv = hal->cv;
5280 h2c->tssi_mode = tssi_mode;
5312 return -ENOMEM;
5315 h2c = (struct rtw89_h2c_rf_iqk *)skb->data;
5317 h2c->phy_idx = cpu_to_le32(phy_idx);
5318 h2c->dbcc = cpu_to_le32(rtwdev->dbcc_en);
5349 return -ENOMEM;
5352 h2c = (struct rtw89_h2c_rf_dpk *)skb->data;
5354 h2c->len = len;
5355 h2c->phy = phy_idx;
5356 h2c->dpk_enable = true;
5357 h2c->kpath = RF_AB;
5358 h2c->cur_band = chan->band_type;
5359 h2c->cur_bw = chan->band_width;
5360 h2c->cur_ch = chan->channel;
5361 h2c->dpk_dbg_en = rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK);
5384 struct rtw89_hal *hal = &rtwdev->hal;
5393 return -ENOMEM;
5396 h2c = (struct rtw89_h2c_rf_txgapk *)skb->data;
5398 h2c->len = len;
5399 h2c->ktype = 2;
5400 h2c->phy = phy_idx;
5401 h2c->kpath = RF_AB;
5402 h2c->band = chan->band_type;
5403 h2c->bw = chan->band_width;
5404 h2c->ch = chan->channel;
5405 h2c->cv = hal->cv;
5434 return -ENOMEM;
5437 h2c = (struct rtw89_h2c_rf_dack *)skb->data;
5439 h2c->len = cpu_to_le32(len);
5440 h2c->phy = cpu_to_le32(phy_idx);
5441 h2c->type = cpu_to_le32(0);
5472 return -ENOMEM;
5475 h2c = (struct rtw89_h2c_rf_rxdck *)skb->data;
5477 h2c->len = len;
5478 h2c->phy = phy_idx;
5479 h2c->is_afe = false;
5480 h2c->kpath = RF_AB;
5481 h2c->cur_band = chan->band_type;
5482 h2c->cur_bw = chan->band_width;
5483 h2c->cur_ch = chan->channel;
5484 h2c->rxdck_dbg_en = rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK);
5513 return -ENOMEM;
5542 return -ENOMEM;
5563 lockdep_assert_held(&rtwdev->mutex);
5565 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) {
5566 rtw89_fw_h2c_raw(rtwdev, early_h2c->h2c, early_h2c->h2c_len);
5574 mutex_lock(&rtwdev->mutex);
5575 list_for_each_entry_safe(early_h2c, tmp, &rtwdev->early_h2c_list, list) {
5576 list_del(&early_h2c->list);
5577 kfree(early_h2c->h2c);
5580 mutex_unlock(&rtwdev->mutex);
5585 const struct rtw89_c2h_hdr *hdr = (const struct rtw89_c2h_hdr *)c2h->data;
5588 attr->category = le32_get_bits(hdr->w0, RTW89_C2H_HDR_W0_CATEGORY);
5589 attr->class = le32_get_bits(hdr->w0, RTW89_C2H_HDR_W0_CLASS);
5590 attr->func = le32_get_bits(hdr->w0, RTW89_C2H_HDR_W0_FUNC);
5591 attr->len = le32_get_bits(hdr->w1, RTW89_C2H_HDR_W1_LEN);
5598 u8 category = attr->category;
5599 u8 class = attr->class;
5600 u8 func = attr->func;
5623 skb_queue_tail(&rtwdev->c2h_queue, c2h);
5624 ieee80211_queue_work(rtwdev->hw, &rtwdev->c2h_work);
5631 u8 category = attr->category;
5632 u8 class = attr->class;
5633 u8 func = attr->func;
5634 u16 len = attr->len;
5637 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
5659 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "C2H: ", skb->data, skb->len);
5668 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
5669 skb_unlink(skb, &rtwdev->c2h_queue);
5670 mutex_lock(&rtwdev->mutex);
5672 mutex_unlock(&rtwdev->mutex);
5680 const struct rtw89_chip_info *chip = rtwdev->chip;
5681 struct rtw89_fw_info *fw_info = &rtwdev->fw;
5682 const u32 *h2c_reg = chip->h2c_regs;
5687 rtwdev, chip->h2c_ctrl_reg);
5693 len = DIV_ROUND_UP(info->content_len + RTW89_H2CREG_HDR_LEN,
5694 sizeof(info->u.h2creg[0]));
5696 u32p_replace_bits(&info->u.hdr.w0, info->id, RTW89_H2CREG_HDR_FUNC_MASK);
5697 u32p_replace_bits(&info->u.hdr.w0, len, RTW89_H2CREG_HDR_LEN_MASK);
5700 rtw89_write32(rtwdev, h2c_reg[i], info->u.h2creg[i]);
5702 fw_info->h2c_counter++;
5703 rtw89_write8_mask(rtwdev, chip->h2c_counter_reg.addr,
5704 chip->h2c_counter_reg.mask, fw_info->h2c_counter);
5705 rtw89_write8(rtwdev, chip->h2c_ctrl_reg, B_AX_H2CREG_TRIGGER);
5713 const struct rtw89_chip_info *chip = rtwdev->chip;
5714 struct rtw89_fw_info *fw_info = &rtwdev->fw;
5715 const u32 *c2h_reg = chip->c2h_regs;
5719 info->id = RTW89_FWCMD_C2HREG_FUNC_NULL;
5723 chip->c2h_ctrl_reg);
5730 info->u.c2hreg[i] = rtw89_read32(rtwdev, c2h_reg[i]);
5732 rtw89_write8(rtwdev, chip->c2h_ctrl_reg, 0);
5734 info->id = u32_get_bits(info->u.hdr.w0, RTW89_C2HREG_HDR_FUNC_MASK);
5735 info->content_len =
5736 (u32_get_bits(info->u.hdr.w0, RTW89_C2HREG_HDR_LEN_MASK) << 2) -
5739 fw_info->c2h_counter++;
5740 rtw89_write8_mask(rtwdev, chip->c2h_counter_reg.addr,
5741 chip->c2h_counter_reg.mask, fw_info->c2h_counter);
5752 if (h2c_info && h2c_info->id != RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE)
5753 lockdep_assert_held(&rtwdev->mutex);
5756 return -EINVAL;
5778 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
5779 rtw89_err(rtwdev, "[ERR]pwr is off\n");
5797 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
5802 if (!(rtwdev->chip->support_bands & BIT(idx)))
5806 if (test_bit(info->id, rtwdev->pkt_offload))
5807 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
5808 list_del(&info->list);
5819 struct cfg80211_scan_request *req = rtwvif->scan_req;
5824 if (req->ssids[ssid_idx].ssid_len) {
5825 memcpy(info->ssid, req->ssids[ssid_idx].ssid,
5826 req->ssids[ssid_idx].ssid_len);
5827 info->ssid_len = req->ssids[ssid_idx].ssid_len;
5830 info->wildcard_6ghz = true;
5839 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
5840 struct ieee80211_scan_ies *ies = rtwvif->scan_ies;
5847 if (!(rtwdev->chip->support_bands & BIT(band)))
5852 ret = -ENOMEM;
5855 skb_put_data(new, ies->ies[band], ies->len[band]);
5856 skb_put_data(new, ies->common_ies, ies->common_ie_len);
5860 ret = -ENOMEM;
5868 ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, new);
5875 list_add_tail(&info->list, &scan_info->pkt_list[band]);
5885 struct cfg80211_scan_request *req = rtwvif->scan_req;
5887 u8 num = req->n_ssids, i;
5891 skb = ieee80211_probereq_get(rtwdev->hw, rtwvif->mac_addr,
5892 req->ssids[i].ssid,
5893 req->ssids[i].ssid_len,
5894 req->ie_len);
5896 return -ENOMEM;
5912 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
5913 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
5915 struct ieee80211_scan_ies *ies = rtwvif->scan_ies;
5924 if (!req->n_6ghz_params)
5927 for (i = 0; i < req->n_6ghz_params; i++) {
5928 params = &req->scan_6ghz_params[i];
5930 if (req->channels[params->channel_idx]->hw_value !=
5931 ch_info->pri_ch)
5936 if (ether_addr_equal(tmp->bssid, params->bssid)) {
5944 skb = ieee80211_probereq_get(rtwdev->hw, rtwvif->mac_addr,
5945 NULL, 0, req->ie_len);
5946 skb_put_data(skb, ies->ies[NL80211_BAND_6GHZ], ies->len[NL80211_BAND_6GHZ]);
5947 skb_put_data(skb, ies->common_ies, ies->common_ie_len);
5948 hdr = (struct ieee80211_hdr *)skb->data;
5949 ether_addr_copy(hdr->addr3, params->bssid);
5953 ret = -ENOMEM;
5958 ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, skb);
5965 ether_addr_copy(info->bssid, params->bssid);
5966 info->channel_6ghz = req->channels[params->channel_idx]->hw_value;
5967 list_add_tail(&info->list, &rtwdev->scan_info.pkt_list[NL80211_BAND_6GHZ]);
5969 ch_info->tx_pkt = true;
5970 ch_info->period = RTW89_CHANNEL_TIME_6G + RTW89_DWELL_TIME_6G;
5983 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
5984 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
5985 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5986 struct cfg80211_scan_request *req = rtwvif->scan_req;
5987 struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
5992 ch_info->notify_action = RTW89_SCANOFLD_DEBUG_MASK;
5993 ch_info->dfs_ch = chan_type == RTW89_CHAN_DFS;
5994 ch_info->bw = RTW89_SCAN_WIDTH;
5995 ch_info->tx_pkt = true;
5996 ch_info->cfg_tx_pwr = false;
5997 ch_info->tx_pwr_idx = 0;
5998 ch_info->tx_null = false;
5999 ch_info->pause_data = false;
6000 ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
6002 if (ch_info->ch_band == RTW89_BAND_6G) {
6003 if ((ssid_num == 1 && req->ssids[0].ssid_len == 0) ||
6004 !ch_info->is_psc) {
6005 ch_info->tx_pkt = false;
6006 if (!req->duration_mandatory)
6007 ch_info->period -= RTW89_DWELL_TIME_6G;
6016 band = rtw89_hw_to_nl80211_band(ch_info->ch_band);
6018 list_for_each_entry(info, &scan_info->pkt_list[band], list) {
6019 if (info->channel_6ghz &&
6020 ch_info->pri_ch != info->channel_6ghz)
6022 else if (info->channel_6ghz && probe_count != 0)
6023 ch_info->period += RTW89_CHANNEL_TIME_6G;
6025 if (info->wildcard_6ghz)
6028 ch_info->pkt_id[probe_count++] = info->id;
6032 ch_info->num_pkt = probe_count;
6037 ch_info->central_ch = op->channel;
6038 ch_info->pri_ch = op->primary_channel;
6039 ch_info->ch_band = op->band_type;
6040 ch_info->bw = op->band_width;
6041 ch_info->tx_null = true;
6042 ch_info->num_pkt = 0;
6045 if (ch_info->ch_band != RTW89_BAND_6G)
6046 ch_info->period = max_t(u8, ch_info->period,
6048 ch_info->dwell_time = RTW89_DWELL_TIME;
6061 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
6062 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
6063 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
6064 struct cfg80211_scan_request *req = rtwvif->scan_req;
6068 ch_info->notify_action = RTW89_SCANOFLD_DEBUG_MASK;
6069 ch_info->dfs_ch = chan_type == RTW89_CHAN_DFS;
6070 ch_info->bw = RTW89_SCAN_WIDTH;
6071 ch_info->tx_null = false;
6072 ch_info->pause_data = false;
6073 ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
6076 band = rtw89_hw_to_nl80211_band(ch_info->ch_band);
6078 list_for_each_entry(info, &scan_info->pkt_list[band], list) {
6079 if (info->channel_6ghz &&
6080 ch_info->pri_ch != info->channel_6ghz)
6083 if (info->wildcard_6ghz)
6086 ch_info->pkt_id[probe_count++] = info->id;
6092 if (ch_info->ch_band == RTW89_BAND_6G) {
6093 if ((ssid_num == 1 && req->ssids[0].ssid_len == 0) ||
6094 !ch_info->is_psc) {
6095 ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
6096 if (!req->duration_mandatory)
6097 ch_info->period -= RTW89_DWELL_TIME_6G;
6102 ch_info->pkt_id[i] = RTW89_SCANOFLD_PKT_NONE;
6106 if (ch_info->ch_band != RTW89_BAND_6G)
6107 ch_info->period =
6108 max_t(u8, ch_info->period, RTW89_DFS_CHAN_TIME);
6109 ch_info->dwell_time = RTW89_DWELL_TIME;
6122 struct cfg80211_scan_request *req = rtwvif->scan_req;
6126 bool random_seq = req->flags & NL80211_SCAN_FLAG_RANDOM_SN;
6133 for (idx = rtwdev->scan_info.last_chan_idx, list_len = 0;
6134 idx < req->n_channels && list_len < RTW89_SCAN_LIST_LIMIT;
6136 channel = req->channels[idx];
6139 ret = -ENOMEM;
6143 if (req->duration)
6144 ch_info->period = req->duration;
6145 else if (channel->band == NL80211_BAND_6GHZ)
6146 ch_info->period = RTW89_CHANNEL_TIME_6G +
6149 ch_info->period = RTW89_CHANNEL_TIME;
6151 ch_info->ch_band = rtw89_nl80211_to_hw_band(channel->band);
6152 ch_info->central_ch = channel->hw_value;
6153 ch_info->pri_ch = channel->hw_value;
6154 ch_info->rand_seq_num = random_seq;
6155 ch_info->is_psc = cfg80211_channel_is_psc(channel);
6157 if (channel->flags &
6162 rtw89_hw_scan_add_chan(rtwdev, type, req->n_ssids, ch_info);
6165 off_chan_time + ch_info->period > RTW89_OFF_CHAN_TIME) {
6168 ret = -ENOMEM;
6174 tmp->period = req->duration_mandatory ?
6175 req->duration : RTW89_CHANNEL_TIME;
6177 list_add_tail(&tmp->list, &chan_list);
6181 list_add_tail(&ch_info->list, &chan_list);
6182 off_chan_time += ch_info->period;
6184 rtwdev->scan_info.last_chan_idx = idx;
6189 list_del(&ch_info->list);
6199 struct cfg80211_scan_request *req = rtwvif->scan_req;
6208 random_seq = !!(req->flags & NL80211_SCAN_FLAG_RANDOM_SN);
6211 for (idx = rtwdev->scan_info.last_chan_idx, list_len = 0;
6212 idx < req->n_channels && list_len < RTW89_SCAN_LIST_LIMIT;
6214 channel = req->channels[idx];
6217 ret = -ENOMEM;
6221 if (req->duration)
6222 ch_info->period = req->duration;
6223 else if (channel->band == NL80211_BAND_6GHZ)
6224 ch_info->period = RTW89_CHANNEL_TIME_6G + RTW89_DWELL_TIME_6G;
6226 ch_info->period = RTW89_CHANNEL_TIME;
6228 ch_info->ch_band = rtw89_nl80211_to_hw_band(channel->band);
6229 ch_info->central_ch = channel->hw_value;
6230 ch_info->pri_ch = channel->hw_value;
6231 ch_info->rand_seq_num = random_seq;
6232 ch_info->is_psc = cfg80211_channel_is_psc(channel);
6234 if (channel->flags & (IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR))
6238 rtw89_hw_scan_add_chan_be(rtwdev, type, req->n_ssids, ch_info);
6240 list_add_tail(&ch_info->list, &chan_list);
6243 rtwdev->scan_info.last_chan_idx = idx;
6248 list_del(&ch_info->list);
6258 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6270 ret = mac->add_chan_list(rtwdev, rtwvif, connected);
6278 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
6279 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6280 struct cfg80211_scan_request *req = &scan_req->req;
6281 u32 rx_fltr = rtwdev->hal.rx_fltr;
6284 rtw89_get_channel(rtwdev, rtwvif, &rtwdev->scan_info.op_chan);
6285 rtwdev->scan_info.scanning_vif = vif;
6286 rtwdev->scan_info.last_chan_idx = 0;
6287 rtwdev->scan_info.abort = false;
6288 rtwvif->scan_ies = &scan_req->ies;
6289 rtwvif->scan_req = req;
6290 ieee80211_stop_queues(rtwdev->hw);
6293 if (req->flags & NL80211_SCAN_FLAG_RANDOM_ADDR)
6294 get_random_mask_addr(mac_addr, req->mac_addr,
6295 req->mac_addr_mask);
6297 ether_addr_copy(mac_addr, vif->addr);
6304 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0),
6314 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6315 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
6325 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0),
6327 rtwdev->hal.rx_fltr);
6330 ieee80211_scan_completed(rtwdev->hw, &info);
6331 ieee80211_wake_queues(rtwdev->hw);
6336 rtwvif->scan_req = NULL;
6337 rtwvif->scan_ies = NULL;
6338 scan_info->last_chan_idx = 0;
6339 scan_info->scanning_vif = NULL;
6340 scan_info->abort = false;
6347 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
6350 scan_info->abort = true;
6370 if (!is_zero_ether_addr(rtwvif->bssid))
6380 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6386 rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
6388 return -EINVAL;
6399 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
6404 opt.mlo_mode = rtwdev->mlo_dbcc_mode;
6409 ret = mac->scan_offload(rtwdev, &opt, rtwvif);
6425 return -ENOMEM;
6429 RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(skb->data,
6462 return -ENOMEM;
6465 switch (params->sel) {
6474 "H2C of pkt drop might not fully support sel: %d yet\n",
6475 params->sel);
6480 RTW89_SET_FWCMD_PKT_DROP_SEL(skb->data, params->sel);
6481 RTW89_SET_FWCMD_PKT_DROP_MACID(skb->data, params->macid);
6482 RTW89_SET_FWCMD_PKT_DROP_BAND(skb->data, params->mac_band);
6483 RTW89_SET_FWCMD_PKT_DROP_PORT(skb->data, params->port);
6484 RTW89_SET_FWCMD_PKT_DROP_MBSSID(skb->data, params->mbssid);
6485 RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(skb->data, params->tf_trs);
6486 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(skb->data,
6487 params->macid_band_sel[0]);
6488 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(skb->data,
6489 params->macid_band_sel[1]);
6490 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(skb->data,
6491 params->macid_band_sel[2]);
6492 RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(skb->data,
6493 params->macid_band_sel[3]);
6527 return -EPERM;
6533 return -ENOMEM;
6538 RTW89_SET_KEEP_ALIVE_ENABLE(skb->data, enable);
6539 RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(skb->data, pkt_id);
6540 RTW89_SET_KEEP_ALIVE_PERIOD(skb->data, 5);
6541 RTW89_SET_KEEP_ALIVE_MACID(skb->data, rtwvif->mac_id);
6583 return -ENOMEM;
6587 h2c = (struct rtw89_h2c_arp_offload *)skb->data;
6589 h2c->w0 = le32_encode_bits(enable, RTW89_H2C_ARP_OFFLOAD_W0_ENABLE) |
6591 le32_encode_bits(rtwvif->mac_id, RTW89_H2C_ARP_OFFLOAD_W0_MACID) |
6618 struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
6620 u8 macid = rtwvif->mac_id;
6626 return -ENOMEM;
6631 if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags)) {
6632 RTW89_SET_DISCONNECT_DETECT_ENABLE(skb->data, enable);
6633 RTW89_SET_DISCONNECT_DETECT_DISCONNECT(skb->data, !enable);
6634 RTW89_SET_DISCONNECT_DETECT_MAC_ID(skb->data, macid);
6635 RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(skb->data, 100);
6636 RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(skb->data, 5);
6662 struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
6664 u8 macid = rtwvif->mac_id;
6672 return -ENOMEM;
6676 h2c = (struct rtw89_h2c_wow_global *)skb->data;
6678 h2c->w0 = le32_encode_bits(enable, RTW89_H2C_WOW_GLOBAL_W0_ENABLE) |
6680 le32_encode_bits(rtw_wow->ptk_alg,
6682 le32_encode_bits(rtw_wow->gtk_alg,
6684 h2c->key_info = rtw_wow->key_info;
6711 struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
6713 u8 macid = rtwvif->mac_id;
6719 return -ENOMEM;
6724 if (rtw_wow->pattern_cnt)
6725 RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(skb->data, enable);
6726 if (test_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags))
6727 RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(skb->data, enable);
6728 if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags))
6729 RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(skb->data, enable);
6731 RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(skb->data, macid);
6763 return -ENOMEM;
6768 RTW89_SET_WOW_CAM_UPD_R_W(skb->data, cam_info->r_w);
6769 RTW89_SET_WOW_CAM_UPD_IDX(skb->data, cam_info->idx);
6770 if (cam_info->valid) {
6771 RTW89_SET_WOW_CAM_UPD_WKFM1(skb->data, cam_info->mask[0]);
6772 RTW89_SET_WOW_CAM_UPD_WKFM2(skb->data, cam_info->mask[1]);
6773 RTW89_SET_WOW_CAM_UPD_WKFM3(skb->data, cam_info->mask[2]);
6774 RTW89_SET_WOW_CAM_UPD_WKFM4(skb->data, cam_info->mask[3]);
6775 RTW89_SET_WOW_CAM_UPD_CRC(skb->data, cam_info->crc);
6776 RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(skb->data,
6777 cam_info->negative_pattern_match);
6778 RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(skb->data,
6779 cam_info->skip_mac_hdr);
6780 RTW89_SET_WOW_CAM_UPD_UC(skb->data, cam_info->uc);
6781 RTW89_SET_WOW_CAM_UPD_MC(skb->data, cam_info->mc);
6782 RTW89_SET_WOW_CAM_UPD_BC(skb->data, cam_info->bc);
6784 RTW89_SET_WOW_CAM_UPD_VALID(skb->data, cam_info->valid);
6809 struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
6810 struct rtw89_wow_gtk_info *gtk_info = &rtw_wow->gtk_info;
6812 u8 macid = rtwvif->mac_id;
6819 if (!rtw_wow->gtk_alg)
6825 return -ENOMEM;
6829 h2c = (struct rtw89_h2c_wow_gtk_ofld *)skb->data;
6840 if (gtk_info->igtk_keyid) {
6849 h2c->w0 = le32_encode_bits(enable, RTW89_H2C_WOW_GTK_OFLD_W0_EN) |
6851 le32_encode_bits(gtk_info->igtk_keyid ? 1 : 0,
6855 h2c->w1 = le32_encode_bits(gtk_info->igtk_keyid ? pkt_id_sa_query : 0,
6857 le32_encode_bits(rtw_wow->akm, RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT);
6858 h2c->gtk_info = rtw_wow->gtk_info;
6882 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
6891 return -ENOMEM;
6923 return -EBUSY;
6926 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
6936 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
6944 return -ENOMEM;
6948 RTW89_SET_FWCMD_ADD_MCC_MACID(skb->data, p->macid);
6949 RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(skb->data, p->central_ch_seg0);
6950 RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(skb->data, p->central_ch_seg1);
6951 RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(skb->data, p->primary_ch);
6952 RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(skb->data, p->bandwidth);
6953 RTW89_SET_FWCMD_ADD_MCC_GROUP(skb->data, p->group);
6954 RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(skb->data, p->c2h_rpt);
6955 RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(skb->data, p->dis_tx_null);
6956 RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(skb->data, p->dis_sw_retry);
6957 RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(skb->data, p->in_curr_ch);
6958 RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(skb->data, p->sw_retry_count);
6959 RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(skb->data, p->tx_null_early);
6960 RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(skb->data, p->btc_in_2g);
6961 RTW89_SET_FWCMD_ADD_MCC_PTA_EN(skb->data, p->pta_en);
6962 RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(skb->data, p->rfk_by_pass);
6963 RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(skb->data, p->ch_band_type);
6964 RTW89_SET_FWCMD_ADD_MCC_DURATION(skb->data, p->duration);
6965 RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(skb->data, p->courtesy_en);
6966 RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(skb->data, p->courtesy_num);
6967 RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(skb->data, p->courtesy_target);
6975 cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_ADD_MCC);
6983 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
6991 return -ENOMEM;
6995 RTW89_SET_FWCMD_START_MCC_GROUP(skb->data, p->group);
6996 RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(skb->data, p->btc_in_group);
6997 RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(skb->data, p->old_group_action);
6998 RTW89_SET_FWCMD_START_MCC_OLD_GROUP(skb->data, p->old_group);
6999 RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(skb->data, p->notify_cnt);
7000 RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(skb->data, p->notify_rxdbg_en);
7001 RTW89_SET_FWCMD_START_MCC_MACID(skb->data, p->macid);
7002 RTW89_SET_FWCMD_START_MCC_TSF_LOW(skb->data, p->tsf_low);
7003 RTW89_SET_FWCMD_START_MCC_TSF_HIGH(skb->data, p->tsf_high);
7011 cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_START_MCC);
7019 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
7027 return -ENOMEM;
7031 RTW89_SET_FWCMD_STOP_MCC_MACID(skb->data, macid);
7032 RTW89_SET_FWCMD_STOP_MCC_GROUP(skb->data, group);
7033 RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(skb->data, prev_groups);
7049 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
7057 return -ENOMEM;
7061 RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(skb->data, group);
7062 RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(skb->data, prev_groups);
7077 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
7085 return -ENOMEM;
7089 RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(skb->data, group);
7106 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
7116 return -ENOMEM;
7120 RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(skb->data, req->group);
7121 RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(skb->data, req->macid_x);
7122 RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(skb->data, req->macid_y);
7130 cond = RTW89_MCC_WAIT_COND(req->group, H2C_FUNC_MCC_REQ_TSF);
7135 tmp = (struct rtw89_mac_mcc_tsf_rpt *)wait->data.buf;
7145 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
7158 return -ENOMEM;
7162 RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(skb->data, group);
7163 RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(skb->data, macid);
7164 RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(skb->data, map_len);
7165 RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(skb->data, bitmap, map_len);
7181 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
7189 return -ENOMEM;
7193 RTW89_SET_FWCMD_MCC_SYNC_GROUP(skb->data, group);
7194 RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(skb->data, source);
7195 RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(skb->data, target);
7196 RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(skb->data, offset);
7212 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
7220 return -ENOMEM;
7224 RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(skb->data, p->group);
7225 RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(skb->data, p->btc_in_group);
7226 RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(skb->data, p->start_macid);
7227 RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(skb->data, p->macid_x);
7228 RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(skb->data, p->macid_y);
7229 RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(skb->data,
7230 p->start_tsf_low);
7231 RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(skb->data,
7232 p->start_tsf_high);
7233 RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(skb->data, p->duration_x);
7234 RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(skb->data, p->duration_y);
7242 cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_MCC_SET_DURATION);
7257 slot_h2c->w0 = le32_encode_bits(slot_arg->duration,
7259 le32_encode_bits(slot_arg->courtesy_en,
7261 le32_encode_bits(slot_arg->role_num,
7263 slot_h2c->w1 = le32_encode_bits(slot_arg->courtesy_period,
7265 le32_encode_bits(slot_arg->courtesy_target,
7268 for (i = 0; i < slot_arg->role_num; i++) {
7269 slot_h2c->roles[i].w0 =
7270 le32_encode_bits(slot_arg->roles[i].macid,
7272 le32_encode_bits(slot_arg->roles[i].role_type,
7274 le32_encode_bits(slot_arg->roles[i].is_master,
7276 le32_encode_bits(slot_arg->roles[i].en_tx_null,
7282 slot_h2c->roles[i].w1 =
7283 le32_encode_bits(slot_arg->roles[i].central_ch,
7285 le32_encode_bits(slot_arg->roles[i].primary_ch,
7287 le32_encode_bits(slot_arg->roles[i].bw,
7289 le32_encode_bits(slot_arg->roles[i].band,
7291 le32_encode_bits(slot_arg->roles[i].null_early,
7297 slot_h2c->roles[i].macid_main_bitmap =
7298 cpu_to_le32(slot_arg->roles[i].macid_main_bitmap);
7299 slot_h2c->roles[i].macid_paired_bitmap =
7300 cpu_to_le32(slot_arg->roles[i].macid_paired_bitmap);
7304 return struct_size(slot_h2c, roles, slot_arg->role_num);
7322 for (i = 0; i < arg->slot_num; i++)
7323 len += rtw89_fw_h2c_mrc_add_slot(rtwdev, &arg->slots[i], NULL);
7328 return -ENOMEM;
7332 tmp = skb->data;
7339 h2c_head->w0 = le32_encode_bits(arg->sch_idx,
7341 le32_encode_bits(arg->sch_type,
7343 le32_encode_bits(arg->slot_num,
7345 le32_encode_bits(arg->btc_in_sch,
7349 for (i = 0; i < arg->slot_num; i++)
7351 tmp += rtw89_fw_h2c_mrc_add_slot(rtwdev, &arg->slots[i], tmp);
7353 tmp += rtw89_fw_h2c_mrc_add_slot(rtwdev, &arg->slots[i], (void *)tmp);
7366 return -EBUSY;
7375 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
7384 return -ENOMEM;
7388 h2c = (struct rtw89_h2c_mrc_start *)skb->data;
7390 h2c->w0 = le32_encode_bits(arg->sch_idx,
7392 le32_encode_bits(arg->old_sch_idx,
7394 le32_encode_bits(arg->action,
7397 h2c->start_tsf_high = cpu_to_le32(arg->start_tsf >> 32);
7398 h2c->start_tsf_low = cpu_to_le32(arg->start_tsf);
7406 cond = RTW89_MRC_WAIT_COND(arg->sch_idx, H2C_FUNC_START_MRC);
7412 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
7421 return -ENOMEM;
7425 h2c = (struct rtw89_h2c_mrc_del *)skb->data;
7427 h2c->w0 = le32_encode_bits(sch_idx, RTW89_H2C_MRC_DEL_W0_SCH_IDX);
7443 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
7451 len = struct_size(h2c, infos, arg->num);
7455 return -ENOMEM;
7459 h2c = (struct rtw89_h2c_mrc_req_tsf *)skb->data;
7461 h2c->req_tsf_num = arg->num;
7462 for (i = 0; i < arg->num; i++)
7463 h2c->infos[i] =
7464 u8_encode_bits(arg->infos[i].band,
7466 u8_encode_bits(arg->infos[i].port,
7479 tmp = (struct rtw89_mac_mrc_tsf_rpt *)wait->data.buf;
7496 return -ENOMEM;
7500 h2c = (struct rtw89_h2c_mrc_upd_bitmap *)skb->data;
7502 h2c->w0 = le32_encode_bits(arg->sch_idx,
7504 le32_encode_bits(arg->action,
7506 le32_encode_bits(arg->macid,
7508 h2c->w1 = le32_encode_bits(arg->client_macid,
7521 return -EBUSY;
7538 return -ENOMEM;
7542 h2c = (struct rtw89_h2c_mrc_sync *)skb->data;
7544 h2c->w0 = le32_encode_bits(true, RTW89_H2C_MRC_SYNC_W0_SYNC_EN) |
7545 le32_encode_bits(arg->src.port,
7547 le32_encode_bits(arg->src.band,
7549 le32_encode_bits(arg->dest.port,
7551 le32_encode_bits(arg->dest.band,
7553 h2c->w1 = le32_encode_bits(arg->offset, RTW89_H2C_MRC_SYNC_W1_OFFSET);
7565 return -EBUSY;
7580 len = struct_size(h2c, slots, arg->slot_num);
7584 return -ENOMEM;
7588 h2c = (struct rtw89_h2c_mrc_upd_duration *)skb->data;
7590 h2c->w0 = le32_encode_bits(arg->sch_idx,
7592 le32_encode_bits(arg->slot_num,
7597 h2c->start_tsf_high = cpu_to_le32(arg->start_tsf >> 32);
7598 h2c->start_tsf_low = cpu_to_le32(arg->start_tsf);
7600 for (i = 0; i < arg->slot_num; i++) {
7601 h2c->slots[i] =
7602 le32_encode_bits(arg->slots[i].slot_idx,
7604 le32_encode_bits(arg->slots[i].duration,
7618 return -EBUSY;
7640 (ent_sz) - __var_sz);\
7652 (ent_sz) - __var_sz);\
7662 if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
7665 if (e->band >= RTW89_BAND_NUM || e->bw >= RTW89_BYR_BW_NUM)
7668 switch (e->rs) {
7670 if (e->shf + e->len > RTW89_RATE_CCK_NUM)
7674 if (e->shf + e->len > RTW89_RATE_OFDM_NUM)
7678 if (e->shf + e->len > __RTW89_RATE_MCS_NUM ||
7679 e->nss >= RTW89_NSS_NUM ||
7680 e->ofdma >= RTW89_OFDMA_NUM)
7684 if (e->shf + e->len > RTW89_RATE_HEDCM_NUM ||
7685 e->nss >= RTW89_NSS_HEDCM_NUM ||
7686 e->ofdma >= RTW89_OFDMA_NUM)
7690 if (e->shf + e->len > __RTW89_RATE_OFFSET_NUM)
7704 const struct rtw89_txpwr_conf *conf = tbl->data;
7721 byr_head = &rtwdev->byr[entry.band][entry.bw];
7740 if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
7743 if (e->bw >= RTW89_2G_BW_NUM)
7745 if (e->nt >= RTW89_NTX_NUM)
7747 if (e->rs >= RTW89_RS_LMT_NUM)
7749 if (e->bf >= RTW89_BF_NUM)
7751 if (e->regd >= RTW89_REGD_NUM)
7753 if (e->ch_idx >= RTW89_2G_CH_NUM)
7762 const struct rtw89_txpwr_conf *conf = &data->conf;
7774 data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
7784 if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
7787 if (e->bw >= RTW89_5G_BW_NUM)
7789 if (e->nt >= RTW89_NTX_NUM)
7791 if (e->rs >= RTW89_RS_LMT_NUM)
7793 if (e->bf >= RTW89_BF_NUM)
7795 if (e->regd >= RTW89_REGD_NUM)
7797 if (e->ch_idx >= RTW89_5G_CH_NUM)
7806 const struct rtw89_txpwr_conf *conf = &data->conf;
7818 data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
7828 if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
7831 if (e->bw >= RTW89_6G_BW_NUM)
7833 if (e->nt >= RTW89_NTX_NUM)
7835 if (e->rs >= RTW89_RS_LMT_NUM)
7837 if (e->bf >= RTW89_BF_NUM)
7839 if (e->regd >= RTW89_REGD_NUM)
7841 if (e->reg_6ghz_power >= NUM_OF_RTW89_REG_6GHZ_POWER)
7843 if (e->ch_idx >= RTW89_6G_CH_NUM)
7852 const struct rtw89_txpwr_conf *conf = &data->conf;
7864 data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
7874 if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
7877 if (e->ru >= RTW89_RU_NUM)
7879 if (e->nt >= RTW89_NTX_NUM)
7881 if (e->regd >= RTW89_REGD_NUM)
7883 if (e->ch_idx >= RTW89_2G_CH_NUM)
7892 const struct rtw89_txpwr_conf *conf = &data->conf;
7904 data->v[entry.ru][entry.nt][entry.regd][entry.ch_idx] = entry.v;
7913 if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
7916 if (e->ru >= RTW89_RU_NUM)
7918 if (e->nt >= RTW89_NTX_NUM)
7920 if (e->regd >= RTW89_REGD_NUM)
7922 if (e->ch_idx >= RTW89_5G_CH_NUM)
7931 const struct rtw89_txpwr_conf *conf = &data->conf;
7943 data->v[entry.ru][entry.nt][entry.regd][entry.ch_idx] = entry.v;
7952 if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
7955 if (e->ru >= RTW89_RU_NUM)
7957 if (e->nt >= RTW89_NTX_NUM)
7959 if (e->regd >= RTW89_REGD_NUM)
7961 if (e->reg_6ghz_power >= NUM_OF_RTW89_REG_6GHZ_POWER)
7963 if (e->ch_idx >= RTW89_6G_CH_NUM)
7972 const struct rtw89_txpwr_conf *conf = &data->conf;
7984 data->v[entry.ru][entry.nt][entry.regd][entry.reg_6ghz_power]
7994 if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
7997 if (e->band >= RTW89_BAND_NUM)
7999 if (e->tx_shape_rs >= RTW89_RS_TX_SHAPE_NUM)
8001 if (e->regd >= RTW89_REGD_NUM)
8010 const struct rtw89_txpwr_conf *conf = &data->conf;
8022 data->v[entry.band][entry.tx_shape_rs][entry.regd] = entry.v;
8031 if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
8034 if (e->band >= RTW89_BAND_NUM)
8036 if (e->regd >= RTW89_REGD_NUM)
8045 const struct rtw89_txpwr_conf *conf = &data->conf;
8057 data->v[entry.band][entry.regd] = entry.v;
8065 struct rtw89_rfe_data *rfe_data = rtwdev->rfe_data;
8071 parms = &rfe_data->rfe_parms;
8075 if (rtw89_txpwr_conf_valid(&rfe_data->byrate.conf)) {
8076 rfe_data->byrate.tbl.data = &rfe_data->byrate.conf;
8077 rfe_data->byrate.tbl.size = 0; /* don't care here */
8078 rfe_data->byrate.tbl.load = rtw89_fw_load_txpwr_byrate;
8079 parms->byr_tbl = &rfe_data->byrate.tbl;
8082 if (rtw89_txpwr_conf_valid(&rfe_data->lmt_2ghz.conf)) {
8083 rtw89_fw_load_txpwr_lmt_2ghz(&rfe_data->lmt_2ghz);
8084 parms->rule_2ghz.lmt = &rfe_data->lmt_2ghz.v;
8087 if (rtw89_txpwr_conf_valid(&rfe_data->lmt_5ghz.conf)) {
8088 rtw89_fw_load_txpwr_lmt_5ghz(&rfe_data->lmt_5ghz);
8089 parms->rule_5ghz.lmt = &rfe_data->lmt_5ghz.v;
8092 if (rtw89_txpwr_conf_valid(&rfe_data->lmt_6ghz.conf)) {
8093 rtw89_fw_load_txpwr_lmt_6ghz(&rfe_data->lmt_6ghz);
8094 parms->rule_6ghz.lmt = &rfe_data->lmt_6ghz.v;
8097 if (rtw89_txpwr_conf_valid(&rfe_data->lmt_ru_2ghz.conf)) {
8098 rtw89_fw_load_txpwr_lmt_ru_2ghz(&rfe_data->lmt_ru_2ghz);
8099 parms->rule_2ghz.lmt_ru = &rfe_data->lmt_ru_2ghz.v;
8102 if (rtw89_txpwr_conf_valid(&rfe_data->lmt_ru_5ghz.conf)) {
8103 rtw89_fw_load_txpwr_lmt_ru_5ghz(&rfe_data->lmt_ru_5ghz);
8104 parms->rule_5ghz.lmt_ru = &rfe_data->lmt_ru_5ghz.v;
8107 if (rtw89_txpwr_conf_valid(&rfe_data->lmt_ru_6ghz.conf)) {
8108 rtw89_fw_load_txpwr_lmt_ru_6ghz(&rfe_data->lmt_ru_6ghz);
8109 parms->rule_6ghz.lmt_ru = &rfe_data->lmt_ru_6ghz.v;
8112 if (rtw89_txpwr_conf_valid(&rfe_data->tx_shape_lmt.conf)) {
8113 rtw89_fw_load_tx_shape_lmt(&rfe_data->tx_shape_lmt);
8114 parms->tx_shape.lmt = &rfe_data->tx_shape_lmt.v;
8117 if (rtw89_txpwr_conf_valid(&rfe_data->tx_shape_lmt_ru.conf)) {
8118 rtw89_fw_load_tx_shape_lmt_ru(&rfe_data->tx_shape_lmt_ru);
8119 parms->tx_shape.lmt_ru = &rfe_data->tx_shape_lmt_ru.v;